Maxscend-MXD86A0S

Part #	Maxscend-MXD86A0S
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MXD86A0S

SP10T Switch with MIPI for LTE Diversity

This document contains information that is confidential and proprietary to Maxscend Microelectronics

Company Limited (Maxscend) and may not be reproduced in any form without express written consent of

Maxscend. No

transfer or licensing of technology is implied by this document.

Page 1 of 10

Maxscend Confidential

MXD86A0S

–

SP10T Switch with MIPI for LTE Diversity

General Description

Features



Excellent insertion loss

The MXD86A0S is a low loss, high isolation SP10T

– 0.80

dB Insertion Loss at 2.7GHz

P0.1dB @ 27dBm

switch for antenna diversity receiving.



The MXD86A0S is compatible with MIPI control,

which is a key requirement for many cellular

transceivers. This part is packaged in a compact

2.4mm x 2.4mm, 20-pin, QFN package which

allows for a small solution size with no need for

external DC blocking capacitors (when no external

DC is applied to the device ports).

Multi-Band operation 700MHz to 3000MHz

RFFE serial control interface

Compact 2.4mm x 2.4mm in QFN-20

package



No DC blocking capacitors required (unless

external DC is applied to the RF ports)

Applications



2G/3G/4G antenna diversity

Cellular modems and USB Devices

Functional Block Diagram and Pin Function

RF1

RF2

RF3

RF4

RF5

ANT

RF6

Ground

Paddle

RF7

RF8

RF9

RF10

VIO

SCLK

VDD

Figure 1 Functional Block Diagram and Pinout (Top View)

Page 2 of 10

Maxscend Confidential

MXD86A0S

–

SP10T Switch with MIPI for LTE Diversity

Application Circuit

VDD

VIO

SDATA SCLK

VDD

GND

ANT

VIO

ANT

Ground

Paddle

SDATA

GND

SCLK

100pF

DN1

33nF

DN1

Figure 2 Evaluation Board Schematic

Table 1. Pin Description

Pin No.

Name

Description

Not Connect

RF port10

RF port9

RF port8

RF port7

RF port6

Ground

Pin No.

Name

RF5

RF4

RF3

RF2

RF1

GND

VDD

VIO

Description

RF port5

RF port4

RF port3

RF port2

RF port1

Ground

Power supply

Supply voltage for MIPI

RF10

RF9

RF8

RF7

RF6

GND

ANT

GND

Ground

Antenna port

Ground

SDATA MIPI

data input/output

SCLK MIPI

clock

Ground

Paddle

GND

Ground

Note:

Bottom ground paddles must be connected to ground.

Page 3 of 10

Maxscend Confidential

MXD86A0S

–

SP10T Switch with MIPI for LTE Diversity

Truth Table

Table 2.

Register_0

State

Mode

ISO

RF1 on

RF2 on

RF3 on

RF4 on

RF5 on

RF6 on

RF7 on

RF8 on

RF9 on

RF10 on

Recommended Operation Range

Table 3. Recommended Operation Condition

Parameters

Operation Frequency

Symbol

Min

0.7

Typ

–

Max

3.0

Units

GHz

Power supply

2.5

2.8

1.8

3.0

Power supply for MIPI

MIPI Control Voltage High

MIPI Control Voltage Low

1.65

0.8*VIO

1.95

0.3

Specifications

Table 4. Electrical Specifications

Parameter

DC Specifications

Supply voltage

Symbol

Test Condition

Min

Typical Max Units

2.5

2.8

3.0

Supply current

1.8

1.95

supply voltage

Supply current

1.65

SDATA, SCLK control voltage: High

Low

CTL

0.8* V

1.95

0.3

Switching Speed, one RF to another

10% to 90% RF

RF Specifications

0.1 to 1.0 GHz

1.0 to 2.0 GHz

2.0 to 2.7 GHz

0.1 to 1.0 GHz

1.0 to 2.0 GHz

2.0 to 2.7 GHz

0.1 to 1.0 GHz

1.0 to 2.0 GHz

2.0 to 2.7 GHz

0.60

0.70

0.80

0.70

0.85

1.00

Insertion loss (ANT pin to

RF1/2/3/4/5/6/7/8/9/10 pins)

Isolation (ANT pin to

RF1/2/3/4/5/6/7/8/9/10 pins)

Iso

Input return loss (ANT pin to

RF1/2/3/4/5/6/7/8/9/10 pins)

0.1 dB Compression Point (ANT pin

to RF1/2/3/4/5/6/7/8/9/10 pins)

P0.1dB

0.7 GHz to 3.0 GHz

+26

+27

dBm

Page 4 of 10

Maxscend Confidential

MXD86A0S

–

SP10T Switch with MIPI for LTE Diversity

MIPI Read and Write Timing

MIPI supports the following Command Sequences:

•

• Register_0 Write

• Register Read

Figures 3 and 4 provide the timing diagrams for register write commands and read commands, respectively.

Figure 5 shows the Register 0 Write Command Sequence. Refer to the MIPI Alliance Specification for RF

Front-End Control Interface (RFFE), v1.10 (26 July 2011) for additional information on MIPI USID

programming sequences and MIPI bus specifications.

CLK

SA3

SA2

SA1

SA0

Data

SSC

CLK

Data

Bus

Park

Data Frame

Signal driven by Master

Signal not driven, pull down only

For reference only

Figure 3 Register Write Command Sequence

CLK

SA3

SA2

SA1

SA0

Data

SSC

CLK

Data

Bus

Park

Bus

Park

Data Frame (from Slave)

Signal driven by Master

Signal driven by Slave

Signal not driven, pull down only by Master

For reference only

Figure 4 Register Read Command Sequence

Page 5 of 10

Maxscend Confidential

MXD86A0S

–

SP10T Switch with MIPI for LTE Diversity

In the timing figures, SA[3:0] is slave address.

A[4:0] is register address.

D[7:0] is data. “P” is odd parity

bit.

Figure shows the Register 0 Write Command Sequence. The Command Sequence starts with an SSC,

followed by the Register 0 Write Command Frame containing the Slave address, a logic one, and a seven

bit word to be written to Register 0. The Command Sequence ends with a Bus Park Cycle.

CLK

SA3

SA2

SA1

SA0

Data

Bus

Park

Parity

SSC

Slave Address

Data

Signal driven by Master

Signal not driven, pull down only

For reference only

Figure 5 Register 0 Write Command Sequence

Page 6 of 10

Maxscend Confidential

MXD86A0S

–

SP10T Switch with MIPI for LTE Diversity

Table 5. Register definition table

BROADC

AST_ID

support

Address

Name

Data

Bits

Trigger

support

R/W

Function

Description

Default

0x00

REGISTER_0

GROUP_SID

7:0

R/W

RF Control

Register_0 truth Table: Table 2

Yes

7:4

3:0

RESERVED

GSID

0x0

0x001B

R/W

Group Slave ID

00: Normal Operation (ACTIVE)

01: Reset all registers to default settings

(STARTUP)

10: Low power (LOW POWER)

11: Reserved

7:6

R/W

PWR_MODE

0b10

Yes

Note: Write PWR_MODE=2

’

h1 will reset all

state.

R/W

Trigger_Mask_2

Trigger_Mask_1

If this bit is set, trigger 2 is disabled

If this bit is set, trigger 1 is disabled

If this bit is set, trigger 0 is disabled

Note: When all triggers are disabled, writing

to a register that is associated with trigger 0,

1, or 2, causes the data to go directly to the

destination register.

0x001C

PM_TRIG

R/W

Trigger_Mask_0

A write of a one to this bit loads trigger 2’s

registers

Trigger_2

Trigger_1

Yes

A write of a one to this bit loads trigger 1’s

registers

A write of a one to this bit loads trigger 0’s

registers

Trigger_0

Note: Trigger processed immediately then

cleared. Trigger 0, 1, and 2 will always read

as 0.

Yes

0x001D

0x001E

PRODUCT_ID

7:0

7:6

5:4

3:0

PRODUCT_ID

Product Number

0x5d

0x81

0b00

0b11

0xb

MANUFACTU

RER_ID

MANUFACTUR

ER_ID[7:0]

Lower eight bits of MIPI registered

Manufacturer ID

RESERVED

MANUFACTUR

ER_ID[9:8]

Upper two bits of MIPI registered

Manufacturer ID

0x001F

MAN_USID

R/W

USID

USID of the device.

Page 7 of 10

Maxscend Confidential

MXD86A0S

–

SP10T Switch with MIPI for LTE Diversity

Absolute Maximum Ratings

Table 6. Maximum ratings

Parameters

Supply voltage

Symbol

Minimum

+2.0

Maximum

+3.3

Units

Supply voltage for MIPI

MIPI Control voltage

(SDATA, SCLK)

RF input power (RF1 to

RF10)

+1.0

+2.0

CTL

+2.0

+28

dBm

Operating temperature

Storage temperature

STG

–

+85

+125

℃

Electrostatic Discharge

Human

(HBM), Class 1C

Machine Model (MM),

Class A

Charged device model

(CDM), Class III

body

model

ESD_HBM

ESD_MM

ESD_CDM

1000

100

500

Note:

Exposure to maximum rating conditions for extended periods may reduce device reliability. There is no damage to device with

only one parameter set at the limit and all other parameters set at or below their nominal value. Exceeding any of the limits listed

here may result in permanent damage to the device

Power ON and OFF sequence

Here is the recommendation about power-on/off sequence in order to avoid damaging the device.

Power ON

1) Apply voltage supply – V

2) Apply logic supply – V

3) Wait 10μs or greater and then apply

MIPI bus signals

–

SCLK and SDATA

4) Wait 5μs or greater after

MIPI bus goes idle and then apply the RF Signal

Power OFF

1) Remove the RF Signal

2) Remove MIPI bus

–

SCLK and SDATA

3) Remove logic supply – V

4) Remove voltage supply – V

VIO

OFF

VIO

OFF

VDD

OFF

VDD

MIPI

Trigger

≥

100us

≥

100us

SHUTDOWN

STARTUP

≥

10us

SHUTDOWN

ACTIVE

Slave State

SDATA,SCLK

RF Signal

≥

5us

Note

: VIO can be applied to the device before VDD or removed after VDD.

It is important to wait 10μs after

VIO &

VDD are applied before sending SDATA

to ensure correction data transmission.

The

minimum time between a power up and power down sequence (and vice versa) is ≥ 100

us.

Page 8 of 10

Maxscend Confidential

MXD86A0S

–

SP10T Switch with MIPI for LTE Diversity

Package Outline Dimension

Figure 6

package outline dimension

Page 9 of 10

Maxscend Confidential

MXD86A0S

–

SP10T Switch with MIPI for LTE Diversity

Reflow Chart

Critical Zone

to T

Ramp-up

max

min

Ramp-down

Preheat

t 25

℃

to Peak

Time

Figure 7 Recommended Lead-Free Reflow Profile

Table 7. Reflow condition

Profile Parameter

Lead-Free Assembly, Convection, IR/Convection

Ramp-up rate

（

max

to T

）

Preheat temperature

（

min

to TS

max

Preheat time

（

）

Time above TL , 217

℃（

）

Peak temperature

（

）

℃

/second max.

150

℃

to 200

℃

60 – 180 seconds

60 – 150 seconds

260

℃

）

Time within 5

℃

of peak temperature(t

)

Ramp-down rate

Time 25

℃

to peak temperature

20 – 40 seconds

℃

/second max.

8 minutes max.

ESD Sensitivity

Integrated circuits are ESD sensitive and can be damaged by static electric charge. Proper ESD

protection techniques should be used when handling these devices.

RoHS Compliant

This product does not contain lead, mercury, cadmium, hexavalent chromium, polybrominated biphenyls

(PBB) and polybrominated diphenyl ethers (PBDE), and are considered RoHS compliant.

1.4.1

Page 10 of 10

Maxscend Confidential

Maxscend-MXD86A0S

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