onsemi-NTGS4141NT1G
| Part # | onsemi-NTGS4141NT1G |
Download  | onsemi-NTGS4141NT1G |
NTGS4141N, NVGS4141N
MOSFET
– Powe
r
,
S
ingle,
N-Channel, TSOP-6
30
V
,
7
.0 A
Features
•
Low R
DS(on)
•
Low Gate Charge
•
NV Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC
−
Q101 Qualified and
PPAP Capable
•
Pb
−
Free Package is Available
V
R
TYP
I MAX
D
(BR)DSS
DS(on)
21.5 m
W
@ 10 V
30 m
W
@ 4.5 V
30 V
7.0 A
Applications
•
Load Switch
•
Notebook PC
•
Desktop PC
N
−
Channel
Drain 1
2 5 6
MAXIMUM RATINGS
(T =
25
°
C unless otherwise noted)
J
Rating
Drain
−
to
−
Source Voltage
Gate
−
to
−
Source Voltage
Symbol Value
Unit
V
Gate 3
V
DSS
30
20
V
GS
V
Continuous Drain
Current (Note 1)
Steady T
= 25
°
C
I
5.0
3.6
7.0
1.0
A
A
D
Source
4
State
T =
85
°
C
A
MARKING
DIAGRAM
t
≤
10 s
T =
25
°
C
A
Power Dissipation
(Note 1)
Steady T
= 25
°
C
P
W
A
D
TSOP
−
6
CASE 318G
STYLE 1
State
t
≤
10 s
2.0
3.5
2.5
0.5
XX M
G
1
Continuous Drain
Current (Note 2)
Steady T
= 25
°
C
I
D
A
G
A
State
T =
85
°
C
A
Power Dissipation
(Note 2)
T =
25
°
C
A
P
W
D
XX
M
G
= Device Code
= Date Code
= Pb
−
Free Package
Pulsed Drain Current
Pulsed Drain Current
t =
10
m
s, V
=10V
I
45
30
A
A
p
GS
DM
(Note: Microdot may be in either location)
t =
30
m
s, V
=5V
I
D
p
GS
Operating Junction and Storage
T
e
mperature
T ,
STG
−
55 to
150
°
C
J
T
PIN ASSIGNMENT
Source Current (Body Diode)
I
2.0
54
A
S
Drain Drain Source
6
5
4
Single Pulse Drain
−
to
−
Source Avalanche Energy
EAS
mJ
(V =
30
V
, I
=
1
0.4 A, V
= 10
V
,
DD
L
G
GS
L = 1.0 mH, R
= 25
W
)
Lead
T
e
mperature for Soldering Purposes
(1/8
″
from case for 10 s)
T
L
260
°
C
1
2
3
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
Drain Drain
Gate
THERMAL RESISTANCE RATINGS
ORDERING INFORMATION
See detailed ordering and shipping information ion page 6 of
this data sheet.
Rating
Symbol
Max
125
62.5
248
Unit
Junction
−
to
−
Ambient – Steady State (Note 1)
Junction
−
to
−
Ambient – t
≤
10 s (Note 1)
Junction
−
to
−
Ambient – Steady State (Note 2)
R
R
R
°
C/W
θ
θ
θ
JA
JA
JA
1. Surface
−
mounted on FR4 board using 1 inch sq pad size
(Cu area = 1.127 in sq [1 oz] including traces).
©
Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
May,2019
−
Rev. 6
NTGS4141N/D
NTGS4141N, NVGS4141N
2. Surface
−
mounted on FR4 board using the minimum recommended pad size
(Cu area = 0.0773 in sq).
2
NTGS4141N, NVGS4141N
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise noted)
J
Characteristic
OFF CHARACTERISTICS
Symbol
Test Condition
Min
Typ
Max
Unit
Drain
−
to
−
Source Breakdown Voltage
V
V
GS
= 0
V
, I
= 250
m
A
30
V
(BR)DSS
D
Drain
−
to
−
Source Breakdown Voltage
T
e
mperature Coefficient
V
/T
J
18.4
mV/
°
C
(BR)DSS
Zero Gate Voltage Drain Current
I
T =
25
°
C
1.0
10
m
A
DSS
J
V
= 0
V
,
= 24 V
GS
DS
V
T =
125
°
C
J
Gate
−
to
−
Source Leakage Current
ON CHARACTERISTICS
(Note 3)
Gate Threshold Voltage
I
V
= 0
V
, V
=
20 V
100
nA
GSS
DS
GS
V
V
GS
= V
, I
= 250
m
A
1.0
3.0
V
GS(TH)
DS
D
Negative Threshold
T
e
mperature Coefficient
V
/T
5.7
21.5
30
mV/
°
C
m
W
GS(TH)
J
Drain
−
to
−
Source On Resistance
R
V
= 10 V, I
= 7.0 A
25
35
DS(on)
GS
D
V
GS
= 4.5
V
, I
= 6.0 A
D
Forward Transconductance
g
FS
V
DS
= 10 V, I
= 7.0 A
30
S
D
CHARGES, CAPACITANCES AND GATE RESISTANCE
Input Capacitance
C
560
115
75
pF
ISS
V
= 0
V
, f =
1
.0 MHz,
GS
Output Capacitance
C
OSS
C
RSS
V
= 24 V
DS
Reverse Transfer Capacitance
T
o
tal Gate Charge
Q
12
nC
nC
G(TOT)
Threshold Gate Charge
Gate
−
to
−
Source Charge
Gate
−
to
−
Drain Charge
T
o
tal Gate Charge
Q
0.85
1.9
3.0
6.0
0.8
1.85
3.0
2.8
G(TH)
V
GS
= 10
V
, V
=
1
5 V,
DS
I
D
= 7.0 A
Q
GS
Q
GD
Q
G(TOT)
Threshold Gate Charge
Gate
−
to
−
Source Charge
Gate
−
to
−
Drain Charge
Gate Resistance
Q
G(TH)
V
GS
= 4.5
V
, V
= 15 V,
DS
I
D
= 7.0 A
Q
GS
GD
Q
R
W
G
SWITCHING CHARACTERISTICS
(Note 4)
Turn
−
On Delay Time
t
6.0
15
ns
d(ON)
Rise Time
t
r
V
= 10
V
, V
=
2
4 V,
DS
GS
D
I
= 7.0 A, R
= 3.0
W
G
Turn
−
Off Delay Time
t
18
d(OFF)
Fall Time
t
f
4.0
DRAIN
−
SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
T =
25
°
C
0.78
0.63
15
1.0
V
SD
J
V
S
= 0
V
,
GS
I =
2.0 A
T =
125
°
C
J
Reverse Recovery Time
Charge Time
t
ns
RR
t
t
9.0
6.0
8.0
a
V
GS
= 0 V
dI /dt
= 100 A/
m
s, I
= 2.0 A
S
S
Discharge Time
b
Reverse Recovery Charge
Q
nC
RR
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Pulse
T
e
st: pulse width
v
300
m
s, duty cycle
v
2%.
4. Switching
characteristics are independent of operating junction temperatures.
3
NTGS4141N, NVGS4141N
TYPICAL PERFORMANCE CURVES
15
10
15
10 V
6 V
T =
25
°
C
J
V
DS
≥
10 V
3.5 V
4.5 V
10
3 V
5
0
5
0
125
°
C
25
°
C
2.6 V
T =
−
55
°
C
J
0
2
4
6
8
10
1
2
3
4
5
V
GS
, GATE
−
TO
−
SOURCE VOLTAGE (VOLTS)
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (VOLTS)
Figure 1. On
−
Region Characteristics
Figure 2. Transfer Characteristics
0.05
0.04
0.03
0.05
0.04
T =
25
°
C
J
T =
25
°
C
D
J
I
= 7 A
V
= 4.5 V
= 10 V
0.03
0.02
0.01
GS
0.02
0.01
0
V
GS
0
2
4
6
8
10
0
5
10
15
V
GS,
GATE
−
TO
−
SOURCE VOLTAGE (VOLTS)
I
D,
DRAIN CURRENT (AMPS)
Figure 4. On
−
Resistance vs. Drain Current and
Figure 3. On
−
Resistance vs. Gate
−
to
−
Source
Gate Voltage
Voltage
2.0
10000
1000
I
V
= 7 A
V
GS
= 0 V
D
= 10 V
GS
1.5
1.0
T =
150
°
C
J
100
10
T =
125
°
C
J
0.5
0
−
50
−
25
0
25
50
75
100
125
150
0
5
10
15
20
25
30
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (VOLTS)
T , JUNCTION TEMPERATURE (
°
C)
J
Figure 5. On
−
Resistance Variation with
Figure 6. Drain
−
to
−
Source Leakage Current
Temperature
vs. Voltage
4
NTGS4141N, NVGS4141N
TYPICAL PERFORMANCE CURVES
10
1200
1000
T =
25
°
C
QT
V
DS
= 0 V
V
GS
= 0 V
J
8
6
C
iss
V
GS
800
600
400
C
iss
4
Q
Q
GD
GS
C
rss
I
V
= 7 A
2
0
D
200
0
C
oss
= 15 V
DD
T =
25
°
C
J
C
rss
10
5
0
5
10
15
20
25
0
2
4
6
8
10
12
Q ,
TOTAL GATE CHARGE (nC)
G
V
GS
V
DS
Figure 8. Gate
−
To
−
Source and
Drain
−
To
−
Source Voltage vs. Total Charge
GATE
−
TO
−
SOURCE OR DRAIN
−
TO
−
SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
1000
7
V
I
= 24 V
= 7 A
= 10 V
V
= 0 V
DD
GS
T =
25
°
C
J
6
5
4
3
2
D
V
GS
t
d(off)
100
10
1
t
f
t
r
t
d(on)
1
0
1
10
100
0
0.1 0.2
0.3 0.4
0.5 0.6 0.7 0.8 0.9
R ,
GATE RESISTANCE (OHMS)
G
V
SD
, SOURCE
−
TO
−
DRAIN VOLTAGE (VOLTS)
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
100
60
40
I
D
= 10.4 A
10
m
s
10
1
100
m
s
1 ms
0 V
≤
V
≤
20 V
GS
10 ms
SINGLE PULSE
20
0
T
= 25
°
C
C
0.1
R
LIMIT
DS(on)
dc
THERMAL LIMIT
PACKAGE LIMIT
0.01
25
50
75
100
125
150
0.1
1
10
100
T , STARTING JUNCTION TEMPERATURE (
°
C)
J
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (VOLTS)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
5
NTGS4141N, NVGS4141N
TYPICAL PERFORMANCE CURVES
2.5
2.25
2.0
8.0
7.5
References is T
–
J
References is T
–
J
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
= 150
°
C
max
= 150
°
C
max
R
, t < 10 s, 1 sq in
q
JA
1.75
1.5
R
, 1 sq in
q
JA
R
, t < 10 s, 1 sq in
q
JA
R
, 1 sq in
1.25
1.0
q
JA
R
, min pad
q
JA
0.75
0.5
R
, min pad
0.25
0
q
JA
0
20
40
60
80
100 120
140
160
0
20
40
60
80
100 120
140
160
T ,
AMBIENT TEMPERATURE (
°
C)
A
T ,
AMBIENT TEMPERATURE (
°
C)
A
Figure 13. Maximum Power Derating Chart
Figure 14. Current Derating Chart
1000
D = 0.5
100
10
0.2
0.1
0.05
0.02
1
0.01
0.1
0.01
Single Pulse
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
t, PULSE TIME (s)
Figure 15. Thermal Response
Table 1. ORDERING INFORMATION
Marking
(XX)
†
Part Number
NTGS4141NT1
Package
Shipping
S4
S4
TSOP
−
6
3000 /
T
a
pe & Reel
3000 /
T
a
pe & Reel
NTGS4141NT1G
TSOP
−
6
(Pb
−
Free)
NVGS4141NT1G
VS4
TSOP
−
6
(Pb
−
Free)
3000 /
T
a
pe & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our
T
a
pe and Reel Packaging
Specifications Brochure, BRD8011/D.
6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSOP
−
6
CASE 318G
−
02
ISSUE V
1
DATE 12 JUN 2012
SCALE 2:1
NOTES:
D
1. DIMENSIONING
AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING
DIMENSION: MILLIMETERS.
H
3. MAXIMUM
LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM
LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS
D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D
AND E1 ARE DETERMINED AT DATUM H.
6
1
5
4
L2
GAUGE
PLANE
E1
E
5. PIN
ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.
2
3
L
MILLIMETERS
SEATING
C
M
NOTE 5
DIM
A
A1
b
c
D
E
E1
e
MIN
0.90
0.01
0.25
0.10
2.90
2.50
1.30
0.85
0.20
NOM
1.00
MAX
1.10
0.10
0.50
0.26
3.10
3.00
1.70
1.05
0.60
PLANE
b
DETAIL Z
e
0.06
0.38
0.18
3.00
c
2.75
A
0.05
1.50
0.95
L
0.40
A1
L2
M
0.25 BSC
−
DETAIL Z
0
°
1
0
°
STYLE 1:
STYLE 2:
PIN 1.
EMITTER 2
2. BASE
1
STYLE 3:
PIN 1.
ENABLE
2. N/C
STYLE 4:
PIN 1.
N/C
2. V
in
STYLE 5:
PIN 1.
EMITTER 2
2. BASE
2
STYLE 6:
PIN 1.
DRAIN
2. DRAIN
PIN 1.
COLLECTOR
2. COLLECTOR
3. BASE
3. GATE
3. COLLECTOR
1
4. EMITTER
1
5. BASE
2
3. R
BOOST
4. Vz
5. V
in
6. V
out
3. NOT
USED
4. GROUND
5. ENABLE
6. LOAD
3. COLLECTOR
1
4. EMITTER
1
5. BASE
1
4. SOURCE
5. DRAIN
6. DRAIN
4. EMITTER
5. COLLECTOR
6. COLLECTOR
6. COLLECTOR
2
6. COLLECTOR
2
STYLE 7:
STYLE 8:
PIN 1.
Vbus
2. D(in)
STYLE 9:
STYLE 10:
PIN 1.
D(OUT)+
2. GND
STYLE 11:
STYLE 12:
PIN 1.
I/O
2. GROUND
3. I/O
PIN 1.
COLLECTOR
2. COLLECTOR
3. BASE
PIN 1.
LOW VOLTAGE GATE
2. DRAIN
PIN 1.
SOURCE 1
2. DRAIN
2
3. D(in)+
4. D(out)+
5. D(out)
6. GND
3. SOURCE
3. D(OUT)
−
4. D(IN)
−
5. VBUS
6. D(IN)+
3. DRAIN
2
4. N/C
5. COLLECTOR
6. EMITTER
4. DRAIN
4. SOURCE
2
5. GATE
1
4. I/O
5. DRAIN
5. VCC
6. I/O
6. HIGH
VOLTAGE GATE
6. DRAIN
1/GATE 2
STYLE 13:
STYLE 14:
PIN 1.
ANODE
2. SOURCE
3. GATE
STYLE 15:
PIN 1.
ANODE
2. SOURCE
3. GATE
STYLE 16:
STYLE 17:
PIN 1.
EMITTER
2. BASE
PIN 1.
GATE 1
2. SOURCE
2
3. GATE
2
PIN 1.
ANODE/CATHODE
2. BASE
3. EMITTER
3. ANODE/CATHODE
4. ANODE
5. CATHODE
6. COLLECTOR
4. DRAIN
2
5. SOURCE
1
6. DRAIN
1
4. CATHODE/DRAIN
4. DRAIN
4. COLLECTOR
5. ANODE
5. CATHODE/DRAIN
6. CATHODE/DRAIN
5. N/C
6. CATHODE
6. CATHODE
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
6X
0.60
XXXAYW
G
XXX M
G
G
G
1
1
6X
0.95
3.20
IC
STANDARD
XXX =
Specific Device Code
XXX =
Specific Device Code
A
Y
W
G
=Assembly Location
=
Y
e
ar
= Work Week
M
G
= Date Code
= Pb
−
Free Package
0.95
PITCH
= Pb
−
Free Package
DIMENSIONS: MILLIMETERS
*For additional information on our Pb
−
Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting
T
e
chniques Reference Manual, SOLDERRM/D.
*This information is generic. Please refer to device data sheet
for actual part marking. Pb
−
Free indicator, “G” or microdot “
G
”, may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB14888C
TSOP
−
6
PAGE 1 OF 1
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:
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T
o
ll Free USA/Canada
Phone: 011 421 33 790 2910
Europe, Middle East and Africa Technical Support:
Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative
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