Texas-Instruments-TPS1100DR
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T
P
S1100, TPS1100Y
S
I
NGLE
P
-CHANNEL ENHANCE
M
E
NT-
M
O
DE
M
O
SFETS
SLVS078C – DECEMBER 1993 – REVISED AUGUST 1995
D OR PW PACKAGE
Low r
. . . 0.18
Ω
Typ at V
=
–
1
0 V
DS(on)
GS
(TOP VIEW)
3 V Compatible
Requires No External V
SOURCE
SOURCE
SOURCE
GATE
DRAIN
DRAIN
DRAIN
DRAIN
1
2
3
4
8
7
6
5
CC
TTL and CMOS Compatible Inputs
=
–
1
.5 V Max
V
GS(th)
Available in Ultrathin TSSOP Package (PW)
ESD Protection Up to 2 kV Per
MIL-STD-883C, Method 3015
D PACKAGE
PW PACKAGE
description
The TPS1100 is
a
single P-channel
enhancement-mode MOSFE
T
.
T
he device has
been optimized for 3-V or 5-V power distribution
in battery-powered systems by means of
T
e
xas
Instruments LinBiCMOS
process. With
a
schematic
maximum V
of
–
1
.5 V and an I
of only
GS(th)
DSS
SOURCE
0.5
µ
A, the TPS1100 is the ideal high-side switch
for low-voltage, portable battery-management
system
s
w
her
e
m
aximizin
g
b
atter
y
l
if
e
i
s
a
p
rimary
concern. The low r
and excellent ac
DS(on)
ESD-
characteristics (rise time 10 ns typical) make the
TPS1100 the logical choice for low-voltage
switching applications such as power switches for
pulse-width-modulated (PWM) controllers or
motor/bridge drivers.
Protection
Circuitry
GATE
The ultrathin thin shrink small-outline package or
TSSOP (PW) version with its smaller footprint and
reduction in height fits in places where other
P-channel MOSFE
T
s
c
annot. The size advantage
is especially important where board real estate is
at a premium and height restrictions do not allow
for a small-outline integrated circuit (SOIC)
package.
DRAIN
NOTE A:
For all applications, all source pins should be connected
and all drain pins should be connected.
AVAILABLE OPTIONS
PACKAGED DEVICES
SMALL OUTLINE
PLASTIC DIP
CHIP FORM
(Y)
T
A
(D)
(P)
–
4
0
°
C to 85
°
C
TPS1100D
TPS1100PWLE
TPS1100Y
The D package is available taped and reeled. Add an R suffix to device type (e.g.,
TPS1100DR). The PW package is available only left-end taped and reeled
(indicated by the LE suffix on the device type; e.g., TPS1100PWLE). The chip form
is tested at 25
°
C.
Caution. This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic
fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to
MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to these high-impedance circuits.
LinBiCMOS is a trademark of
T
e
xas Instruments Incorporated.
Copyright 1995,
T
e
xas Instruments Incorporated
PRODUCTION D
A
TA
i
nformation is current as of publication date.
Products conform to specifications per the terms of
T
e
xas
I
n
struments
standard
w
a
rrant
y
.
P
roduction processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303
•
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T
P
S1100, TPS1100Y
S
I
NGLE
P
-CHANNEL ENHANCE
M
E
NT-
M
O
DE
M
O
SFETS
SLVS078C – DECEMBER 1993 – REVISED AUGUST 1995
description (continued)
Such applications include notebook computers, personal digital assistants (PDAs), cellular telephones, and
PCMCIA cards. For existing designs, the D-packaged version has a pinout common with other p-channel
MOSFE
T
s
i
n SOIC packages.
TPS1100Y chip information
This chip, when properly assembled, displays characteristics similar to the TPS1100. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
(4)
(1)
(2)
(3)
(4)
(8)
(7)
(6)
(5)
SOURCE
DRAIN
SOURCE
SOURCE
DRAIN
DRAIN
TPS1100Y
(5)
(6)
GATE
DRAIN
(3)
57
CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4
×
4 MILS MINIMUM
T max
= 150
°
C
J
(1)
(2)
(8)
(7)
TOLERANCES ARE
±
10%
ALL DIMENSIONS ARE IN MILS
64
2
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T
P
S1100, TPS1100Y
S
I
NGLE
P
-CHANNEL ENHANCE
M
E
NT-
M
O
DE
M
O
SFETS
SLVS078C – DECEMBER 1993 – REVISED AUGUST 1995
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
UNIT
Drain-to-source voltage, V
–15
2 or –15
±
0.41
±
0.28
±
0.4
V
V
DS
Gate-to-source voltage, V
GS
T
= 25
°
C
= 125
°
C
= 25
°
C
= 125
°
C
= 25
°
C
= 125
°
C
= 25
°
C
= 125
°
C
= 25
°
C
= 125
°
C
= 25
°
C
= 125
°
C
= 25
°
C
= 125
°
C
= 25
°
C
= 125
°
C
= 25
°
C
= 25
°
C
A
D package
PW package
D package
PW package
D package
PW package
D package
PW package
T
A
V
GS
V
GS
V
GS
V
GS
=
–
2
.7 V
=
–
3 V
T
A
T
A
±
0.23
±
0.6
T
A
T
A
±
0.33
±
0.53
±
0.27
±
1
T
A
T
A
‡
Continuous drain current (T
= 150
°
C), I
A
J
D
T
A
T
A
±
0.47
±
0.81
±
0.37
±
1.6
=
–
4
.5 V
=
–
1
0 V
T
A
T
A
T
A
T
A
±
0.72
±
1.27
±
0.58
±
7
T
A
T
A
‡
Pulsed drain current, I
T
A
A
D
Continuous source current (diode conduction), I
T
A
–1
A
S
Storage temperature range, T
stg
–
5
5 to 150
°
C
°
C
°
C
°
C
Operating junction temperature range, T
–
4
0 to 150
–
4
0 to 125
260
J
Operating free-air temperature range, T
A
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡
Maximum values are calculated using a derating factor based on R
= 158
°
C
/
W
f
or the D package and R
= 248
°
C
/
W
f
or the PW package.
θ
JA
θ
JA
These devices are mounted on a FR4 board with no special thermal considerations.
DISSIPATION RATING TABLE
‡
T
≤
25
°
C
DERATING FACTOR
T
= 70
°
C
T
= 85
°
C
T =
125
°
C
A
A
A
A
PACKAGE
POWER RATING
ABOVE T
= 25
°
C
POWER RATING
POWER RATING
POWER RATING
A
D
791 mW
6.33 mW/
°
C
4.03 mW/
°
C
506 mW
323 mW
411 mW
262 mW
158 mW
101 mW
PW
504 mW
‡
Maximum values are calculated using a derating factor based on R
for the PW package. These devices are mounted on an FR4 board with no special thermal considerations when tested.
= 158
°
C
/
W
f
or the D package and R
= 248
°
C
/
W
θ
JA
θ
JA
3
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•
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T
P
S1100, TPS1100Y
S
I
NGLE
P
-CHANNEL ENHANCE
M
E
NT-
M
O
DE
M
O
SFETS
SLVS078C – DECEMBER 1993 – REVISED AUGUST 1995
electrical characteristics at T
= 25
°
C (unless otherwise noted)
J
static
TPS1100
TYP
TPS1100Y
TYP MAX
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
MIN
Gate-to-source
threshold voltage
V
V
V
= V
,
I =
–
2
50
µ
A
D
–1 –
1
.25
–
1
.50
–
1
.25
V
GS(th)
DS
GS
Source-to-drain voltage
(diode-forward
I
S
=
–
1
A
,
V
GS
= 0 V
–
0
.9
–
0
.9
V
SD
†
voltage)
Reverse gate current,
drain short circuited to
source
I
I
V
V
= 0
V
,
V
V
=
–
1
2 V
= 0 V
±
100
nA
GSS
DS
GS
T =
25
°
C
–
0
.5
–
1
0
Zero-gate-voltage drain
current
J
=
–
1
2
V
,
µ
A
DSS
DS
GS
T =
125
°
C
J
V
V
V
V
=
–
1
0 V
=
–
4
.5 V
=
–
3 V
I
I
=
–
1
.5 A
=
–
0
.5 A
180
180
291
476
606
GS
GS
GS
GS
D
291
476
606
400
700
850
Static drain-to-source
on-state resistance
D
r
m
Ω
DS(on)
†
I
=
–
0
.2 A
=
–
2 A
D
D
=
–
2
.7 V
Forward
transconductance
g
V
DS
=
–
1
0 V,
I
2.5
2.5
S
fs
†
†
Pulse test: pulse duration
≤
300
µ
s, duty cycle
≤
2%
dynamic
TPS1100, TPS1100Y
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
5.45
0.87
1.4
4.5
13
MAX
Q
Q
Q
T
o
tal gate charge
g
Gate-to-source charge
Gate-to-drain charge
Turn-on delay time
Turn-off delay time
Rise time
V
V
=
–
1
0 V,
V
GS
=
–
1
0 V,
I
I
=
–
1 A
nC
gs
DS
D
gd
t
t
t
t
t
ns
ns
d(on)
d(off)
r
=
–
1
0 V,
= 6
Ω
,
R
= 10
Ω
,
=
–
1
A
,
DD
G
L
D
R
See Figures 1 and 2
10
Fall time
2
ns
f
Source-to-drain reverse recovery time
I
F
= 5.3 A,
di/dt = 100
A
/
µ
s
16
rr(SD)
4
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T
P
S1100, TPS1100Y
S
I
NGLE
P
-CHANNEL ENHANCE
M
E
NT-
M
O
DE
M
O
SFETS
SLVS078C – DECEMBER 1993 – REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
V
GS
0 V
90%
R
L
V
DS
–
+
V
GS
V
DD
R
G
10%
DUT
V
DS
–
1
0 V
t
t
d(off)
d(on)
t
r
t
f
Figure 1. Switching-Time Test Circuit
Figure 2. Switching-Time Waveforms
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Drain current
Drain current
vs Drain-to-source voltage
3
4
vs Gate-to-source voltage
vs Drain current
Static drain-to-source on-state resistance
Capacitance
5
vs Drain-to-source voltage
6
Static drain-to-source on-state resistance (normalized)
vs Junction temperature
7
Source-to-drain diode current
Static drain-to-source on-state resistance
Gate-to-source threshold voltage
Gate-to-source voltage
vs Source-to-drain voltage
vs Gate-to-source voltage
vs Junction temperature
vs Gate charge
8
9
10
11
5
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T
P
S1100, TPS1100Y
S
I
NGLE
P
-CHANNEL ENHANCE
M
E
NT-
M
O
DE
M
O
SFETS
SLVS078C – DECEMBER 1993 – REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
DRAIN CURRENT
vs
DRAIN CURRENT
vs
GATE-TO-SOURCE VOLTAGE
DRAIN-TO-SOURCE VOLTAGE
– 7
– 7
V
=
–
8 V
GS
=
–
7 V
V
DS
= –10 V
V
GS
– 6
– 5
– 6
– 5
V
=
–
6 V
V
GS
=
–
4 V
GS
T
J
= 25
°
C
T
J
= 150
°
C
T
J
=
–
4
0
°
C
V
GS
=
–
5 V
– 4
– 3
– 4
– 3
V
GS
=
–
3 V
– 2
– 1
– 2
– 1
0
V
=
–
2 V
GS
T
J
= 25
°
C
0
0
– 1
– 2
– 3
– 4
– 5
– 6
– 7
– 8
– 9
– 10
0
– 1
– 2
– 3
– 4
– 5
– 6
– 7
V
DS
– Drain-to-Source Voltage – V
V
GS
– Gate-to-Source Voltage – V
Figure 3
Figure 4
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
CAPACITANCE
vs
vs
DRAIN CURRENT
DRAIN-TO-SOURCE VOLTAGE
350
300
250
0.7
V
= 0
GS
f = 1 MHz
T
= 25
°
C
J
T
J
= 25
°
C
0.6
0.5
0.4
0.3
0.2
0.1
0
†
C
iss
V
GS
=
–
2
.7
V
V
=
–
3 V
200
150
GS
C
oss
V
GS
=
–
4
.5
V
V
= –10 V
GS
‡
100
C
rss
50
0
– 0.1
– 1
– 10
0 –
1 –
2 –
3 –
4 –
5 –
6 – 7
– 8
– 9
–10 –11 –12
I
D
– Drain Current – A
V
DS
– Drain-to-Source Voltage – V
†
‡
C
C
C
, C
gs
iss
gd
ds(shorted)
C
C
gs
gd
C
C
, C
C
≈
C
C
rss
oss
gd
ds
ds
gd
C
C
gs
gd
Figure 5
Figure 6
6
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T
P
S1100, TPS1100Y
S
I
NGLE
P
-CHANNEL ENHANCE
M
E
NT-
M
O
DE
M
O
SFETS
SLVS078C – DECEMBER 1993 – REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
STATIC DRAIN-TO-SOURCE
ON-STATE RESISTANCE (NORMALIZED)
SOURCE-TO-DRAIN DIODE CURRENT
vs
vs
SOURCE-TO-DRAIN VOLTAGE
JUNCTION TEMPERATURE
–10
1.5
1.4
1.3
1.2
1.1
V
=
–
1
0 V
Pulse Test
GS
=
–
1
A
I
D
T
J
= 150
°
C
–1
T
J
= 25
°
C
1
0.9
0.8
T
J
=
–
4
0
°
C
0.7
0.6
– 0.1
0
– 0.2 – 0.4
– 0.6
– 0.8
– 1
–1.2 –1.4 –1.6 –1.8
–
5
0
0
50
100
150
V
SD
– Source-to-Drain Voltage – V
T
J
– Junction Temperature –
°
C
Figure 7
Figure 8
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
GATE-TO-SOURCE THRESHOLD VOLTAGE
vs
GATE-TO-SOURCE VOLTAGE
0.7
vs
JUNCTION TEMPERATURE
– 1.5
– 1.4
– 1.3
– 1.2
– 1.1
I
T
=
–
1 A
= 25
°
C
D
J
I
D
=
–
2
50
µ
A
0.6
0.5
0.4
0.3
0.2
– 1
0.1
0
– 0.9
– 1
– 3
– 5
– 7
– 9
– 11
– 13
– 15
–
5
0
0
50
100
150
V
GS
– Gate-to-Source Voltage – V
T
J
– Junction Temperature –
°
C
Figure 9
Figure 10
7
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T
P
S1100, TPS1100Y
S
I
NGLE
P
-CHANNEL ENHANCE
M
E
NT-
M
O
DE
M
O
SFETS
SLVS078C – DECEMBER 1993 – REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
GATE-TO-SOURCE VOLTAGE
vs
GATE CHARGE
– 10
V
=
–
1
0 V
DS
=
–
1 A
I
T
D
= 25
°
C
J
– 8
– 6
– 4
– 2
0
0
1
2
3
4
5
6
Q
– Gate Charge – nC
g
Figure 11
8
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T
P
S1100, TPS1100Y
S
I
NGLE
P
-CHANNEL ENHANCE
M
E
NT-
M
O
DE
M
O
SFETS
SLVS078C – DECEMBER 1993 – REVISED AUGUST 1995
THERMAL INFORMATION
TRANSIENT JUNCTION-TO-AMBIENT
THERMAL IMPEDANCE
vs
DRAIN CURRENT
vs
PULSE DURATION
DRAIN-TO-SOURCE VOLTAGE
– 10
100
10
Single Pulse
See Note A
0.001 s
0.01 s
0.1 s
Single Pulse
See Note A
– 1
1 s
1
– 0.1
10 s
DC
T
T
A
= 150
°
C
= 25
°
C
J
0.1
– 0.001
0.001
0.01
0.1
1
10
– 0.1
– 1
– 10
– 100
t
w
– Pulse Duration – s
V
DS
– Drain-to-Source Voltage – V
Figure 12
Figure 13
NOTE A:
Values are for the D package and are FR4-board mounted only.
APPLICATION INFORMATION
3 V or 5 V
5 V
Microcontroller
Driver
–4 V
Charge
Pump
GaAs FET
Amplifier
Microcontroller
Load
Figure 15. Cellular Phone Output Drive
Figure 14. Notebook Load Management
9
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PACKAGE OPTION ADDENDUM
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
TPS1100D
Status Package
Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SOIC
SOIC
D
8
8
8
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
1100
1100
1100
TPS1100DG4
TPS1100DR
TPS1100PW
ACTIVE
ACTIVE
ACTIVE
D
D
75
Green (RoHS
& no Sb/Br)
SOIC
2500
150
Green (RoHS
& no Sb/Br)
TSSOP
PW
Green (RoHS
& no Sb/Br)
PS1100
PS1100
TPS1100PWLE
TPS1100PWR
OBSOLETE
ACTIVE
TSSOP
TSSOP
PW
PW
8
8
TBD
Call TI
Call TI
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE:
Product device recommended for new designs.
LIFEBUY:
TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND:
Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW:
Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE:
TI has discontinued the production of the device.
(2)
Eco Plan – The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) – please check
http://www.ti.com/productcontent
for the latest availability
information and additional product content details.
TBD:
The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS):
TI’s terms “Lead-Free” or “Pb-Free” mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt):
This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based
die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br):
TI defines “Green” to mean Pb-Free (RoHS compatible), and free of Bromine (Br)
and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. – The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a “~” will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
10-Jun-2014
(6)
Lead/Ball Finish – Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
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The information provided on this page represents TI’s knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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In no event shall TI’s liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
11-Jun-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width
(mm) (mm) (mm) (mm) (mm)
Quadrant
(mm) W1
(mm)
TPS1100DR
SOIC
D
8
8
2500
2000
330.0
330.0
12.4
12.4
6.4
7.0
5.2
3.6
2.1
1.6
8.0
8.0
12.0
12.0
Q1
Q1
TPS1100PWR
TSSOP
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
11-Jun-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS1100DR
SOIC
D
8
8
2500
2000
340.5
367.0
338.1
367.0
20.6
35.0
TPS1100PWR
TSSOP
PW
Pack Materials-Page 2
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