onsemi-NVD5C486NLT4G
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NVD5C486NL
N-Channel
40
V
,
1
6 m
W
, 24 A
Features
•
Low R
to Minimize Conduction Losses
DS(on)
•
Low Q
and Capacitance to Minimize Driver Losses
G
•
AEC
−
Q101 Qualified and P
P
A
P Capable
•
These Devices are Pb
−
Free, Halogen Free/BFR Free and are RoHS
Compliant
V
R
I
D
(BR)DSS
DS(on)
16 m
ꢂ
@ 10 V
40 V
24 A
24.5 m
ꢂ
@ 4.5 V
MAXIMUM RATINGS
(T =
25
°
C unless otherwise noted)
J
D
Parameter
Drain
−
to
−
Source Voltage
Symbol
Value
40
Unit
V
V
DSS
Gate
−
to
−
Source Voltage
V
“
20
24
V
GS
Continuous Drain Cur-
T
= 25
°
C
= 100
°
C
= 25
°
C
I
A
C
D
G
rent R
ꢀ
JC
T
C
17
Steady
State
Power Dissipation R
T
C
P
18
W
A
ꢀ
D
S
JC
JA
N
−
CHANNEL MOSFET
T
C
= 100
°
C
9.0
9.8
7.0
2.9
1.4
110
Continuous Drain
Current R
T =
25
°
C
A
I
D
4
ꢀ
JA
T =
100
°
C
A
Steady
State
2
1
Power Dissipation R
T =
25
°
C
A
P
W
ꢀ
D
3
T =
100
°
C
A
DPAK
Pulsed Drain Current
T =
25
°
C, t
= 10
ꢁ
s
I
DM
A
A
p
CASE 369C
STYLE 2
Operating Junction and Storage
T
e
mperature
T , T
−
55 to
175
°
C
J
stg
MARKING DIAGRAM
& PIN ASSIGNMENT
Source Current (Body Diode)
I
15
63
A
S
Single Pulse Drain
−
to
−
Source Avalanche
E
AS
mJ
Energy (T
= 25
°
C, I
= 1.7 A)
4
J
L(pk)
Drain
Lead
T
e
mperature for Soldering Purposes
(1/8
″
from case for 10 s)
T
260
°
C
L
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
2
Drain
1
3
THERMAL RESISTANCE MAXIMUM RATINGS
Gate Source
Parameter
Symbol
Value
8.2
Unit
A
Y
WW
= Assembly Location
=
Y
e
ar
= Work Week
R
°
C/W
ꢀ
JC
R
52
ꢀ
JA
5C486NL = Device Code
G
1. The
entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surface
−
mounted on FR4 board using a 650 mm
, 2 oz. Cu pad.
= Pb
−
Free Package
2
3. Maximum
current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
©
Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
June, 2019
−
Rev. 0
NVD5C486NL/D
NVD5C486NL
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise noted)
J
Parameter
OFF CHARACTERISTICS
Symbol
Test Condition
Min
Typ
Max
Unit
Drain
−
to
−
Source Breakdown Voltage
V
V
GS
= 0
V
, I
=
2
50
ꢁ
A
40
V
(BR)DSS
D
Drain
−
to
−
Source Breakdown Voltage
T
e
mperature Coefficient
V
/T
J
17
mV/
°
C
(BR)DSS
Zero Gate Voltage Drain Current
I
T =
25
°
C
10
ꢁ
A
DSS
J
V
= 0
V
,
GS
DS
V
= 40 V
T =
125
°
C
J
250
100
Gate
−
to
−
Source Leakage Current
Gate Threshold Voltage
I
V
= 0
V
, V
=
2
0 V
nA
GSS
DS
GS
GS
V
V
= V
, I
= 20
ꢁ
A
1.2
2.2
V
GS(TH)
DS
D
Negative Threshold
T
e
mperature Coefficient
Drain
−
to
−
Source On Resistance
Drain
−
to
−
Source On Resistance
Forward Transconductance
V
/T
4.6
mV/
°
C
GS(TH)
J
R
R
V
= 4.5
V
, I
=
1
0 A
19.6
13.3
25.5
24.5
16
m
ꢂ
ꢂ
DS(on)
DS(on)
GS
D
V
= 10
V
, I
=
1
0 A
D
m
GS
g
FS
V
= 3
V
, I
=
1
0 A
S
DS
D
CHARGES, CAPACITANCES AND GATE RESISTANCES
Input Capacitance
C
530
210
13
pF
iss
V
= 0
V
, f =
1
.0 MHz,
DS
GS
Output Capacitance
Reverse Transfer Capacitance
T
o
tal Gate Charge
C
oss
V
= 25 V
C
rss
Q
Q
V
GS
= 4.5
V
, V
=
3
2
V
,
4.7
nC
nC
G(TOT)
DS
= 10 A
I
D
T
o
tal Gate Charge
9.8
1.2
2.0
1.5
3.2
G(TOT)
Threshold Gate Charge
Gate
−
to
−
Source Charge
Gate
−
to
−
Drain Charge
Plateau Voltage
Q
G(TH)
V
GS
= 10
V
, V
=
3
2
V
,
DS
Q
GS
GD
GP
I
D
= 10 A
Q
V
V
Turn
−
On Delay Time
t
6.0
14
ns
d(on)
Rise Time
t
r
V
= 10
V
, V
=
3
2
V
,
GS
D
DS
I
= 10 A, R
= 2.5
ꢂ
G
Turn
−
Off Delay Time
t
15
d(off)
Fall Time
t
f
2.0
DRAIN
−
SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
T =
25
°
C
0.88
0.77
19
1.2
V
SD
J
V
S
= 0
V
,
GS
I
= 10 A
T =
125
°
C
J
Reverse Recovery Time
Charge Time
t
ns
RR
ta
8.0
10
V
GS
= 0
V
,
d
Is/dt = 100 A/
ꢁ
s,
I
S
= 10 A
Discharge Time
tb
Reverse Recovery Charge
Q
10
nC
RR
4. Pulse
T
e
st: Pulse Width
≤
300
ꢁ
s, Duty Cycle
≤
2%.
5. Switching
characteristics are independent of operating junction temperatures.
2
NVD5C486NL
TYPICAL CHARACTERISTICS
35
30
25
20
15
10
35
4.0 V
V
= 3 V
DS
30
25
20
15
10
V
GS
= 10 V to 4.5 V
3.6 V
3.2 V
2.8 V
T =
25
°
C
J
5
0
5
0
T =
125
°
C
J
T =
−
55
°
C
J
0
1
2
3
1
2
3
4
5
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
V
GS
, GATE
−
TO
−
SOURCE VOLTAGE (V)
Figure 1. On
−
Region Characteristics
Figure 2. Transfer Characteristics
30
25
20
15
30
25
20
15
I
= 10 A
D
T =
25
°
C
J
T =
25
°
C
J
V
= 4.5 V
= 10 V
GS
V
GS
10
5
10
5
3
4
5
6
7
8
9
10
5
6
7
8
9
10
V
GS
, GATE
−
TO
−
SOURCE VOLTAGE (V)
I ,
DRAIN CURRENT (A)
D
Figure 3. On
−
Resistance vs. Gate
−
to
−
Source
Figure 4. On
−
Resistance vs. Drain Current and
Voltage
Gate Voltage
2.0
1.5
1.0
100K
T =
175
°
C
J
I
= 10 A
= 10 V
D
10K
1K
100
10
V
GS
T =
150
°
C
J
T =
125
°
C
J
T =
85
°
C
J
1
T =
25
°
C
J
0.1
0.5
0
0.01
0.001
−
50
−
25
0
25
50
75 100 125 150
175
5
10
15
20
25
30
35
40
T , JUNCTION TEMPERATURE (
°
C)
J
V
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
DS
Figure 5. On
−
Resistance Variation with
Figure 6. Drain
−
to
−
Source Leakage Current
Temperature
vs. Voltage
3
NVD5C486NL
TYPICAL CHARACTERISTICS
1K
10
C
iss
9
8
7
6
5
4
3
C
oss
100
Q
Q
gs
gd
C
rss
10
1
T =
25
°
C
GS
f = 1 MHz
V
DS
= 32 V
J
V
2
1
0
= 0 V
I
D
= 10 A
T =
25
°
C
J
0
5
10
15
20
25
30
35
40
0
1
2
3
4
5
6
7
8
9
10
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
Q ,
TOTAL GATE CHARGE (nC)
g
Figure 7. Capacitance Variation
Figure 8. Gate
−
to
−
Source Voltage vs. Total
Charge
10
100
10
t
t
V
GS
= 0 V
d(off)
t
f
r
t
d(on)
1
1
V
V
= 10 V
= 32 V
GS
DS
I
D
= 15 A
T =
−
55
°
C
T =
125
°
C
T =
25
°
C
J
J
J
0.1
0.1
1
10
R ,
GATE RESISTANCE (
ꢂ
)
100
0.3 0.4
0.5
0.6
0.7
0.8
0.9
1.0 1.1
V
SD
, SOURCE
−
TO
−
DRAIN VOLTAGE (V)
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
100
100
10
T
= 25
°
C
J(initial)
10
ꢁ
s
10
T
C
= 25
°
C
V
≤
10 V
GS
T
= 100
°
C
J(initial)
1
Single Pulse
1
0.5 ms
1 ms
R
Limit
DS(on)
Thermal Limit
Package Limit
10 ms
0.1
0.1
0.1
1
10
100
1000
0.00001
0.0001
0.001
0.01
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
TIME IN AVALANCHE (s)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Drain Current vs. Time in
Avalanche
4
NVD5C486NL
TYPICAL CHARACTERISTICS
100
50% Duty Cycle
20%
10%
5%
10
1
2%
1%
0.1
Single Pulse
0.01
0.001
0.000001 0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Response
ORDERING INFORMATION
Order Number
†
Package
Shipping
NVD5C486NLT4G
DPAK
(Pb
−
Free)
2500 /
T
a
pe & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our
T
a
pe and Reel Packaging
Specifications Brochure, BRD8011/D.
5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK (SINGLE GAUGE)
CASE 369C
4
ISSUE F
2
1
DATE 21 JUL 2015
3
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
MENSIONS b3, L3 and Z.
A
D
E
C
A
b3
B
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BOD
Y
.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
c2
4
2
L3
Z
DETAIL A
H
1
3
7. OPTIONAL MOLD FEATURE.
INCHES
DIM MIN
MAX
0.086 0.094
A1
0.000 0.005
0.025 0.035
b2
0.028 0.045
b3
0.180 0.215
MILLIMETERS
L4
b2
e
NOTE 7
MIN
2.18
0.00
0.63
0.72
4.57
0.46
0.46
5.97
6.35
MAX
2.38
0.13
0.89
1.14
5.46
0.61
0.61
6.22
6.73
c
BOTTOM VIEW
A
SIDE VIEW
b
b
M
0.005 (0.13)
C
TOP VIEW
c
0.018 0.024
c2
0.018 0.024
Z
Z
D
E
e
0.235 0.245
0.250 0.265
0.090 BSC
H
2.29 BSC
9.40 10.41
1.40 1.78
2.90 REF
0.51 BSC
0.89 1.27
GAUGE
SEATING
PLANE
H
L
L1
L2
0.370 0.410
0.055 0.070
0.114 REF
L2
PLANE
C
0.020 BSC
L3
0.035 0.050
L
BOTTOM VIEW
A1
L4
Z
−−−
0.040
0.155
−−−
−−−
3.93
1.01
−−−
L1
ALTERNATE
CONSTRUCTIONS
DETAIL A
ROTATED 9
0
5
CW
GENERIC
MARKING DIAGRAM*
STYLE 1:
PIN 1.
BASE
STYLE 2:
PIN 1.
GATE
2. DRAIN
STYLE 3:
PIN 1.
ANODE
STYLE 4:
STYLE 5:
PIN 1.
GATE
PIN 1.
CATHODE
2. ANODE
2. COLLECTOR
2. CATHODE
3. ANODE
4. CATHODE
2. ANODE
3. CATHODE
4. ANODE
3. EMITTER
3. SOURCE
4. DRAIN
3. GATE
XXXXXXG
ALYWW
AYWW
XXX
4. COLLECTOR
4. ANODE
STYLE 6:
PIN 1.
MT1
2. MT2
STYLE 7:
STYLE 8:
PIN 1.
N/C
STYLE 9:
PIN 1.
ANODE
2. CATHODE
STYLE 10:
PIN 1.
CATHODE
2. ANODE
XXXXXG
PIN 1.
GATE
2. COLLECTOR
2. CATHODE
3. GATE
4. MT2
3. EMITTER
3. ANODE
4. CATHODE
3. RESISTOR
ADJUST
4. CATHODE
3. CATHODE
4. ANODE
4. COLLECTOR
IC
Discrete
SOLDERING FOOTPRINT*
XXXXXX =
Device Code
A
L
Y
WW
G
= Assembly Location
= Wafer Lot
=
Y
e
ar
= Work Week
= Pb
−
Free Package
6.20
0.244
3.00
0.118
2.58
0.102
5.80
0.228
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb
−
Free indicator, “G” or microdot “
G
”, may
or may not be present. Some products may
not follow the Generic Marking.
1.60
0.063
6.17
0.243
mm
inches
ǒ
Ǔ
SCALE 3:1
*For additional information on our Pb
−
Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting
T
e
chniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON10527D
DPAK (SINGLE GAUGE)
PAGE 1 OF 1
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T
:
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−
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o
ll Free USA/Canada
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