onsemi-NVMFD5877NLWFT3G
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NVMFD5877NL
N-Channel, Logic Level,
Dual SO8FL
60
V
,
3
9 m
W
, 17 A
Features
•
Low R
to Minimize Conduction Losses
•
Low Capacitance to Minimize Driver Losses
DS(on)
V
R
MAX
I MAX
D
(BR)DSS
DS(on)
39 m
W
@ 10 V
60 m
W
@ 4.5 V
•
NVMFD5877NLWF
−
Wettable Flanks Option for Enhanced Optical
60 V
17 A
Inspection
•
AEC
−
Q101 Qualified and P
P
A
P Capable
•
These Devices are Pb
−
Free, Halogen Free and are RoHS Compliant
Dual N
−
Channel
D1
D2
MAXIMUM RATINGS
(T =
25
°
C unless otherwise noted)
J
Parameter
Drain
−
to
−
Source Voltage
Symbol
Value
60
Unit
V
V
DSS
G1
G2
Gate
−
to
−
Source Voltage
V
“
20
17
V
GS
Continuous Drain Cur-
T
= 25
°
C
= 100
°
C
= 25
°
C
I
A
mb
D
rent R
Y
J
−
mb
S1
S2
T
mb
12
Steady
State
Power Dissipation
T
mb
P
23
W
A
D
MARKING DIAGRAM
R
Y
J
−
mb
T
mb
= 100
°
C
12
D1 D1
S1
G1
S2
G2
D1
D1
D2
D2
Continuous Drain Cur-
T =
25
°
C
I
6
A
D
1
5877xx
AYWZZ
rent R
q
JA
DFN8 5×6
(SO8FL)
T =
100
°
C
A
5
Steady
State
Power Dissipation
T =
25
°
C
P
3.2
1.6
74
W
A
D
CASE 506BT
D2 D2
R
q
JA
T =
100
°
C
A
5877NL =
Specific Device Code
for NVMFD5877NL
Pulsed Drain Current
T =
25
°
C, t
= 10
m
s
I
DM
A
A
p
5877LW = Specific Device Code
for NVMFD5877NLWF
Operating Junction and Storage
T
e
mperature
T , T
−
55 to
°
C
J
stg
+175
A
= Assembly Location
=
Y
e
ar
Source Current (Body Diode)
I
S
19
A
Y
W
ZZ
= Work Week
= Lot Traceability
Single Pulse Drain
−
to
−
Source Avalanche
(I
= 14.5 A, L =
E
10.5
mJ
L(pk)
AS
0.1 mH)
Energy (T
= 25
°
C,
J
(I =
6.3 A, L =
40
V
= 24
V
, V
G
=
L(pk)
DD
GS
2 mH)
10
V
, R
=
2
5
W
)
ORDERING INFORMATION
Lead
T
e
mperature for Soldering Purposes
(1/8
″
from case for 10 s)
T
260
°
C
L
†
Device
Package
Shipping
NVMFD5877N
L
T
1G
NVMFD5877N
L
W
FT1G
NVMFD5877N
L
T
3G
NVMFD5877N
L
W
FT3G
DFN8
(Pb
−
Free)
1500 /
T
a
pe &
Reel
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
DFN8
(Pb
−
Free)
1500 /
T
a
pe &
Reel
Parameter
Symbol
Value
Unit
DFN8
(Pb
−
Free)
5000 /
T
a
pe &
Reel
Junction
−
to
−
Mounting Board (top)
−
Steady
R
6.5
°
C/W
Y
J
−
mb
DFN8
(Pb
−
Free)
5000 /
T
a
pe &
Reel
R
47
q
JA
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our
T
a
pe and Reel Packaging Specification
Brochure, BRD8011/D.
1. The
entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
©
Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
July, 2019
−
Rev. 9
NVMFD5877NL/D
NVMFD5877NL
2. Psi
(
Y
) is used as required per JESD51
−
12 for packages in which
substantially less than 100% of the heat flows to single case surface.
2
3. Surface
−
mounted on FR4 board using a 650 mm
, 2 oz. Cu pad.
4. Maximum
current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
2
NVMFD5877NL
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise specified)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain
−
to
−
Source Breakdown Voltage
V
V
GS
= 0
V
, I
=
2
50
m
A
60
V
(BR)DSS
D
Drain
−
to
−
Source Breakdown Voltage
T
e
mperature Coefficient
V
/T
J
53
mV/
°
C
(BR)DSS
T =
25
°
C
1.0
10
Zero Gate Voltage Drain Current
I
m
A
J
DSS
V
= 0
V
,
GS
DS
V
= 60 V
= 0
V
, V
=
GS
T =
125
°
C
J
Gate
−
to
−
Source Leakage Current
Gate Threshold Voltage
I
V
20 V
100
nA
GSS
DS
V
V
= V
, I
= 250
m
A
1.0
3.0
V
GS(TH)
GS
DS
D
Negative Threshold
T
e
mperature
Coefficient
V
/T
3.5
mV/
°
C
GS(TH)
J
V
= 10 V
= 4.5 V
I
I
= 7.5 A
= 7.5 A
31
42
39
60
Drain
−
to
−
Source On Resistance
R
m
W
GS
D
DS(on)
V
GS
D
Forward Transconductance
g
FS
V
DS
= 15
V
, I
=
5
.0 A
7.0
S
D
CHARGES AND CAPACITANCES
Input Capacitance
C
C
540
55
pF
nC
iss
Output Capacitance
V
GS
= 0
V
, f =
1
.0 MHz, V
= 25 V
DS
oss
Reverse Transfer Capacitance
T
o
tal Gate Charge
C
36
rss
Q
5.9
G(TOT)
Threshold Gate Charge
Gate
−
to
−
Source Charge
Gate
−
to
−
Drain Charge
T
o
tal Gate Charge
Q
0.62
1.64
2.80
11
G(TH)
V
= 4.5
V
, V
=
4
8
V
,
DS
GS
I
= 5.0 A
D
Q
GS
Q
GD
Q
V
= 10
V
, V
=
4
8
V
, I
=
5
.0A
20
nC
ns
G(TOT)
GS
DS
D
Turn
−
On Delay Time
Rise Time
t
8.1
15.8
11.8
3.9
d(on)
t
r
V
GS
= 4.5
V
, V
=
4
8
V
,
DS
I
D
= 5.0 A, R
= 2.5
W
G
Turn
−
Off Delay Time
Fall Time
t
t
t
d(off)
t
f
Turn
−
On Delay Time
Rise Time
4.9
ns
d(on)
t
r
6.4
V
= 10
V
, V
=
4
8
V
,
DS
GS
I
D
= 5.0 A, R
= 2.5
W
G
Turn
−
Off Delay Time
Fall Time
14.5
2.4
d(off)
t
f
DRAIN
−
SOURCE DIODE CHARACTERISTICS
T =
25
°
C
0.8
0.7
1.2
Forward Diode Voltage
V
SD
V
J
V
S
= 0
V
,
GS
I
= 5.0 A
T =
125
°
C
J
Reverse Recovery Time
Charge Time
t
14.5
11.5
3.1
ns
RR
t
t
a
V
GS
= 0
V
, d
/
d =
100 A/
m
s,
IS t
I
= 5.0 A
S
Discharge Time
b
Reverse Recovery Charge
Q
11
nC
nH
RR
PACKAGE PARASITIC VALUES
Source Inductance
Drain Inductance
L
0.93
0.005
1.84
1.5
S
D
G
L
T =
25
°
C
A
Gate Inductance
L
Gate Resistance
R
W
G
5. Pulse
T
e
st: pulse width = 300
m
s, duty cycle
v
2%.
6. Switching
characteristics are independent of operating junction temperatures.
3
NVMFD5877NL
TYPICAL CHARACTERISTICS
30
40
36
32
28
24
20
16
12
8
5 V
T =
25
°
C
V
GS
= 10 V
J
V
DS
≥
10 V
4.5 V
20
10
0
4.0 V
T =
25
°
C
J
3.5 V
3.0 V
4
T =
125
°
C
J
T =
−
55
°
C
J
0
0
1
2
3
4
5
1
2
3
4
5
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
V
GS
, GATE
−
TO
−
SOURCE VOLTAGE (V)
Figure 1. On
−
Region Characteristics
Figure 2. Transfer Characteristics
0.065
0.060
0.055
0.050
0.045
0.040
0.035
0.030
0.025
0.065
0.060
0.055
0.050
0.045
0.040
0.035
0.030
0.025
T =
25
°
C
I
= 10 A
J
D
T =
25
°
C
J
V
V
= 4.5 V
GS
= 10 V
15
GS
3
4
5
6
7
8
9
10
5
8
10
13
18
20
23
25
V
GS
, GATE
−
TO
−
SOURCE VOLTAGE (V)
I ,
DRAIN CURRENT (A)
D
Figure 3. On
−
Resistance vs. Gate
−
to
−
Source
Figure 4. On
−
Resistance vs. Drain Current and
Voltage
Gate Voltage
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
1E
−
04
1E
−
05
1E
−
06
1E
−
07
1E
−
08
1E
−
09
1E
−
10
1E
−
11
1E
−
12
V
GS
= 0 V
I
V
= 7.5 A
D
= 10 V
GS
T =
150
°
C
J
T =
125
°
C
J
T =
25
°
C
J
5
10 15 20 25 30 35 40 45 50 55 60
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
−
50
−
25
0
25
50
75
100 125 150 175
T , JUNCTION TEMPERATURE (
°
C)
J
V
DS
Figure 5. On
−
Resistance Variation with
Figure 6. Drain
−
to
−
Source Leakage Current
Temperature
vs. Voltage
4
NVMFD5877NL
TYPICAL CHARACTERISTICS
10
800
700
600
500
400
300
200
100
0
Q
T
V
= 0 V
GS
9
8
7
6
5
4
3
2
1
0
T =
25
°
C
J
C
iss
Q
Q
gs
gd
T =
25
°
C
J
V
I
= 48 V
= 5 A
C
DD
oss
D
C
rss
0
5
10
15
20
25
30
0
1
2
3
4
5
6
7
8
9
10 11
DRAIN
−
TO
−
SOURCE VOLTAGE (V)
Q ,
TOTAL GATE CHARGE (nC)
g
Figure 7. Capacitance Variation
Figure 8. Gate
−
to
−
Source vs. Gate Charge
1000
100
10
40
30
20
V
= 48 V
= 5 A
= 10 V
DD
V
= 0 V
GS
I
D
T =
25
°
C
J
V
GS
t
t
d(off)
t
f
t
r
d(on)
10
0
1
1
10
R ,
GATE RESISTANCE (
W
)
100
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
V
SD
, SOURCE
−
TO
−
DRAIN VOLTAGE (V)
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage
100
10
m
s
100
m
s
10
1 ms
V
= 20 V
GS
10 ms
Single Pulse
= 25
°
C
1
T
C
R
Limit
dc
DS(on)
Thermal Limit
Package Limit
0.1
0.1
1
10
100
V
DS
, DRAIN VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
5
NVMFD5877NL
TYPICAL CHARACTERISTICS
100
10
Duty Cycle = 0.5
0.2
0.1
0.05
0.02
1
0.01
2
Device Mounted on 650 mm
2 oz Cu PCB
0.1
0.01
Single Pulse
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 12. Thermal Response
6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN8 5×6, 1.27P Dual Flag (SO8FL
−
Dual)
CASE 506BT
ISSUE F
1
DATE 23 NOV 2021
2X
SCALE 2:1
NOTES:
0.20
C
1. DIMENSIONING
AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING
DIMENSION: MILLIMETERS.
3. DIMENSION
b APPLIES TO PLATED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TI
P
.
4. PROFILE
TOLERANCE APPLIES TO THE EXPOSED PAD AS WELL
AS THE TERMINALS.
5. DIMENSIONS
D1 AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
D
A
B
E
2X
D1
0.20
C
8
7
6
5
6. SEATING
PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED
AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BOD
Y
.
7. A
VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA.
PIN ONE
E1
MILLIMETERS
IDENTIFIER
DIM
A
A1
b
b1
c
MIN
0.90
−−−
0.33
0.33
0.20
NOM
−−−
−−−
0.42
0.42
−−−
5.15 BSC
4.90
4.10
1.70
6.15 BSC
5.90
4.15
1.27 BSC
0.55
−−−
−−−
−−−
0.61
MAX
1.10
0.05
0.51
0.51
0.33
NOTE 7
4X
h
1
2
3
4
c
TOP VIEW
D
A1
D1
D2
D3
E
E1
E2
e
G
h
K
K1
4.70
3.90
1.50
5.10
4.30
1.90
0.10
0.10
C
C
A
DETAIL B
5.70
3.90
6.10
4.40
ALTERNATE
SEATING
PLANE
NOTE 6
DETAIL A
CONSTRUCTION
C
NOTE 4
SIDE VIEW
DETAIL A
0.45
−−−
0.51
0.56
0.48
3.25
1.80
0.65
12
−−−
−−−
_
D2
D3
L
M
N
0.71
3.75
2.20
4X
L
K
3.50
2.00
e
1
4
SOLDERING FOOTPRINT*
DETAIL B
4.56
4X
2X
2.08
2X
0.56
b1
8X
0.75
N
E2
M
8
5
4X
G
b
8X
4X
1.40
0.10
0.05
C
C
A B
K1
6.59
4.84
NOTE 3
2.30
BOTTOM VIEW
3.70
GENERIC
MARKING DIAGRAM*
0.70
1
XXXXXX
AYWZZ
4X
1.27
PITCH
1.00
5.55
XXXXXX = Specific Device Code
DIMENSION: MILLIMETERS
A
Y
W
ZZ
= Assembly Location
=
Y
e
ar
= Work Week
= Lot Traceability
*For additional information on our Pb
−
Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting
T
e
chniques Reference Manual, SOLDERRM/D.
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb
−
Free indicator, “G” or microdot “
G
”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON50417E
DFN8 5X6, 1.27P DUAL FLAG (SO8FL
−
DUAL)
PAGE 1 OF 1
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Semiconductor Components Industries, LLC, 2019
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