onsemi-HUF75652G3
| Part # | onsemi-HUF75652G3 |
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Ultrafet
100
V
,
7
5 A, 8 m
W
HUF75652G3
Features
•
Ultra Low On
−
Resistance
♦
r
= 0.008
W
,
V
=
10 V
GS
DS(ON)
•
Simulation Models
D
♦
Temperature Compensated PSPICE
™
and SABER
™
Electrical
Models
♦
Spice and SABER Thermal Impedance Models
G
•
Peak Current vs Pulse Width Curve
•
UIS Rating Curve
S
•
This Device is Pb
−
Free, Halogen Free/BFR Free and is RoHS
Compliant
Packing
TO
−
247
−
3LD
CASE 340CK
MARKING DIAGRAMS
Figure 1.
$Y&Z&3&K
75652G
$Y
&Z
&3
&K
= ON Semiconductor Logo
= Assembly Plant Code
= Data Code (
Y
e
ar & Week)
= Lot
75652G
= Specific Device Code
ORDERING INFORMATION
Part Number
HUF75652G3
Package
Brand
TO
−
247
−
3LD
75652G
©
Semiconductor Components Industries, LLC, 2001
1
Publication Order Number:
March, 2020
−
Rev. 3
HUF75652G3/D
HUF75652G3
ABSOLUTE MAXIMUM RATINGS
T =
25
°
C unless otherwise specified
C
Description
Symbol
Ratings
100
Units
V
V
V
V
DSS
DGR
V
100
GS
Gate to Source Voltage
Drain Current
V
GS
+20
I
75
75
A
A
C
C
GS
D
D
I
GS
−
Pulsed Drain Current
I
DM
Pulsed Avalanche Rating
UIS
Power Dissipation
−
Derate Above 25
°
C
P
D
515
3.44
W
W/
°
C
Operating and Storage
T
e
mperature
T , T
−
55 to 175
°
C
J
STG
Maximum
T
e
mperature for Soldering
−
Leads at 0.063 in (1.6 mm) from Case for 10 s
−
Package Body for 10 s, See
T
e
chbrief TB334
T
pkg
300
260
°
C
°
C
L
T
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. T
J
= 25
°
C to 150
°
C.
2
HUF75652G3
ELECTRICAL SPECIFICATIONS
T =
25
°
C unless otherwise noted
C
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
OFF STATE SPECIFICATIONS
BV Drain
to Source Breakdown Voltage
I
100
−
−
−
−
−
−
V
D
GS
DSS
Zero Gate Voltage Drain Current
V
V
V
= 95
V
, V
= 0 V
1
m
A
m
A
nA
I
DSS
DS
DS
GS
GS
= 90
V
, V
= 0 V, T
= 150
°
C
−
250
100
GS
C
=
20 V
I
Gate to Source Leakage Current
−
GSS
ON STATE SPECIFICATIONS
V
DS D
V
Gate to Source Threshold Voltage
Drain to Source On Resistance
2
−
4
V
GS
GS(TH)
DS(ON)
W
r
I
D
−
0.0067 0.008
GS
THERMAL SPECIFICATIONS
°
C/W
°
C/W
R
R
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
TO
−
247
−
−
−
−
0.29
30
θ
JC
JA
θ
SWITCHING SPECIFICATIONS
(V =
10 V)
GS
t
Turn
−
On Time
Turn
−
On Delay Time
Rise Time
−
−
−
−
−
−
−
18.5
195
80
320
−
ns
ns
ns
ns
ns
ns
ON
V
= 50 V, I
≅
75 A, V
=
10
V
,
D GS
= 2.0
W
DD
GS
R
t
td
t
d(ON)
t
r
−
Turn
−
Off Delay Time
Fall Time
−
(OFF)
t
f
190
−
−
Turn
−
Off Time
410
OFF
GATE CHARGE SPECIFICATIONS
V
= 50 V, I
= 75 A,
D
= 1.0 mA
Q
T
o
tal Gate Charge
V
= 0 V to 20 V
= 0 V to 10 V
= 0 V to 2 V
−
−
−
−
−
393
211
14
475
255
16.5
−
nC
nC
nC
nC
nC
DD
g(TOT)
GS
GS
GS
I
g(REF)
Q
Gate Charge at 10 V
V
V
g(10)
Q
Threshold Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
g(TH)
Q
Q
26
gs
74
−
gd
CAPACITANCE SPECIFICATIONS
C
Input Capacitance
V
= 25
V
, V
= 0 V,
−
−
−
7585
2345
630
−
−
−
pF
pF
pF
ISS
DS
GS
f = 1 MHz
C
Output Capacitance
OSS
RSS
C
Reverse Transfer Capacitance
SOURCE TO DRAIN DIODE SPECIFICATIONS
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
−
TYP
−
MAX
UNITS
V
SD
Source to Drain Diode Voltage
I
I
I
I
= 75 A
= 35 A
1.25
1.00
150
490
V
V
SD
SD
SD
SD
−
−
= 75 A, dI
/dt = 100 A/
m
s
t
rr
Reverse Recovery Time
−
−
−
−
ns
SD
= 75 A, dI
/dt = 100 A/
m
s
Q
Reverse Recovered Charge
nC
SD
RR
3
HUF75652G3
TYPICAL PERFORMANCE CURVES
1.2
1.0
0.8
0.6
0.4
0.2
0
80
60
40
20
0
V
= 10V
GS
25
50
75
100
125
150
175
0
25
50
75
100
125
150
175
T
C
, CASE TEMPERATURE (
5
C)
T
C
, CASE TEMPERATURE (
5
C)
Figure 1. NORMALIZED POWER DISSIPATION vs
CASE TEMPERATURE
Figure 2. MAXIMUM CONTINUOUS DRAIN
CURRENT vs CASE TEMPERATURE
2
DUTY CYCLE
−
DESCENDING ORDER
1
0.5
0.2
0.1
0.05
0.02
0.01
0.1
P
DM
NOTES:
DUTY FACTOR: D = t
/t
t
1
SINGLE PULSE
1
2
t
2
PEAK T
= P
y
Z
y
R
+ T
JC C
q
JC
q
J
DM
0.01
−
5
−
4
−
3
10
−
2
10
−
1
0
1
10
10
10
10
10
t, RECTANGULAR PULSE DURATION (s)
Figure 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
2000
1000
T
C
= 25
5
C
FOR TEMPERATURES
ABOVE 25
5
C DERATE PEAK
CURRENT AS FOLLOWS:
V
= 10V
GS
175
−
T
C
V
= 20V
I = I
GS
25
150
TRANSCONDUCTANCE
100 MAY
LIMIT CURRENT
IN THIS REGION
50
−
5
10
−
4
10
−
3
10
−
2
10
−
1
10
0
1
10
10
t, PULSE WIDTH (s)
Figure 4. PEAK CURRENT CAPABILITY
4
HUF75652G3
TYPICAL PERFORMANCE CURVES
(continued)
1000
100
1000
If R = 0
t
= (L)(I
)/(1.3
y
RATED BV
−
V
)
AV
AS
DSS
DD
If R
0
0
t
AV
= (L/R)ln[(I
y
R)/(1.3
y
RATED BV
−
V )
+1]
AS
DSS DD
100
m
s
STARTING T
= 25
5
C
J
100
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
DS(ON)
10
1
STARTING T
= 150
5
C
J
10ms
SINGLE PULSE
T
J
= MAX RATED
T
C
= 25
5
C
10
0.01
1
10
100
5
0
0
0.1
10
1
t
AV
, TIME IN AVALANCHE (ms)
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
Figure 5. FORWARD BIAS SAFE OPERATING AREA
Figure 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
200
200
150
100
50
V
= 7V
= 6V
V
V
GS
= 20V
= 10V
GS
PULSE DURATION = 80
m
s
GS
V
DUTY CYCLE = 0.5% MAX
GS
V
DD
= 15V
150
100
V
GS
=5V
T
J
= 175
5
C
T
J
= 25
5
C
50
0
PULSE DURATION = 80
m
s
DUTY CYCLE = 0.5% MAX
T
C
= 25
5
C
T
J
=
−
55
5
C
0
0
1
2
3
4
2
3
4
5
6
V
GS
, GATE TO SOURCE VOLTAGE (V)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. TRANSFER CHARACTERISTICS
Figure 8. SATURATION CHARACTERISTICS
1.2
1.0
0.8
2.5
2.0
PULSE DURATION = 80
m
s
DUTY CYCLE = 0.5% MAX
V
GS
= V
, I
= 250
m
A
DS D
1.5
1.0
0.5
0.6
0.4
V
GS
= 10V, I
= 75A
D
−
80
−
40
0
40
80
120
160
200
−
80
−
40
0
40
80
120 160
200
T
J
, JUNCTION TEMPERATURE (
5
C)
T
J
, JUNCTION TEMPERATURE (
5
C)
Figure 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATU
Figure 10. NORMALIZED GATE THRESHOLD VOLTAGE
vs JUNCTION TEMPERATURE
5
HUF75652G3
TYPICAL PERFORMANCE CURVES
(continued)
20000
10000
1.2
1.1
I
D
= 250
m
A
C
ISS
= C
+ C
GS GD
C
RSS
= C
GD
1000
100
C
^
C +
C
OSS
DS
GD
1.0
0.9
V
= 0V, f = 1MHz
1.0
GS
−
80
−
40
0
40
80
120
160
200
0.1
10
100
V
, DRAIN TO SOURCE VOLTAGE (V)
T
J
, JUNCTION TEMPERATURE (
5
C)
DS
Figure 11. NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE vs JUNCTION
TEMPERATURE
Figure 12. CAPACITANCE vs DRAIN TO SOURCE
VOLTAGE
10
V
= 50V
DD
8
6
4
2
0
WAVEFORMS IN
DESCENDING ORDER:
I
I
= 75A
= 35A
D
D
0
50
100
150
200
250
Q ,
GATE CHARGE (nC)
g
Figure 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
6
HUF75652G3
TEST CIRCUITS AND WAVEFORMS
V
DS
BV
DSS
L
t
P
V
DS
I
VARY t
TO OBTAIN
P
AS
+
V
DD
R
REQUIRED PEAK I
AS
G
V
DD
−
V
GS
DUT
t
P
I
AS
0V
0
0.01
W
t
AV
Figure 14. UNCLAMPED ENERGY TEST CIRCUIT
Figure 15. UNCLAMPED ENERGY WAVEFORMS
V
DS
V
Q
DD
R
L
g(TOT)
V
DS
V
= 20V
GS
V
GS
Q
g(10)
+
V
DD
V
= 10V
V
GS
GS
−
DUT
V
= 2V
GS
I
0
G(REF)
Q
g(TH)
Q
Q
gd
gs
I
g(REF)
0
Figure 17. GATE CHARGE WAVEFORM
Figure 16. GATE CHARGE TEST CIRCUIT
V
t
t
DS
ON
OFF
t
d(OFF)
t
d(ON)
t
t
f
R
L
r
V
DS
90%
90%
+
V
GS
V
−
DD
10%
10%
0
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
Figure 18. SWITCHING TIME TEST CIRCUIT
Figure 19. SWITCHING TIME WAVEFORM
7
HUF75652G3
PSPICE Electrical Model
.SUBCKT HUF75652 2 1 3 ;
rev 11 May 1999
CA 12 8
11.0e
−
9
CB 15 14
11.4e
−
9
CIN 6 8
6.95e
−
9
DBODY 7 5 DBODYMOD
DBREAK 5 11
DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
LDRAIN
DPLCAP
10
DRAIN
2
5
RLDRAIN
RSLC1
EBREAK 11 7 17
18 117.5
EDS 14 8 5 8
1
DBREAK
51
+
RSLC2
EGS 13 8 6 8
1
ESLC
ESG 6 10 6 8 1
EVTHRES 6 21 19 8
1
EVTEMP 20 6 18 22 1
11
−
50
+
−
17
18
−
DBODY
RDRAIN
6
ESG
8
EBREAK
MWEAK
IT 8 17 1
EVTHRES
+
+
16
21
−
19
8
LDRAIN 2 5 1.0e
−
9
LGATE 1
9 5.74e
−
9
LSOURCE 3 7
4.65e
−
9
LGATE
EVTEMP
+
RGATE
GATE
1
6
−
18
22
MMED
9
20
MSTRO
8
RLGATE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
LSOURCE
CIN
SOURCE
3
7
RSOURCE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 2.80e
−
3
RGATE 9 20
0.85
RLSOURCE
S1A
S2A
RBREAK
12
RLDRAIN 2 5 10
15
13
14
13
17
18
RLGATE 1 9 57.4
8
RLSOURCE 3 7 46.5
RVTEMP
19
S1B
S2B
RSLC1 5 51 RSLCMOD 1e
−
6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD
2.50e
−
3
RVTHRES 22 8 RVTHRESMOD
1
RVTEMP 18 19 RVTEMPMOD 1
13
CB
CA
IT
14
−
+
+
VBAT
6
8
5
8
EGS
EDS
+
−
−
8
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
22
RVTHRES
VBAT 22 19
DC 1
ESLC 51 50 VALUE={(V(5,51) /ABS(V(5,51)))*(PWR(V(5,51)/(1e
−
6*455),2))}
.MODEL DBODYMOD D (IS = 6.55e
−
12 IKF = 30
RS = 1.69e
−
3 TR
=
S
1
1.95e
−
3 TRS2
= 1.05e
−
6 CJO
= 8.71e
−
9 TT
= 7.81e
−
8 M = 0.50)
.MODEL DBREAKMOD D (RS = 1.45e
−
1TRS1 = 1.02e
−
4TRS2 = 1.11e
−
7)
.MODEL DPLCAPMOD D (CJO = 1.00e
−
8IS = 1e
−
3 0N
= 1 M = 0.85)
.MODEL MMEDMOD NMOS (VTO = 2.91 KP = 6.50 IS = 1e
−
30 N = 10 TOX = 1 L = 1u W = 1u RG = 0.85)
.MODEL MSTROMOD NMOS (VTO = 3.37 KP = 205 IS = 1e
−
30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.56 KP = 0.10 IS = 1e
−
30 N = 10 TOX = 1 L = 1u W = 1u RG = 8.5 )
.MODEL RBREAKMOD RES (TC1 = 1.09e
−
3TC2 = 1.04e
−
7)
.MODEL RDRAINMOD RES (TC1 = 1.38e
−
2 TC2
= 3.75e
−
5)
.MODEL RSLCMOD RES (TC1 = 1.05e
−
4 TC2 = 2.13e
−
7)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 =
−
2.92e
−
3 TC2 =
−
1.48e
−
5)
.MODEL RVTEMPMOD RES (TC1 =
−
3.0e
−
3TC2 = 1.21e
−
6)
.MODEL S1AMOD VSWITCH (RON = 1e
−
5 ROFF
= 0.1
VON =
−
5.0 VOFF=
−
3.0)
.MODEL S1BMOD VSWITCH (RON = 1e
−
5 ROFF
= 0.1
VON =
−
3.0 VOFF=
−
5.0)
.MODEL S2AMOD VSWITCH (RON = 1e
−
5 ROFF
= 0.1
VON =
−
2.0 VOFF=
0.0)
.MODEL S2BMOD VSWITCH (RON = 1e
−
5 ROFF
= 0.1
VON = 0.0
VOFF=
−
2.0)
.ENDS
NOTE: For
further discussion of the PSPICE model, consult
A New PSPICE Sub
−
Circuit for the Power MOSFET Featuring Global
Temperature Options
; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank W heatley.
8
HUF75652G3
SABER Electrical Model
REV 11 May 1999
template ta75652 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod =
(is = 6.55e
−
12, cjo = 8.71e
−
9, tt = 7.81e
−
8, m = 0.50)
d..model dbreakmod = ()
d..model dplcapmod =
(cjo = 1.0e
−
8, is = 1e
−
30, n=1, m = 0.85 )
m..model mmedmod = (type=_n, vto = 2.91, kp = 6.5, is = 1e
−
30, tox = 1)
m..model mstrongmod = (type=_n, vto = 3.37, kp = 205, is = 1e
−
30, tox = 1)
m..model mweakmod = (type=_n, vto = 2.56, kp = 0.1, is = 1e
−
30, tox = 1)
sw_vcsp..model s1amod =
(ron = 1e
−
5, roff = 0.1, von =
−
5, voff =
−
3)
LDRAIN
RLDRAIN
RDBODY
DPLCAP
DRAIN
2
5
sw_vcsp..model s1bmod =
(ron =1e
−
5, roff = 0.1, von =
−
3, voff =
−
5)
10
sw_vcsp..model s2amod =
(ron = 1e
−
5, roff = 0.1, von =
−
2, voff = 0)
sw_vcsp..model s2bmod =
(ron = 1e
−
5, roff = 0.1, von = 0, voff =
−
2)
RSLC1
51
RDBREAK
72
c.ca n12 n8 = 11.0e
−
9
c.cb n15 n14 = 11.4e
−
9
c.cin n6 n8 = 6.95e
−
9
RSLC2
ISCL
DBREAK
50
−
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
71
RDRAIN
6
ESG
11
8
EVTHRES
+
+
16
21
−
19
8
MWEAK
i.it n8 n17 = 1
LGATE
EVTEMP
+
DBODY
RGATE
GATE
1
6
−
18
22
EBREAK
+
l.ldrain n2 n5 = 1e
−
9
l.lgate n1 n9 = 5.74e
−
9
l.lsource n3 n7 = 4.65e
−
9
MMED
9
20
MSTRO
17
RLGATE
18
LSOURCE
CIN
−
SOURCE
3
8
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
7
RSOURCE
RLSOURCE
S1A
S2A
14
res.rbreak n17 n18
= 1, tc1 = 1.09e
−
3, tc2 = 1.04e
−
7
RBREAK
12
15
13
res.rdbody n71 n5 = 1.69e
−
3, tc1 = 1.95e
−
3, tc2 = 1.05e
−
6
17
18
8
13
S2B
res.rdbreak n72 n5 = 1.45e
−
1, tc1 = 1.02e
−
4, tc2 = 1.11e
−
7
res.rdrain n50 n16
= 2.80e
−
3, tc1 = 1.38e
−
2, tc2 = 3.75e
−
5
res.rgate n9 n20 = 0.85
RVTEMP
19
S1B
13
CB
CA
res.rldrain n2 n5 = 10
IT
14
−
+
+
res.rlgate n1 n9 = 57.4
VBAT
6
8
5
8
res.rlsource n3 n7 = 46.5
EGS
EDS
+
res.rslc1 n5 n51
= 1e
−
6, tc1 = 1.05e
−
4, tc2 = 2.13e
−
7
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7
= 2.50e
−
3, tc1 = 0, tc2 = 0
res.rvtemp n18 n19
= 1, tc1 =
−
3.0e
−
3, tc2 = 1.21e
−
6
−
−
8
22
RVTHRES
res.rvthres n22 n8
= 1, tc1 =
−
2.92e
−
3, tc2 =
−
1.48e
−
5
spe.ebreak n11 n7 n17 n18 = 117.5
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51
−
>n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e
−
9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/455))** 2))
}
}
9
HUF75652G3
SPICE Thermal Model
JUNCTION
th
REV 1April 1999
HUF75652T
RTHERM1
CTHERM1
CTHERM1 th 6 9.75e
−
3
CTHERM2 6 5 3.90e
−
2
CTHERM3 5 4 2.50e
−
2
CTHERM4 4 3 2.95e
−
2
CTHERM5 3 2 6.55e
−
2
CTHERM6 2 tl 12.55
6
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
RTHERM1 th 6 1.96e
−
3
RTHERM2 6 5 4.89e
−
3
RTHERM3 5 4 1.38e
−
2
RTHERM4 4 3 7.73e
−
2
RTHERM5 3 2 1.17e
−
1
RTHERM6 2 tl 1.55e
−
2
5
SABER Thermal Model
SABER thermal model HUF75652T
4
3
2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 9.75e
−
3
ctherm.ctherm2 6 5 = 3.90e
−
2
ctherm.ctherm3 5 4 = 2.50e
−
2
ctherm.ctherm4 4 3 = 2.95e
−
2
ctherm.ctherm5 3 2 = 6.55e
−
2
ctherm.ctherm6 2 tl = 12.55
rtherm.rtherm1 th 6 = 1.96e
−
3
rtherm.rtherm2 6 5 = 4.89e
−
3
rtherm.rtherm3 5 4 = 1.38e
−
2
rtherm.rtherm4 4 3 = 7.73e
−
2
rtherm.rtherm5 3 2 = 1.17e
−
1
rtherm.rtherm6 2 tl = 1.55e
−
2
}
tl
CASE
PSPICE is a trademark of MicroSim Corporation.
Saber is a registered trademark of Sabremark Limited Partnership.
10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO
−
247
−
3LD SHORT LEAD
CASE 340CK
ISSUE A
DATE 31 JAN 2019
P1
D2
A
E
P
A
A2
Q
E2
S
D1
D
E1
B
2
2
1
3
L1
A1
b4
L
c
(3X) b
(2X) b2
M
M
B A
0.25
MILLIMETERS
MIN NOM
MAX
4.58 4.70 4.82
2.20 2.40 2.60
1.40 1.50 1.60
1.17 1.26 1.35
1.53 1.65 1.77
2.42 2.54 2.66
0.51 0.61 0.71
20.32 20.57 20.82
(2X) e
DIM
A
A1
A2
b
b2
b4
c
GENERIC
D
MARKING DIAGRAM*
D1 13.08
~
~
D2
E
0.51 0.93 1.35
15.37 15.62 15.87
AYWWZZ
XXXXXXX
XXXXXXX
E1 12.81
~
~
E2
e
L
4.96 5.08 5.20
5.56
15.75 16.00 16.25
3.69 3.81 3.93
3.51 3.58 3.65
XXXX = Specific Device Code
~
~
A
Y
= Assembly Location
=
Y
e
ar
WW =
Work Week
ZZ =
Assembly Lot Code
L1
P
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb
−
Free indicator, “G” or microdot “
G
”, may
or may not be present. Some products may
not follow the Generic Marking.
P1 6.60 6.80 7.00
Q
S
5.34 5.46 5.58
5.34 5.46 5.58
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13851G
TO
−
247
−
3LD SHORT LEAD
PAGE 1 OF 1
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