onsemi-FDMC8010
| Part # | onsemi-FDMC8010 |
Download  | onsemi-FDMC8010 |
FDMC8010
MOSFET
– N-Channel,
POWERTRENCH
)
30
V
,
7
5 A, 1.3 m
W
General Description
This N
−
Channel MOSFET is produced using ON Semiconductor’s
advanced POWERTRENCH process that has been especially tailored
to minimize the on
−
state resistance. This device is well suited for
Pin 1
Pin 1
S
S
S
G
applications where ultra low r
is required in small spaces such as
DS(on)
High performance VRM, POL and Oring functions.
D
D
D
D
Features
Top
Bottom
•
Max r
•
Max r
= 1.3 m
W
at V
= 10
V
, I
=
3
0 A
GS D
DS(on)
DS(on)
PQFN8 3.3×3.3, 0.65P
CASE 483AW
Power 33
= 1.8 m
W
at V
= 4.5
V
, I
=
2
5 A
GS
D
•
High Performance Technology for Extremely Low r
DS(on)
•
These Devices are Pb
−
Free and are RoHS Compliant
Applications
MARKING DIAGRAM
•
DC
−
DC Buck Converters
•
Point of Load
•
High Efficiency Load Switch and Low Side Switching
•
Oring FET
$Y&Z&3&K
FDMC
8010
MOSFET MAXIMUM RATINGS
(T =
25
°
C Unless Otherwise Noted)
A
Symbol
V
DS
Parameter
Drain to Source Voltage
Ratings Units
30
20
V
V
A
$Y
&Z
&3
&K
= ON Semiconductor Logo
= Assembly Plant Code
= Numeric Date Code
= Lot Code
V
GS
Gate to Source Volage (Note 4)
I
D
Drain Current
−
Continuous (Package limited)
T
C
= 25
°
C
75
166
30
−
Continuous (Silicon limited)
T
C
= 25
°
C
FDMC8010
= Specific Device Code
−
Continuous
−
Pulsed
T
A
= 25
°
C (Note 1a)
120
E
AS
P
D
Single Pulse Avalance Energy (Note 3)
153
54
mJ
W
Power Dissipation
T
C
= 25
°
C
Power Dissipation
T
A
= 25
°
C (Note 1a)
S
S
D
D
2.4
T
J
, T
STG
Operating and Storage Junction
T
e
mperature
Range
−
55 to
+150
°
C
S
D
D
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
G
THERMAL CHARACTERISTICS
Symbol
R
θ
JC
Parameter
Ratings
1.3
Unit
°
C/W
°
C/W
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 2 of this data sheet.
Thermal Resistance, Junction to Case
R
θ
JA
Thermal Resistance, Junction to Ambient
(Note 1a)
53
©
Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
July, 2019
−
Rev. 2
FDMC8010/D
FDMC8010
PACKAGE MARKING AND ORDERING INFORMATION
Device Marking
Device
Package
Power 33
Reel Size
Tape Width
Quantity
FDMC8010
FDMC8010
13”
12 mm
3000 Units
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise noted)
J
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
BV
Drain to Source Breakdown Voltage
I
D
= 1 mA, V
= 0 V
30
V
DSS
GS
D
BV
/
D
T
Breakdown Voltage
T
e
mperature Coef-
I =
1 mA, referenced to 25
°
C
15
mV/
°
C
DSS
J
D
ficient
m
A
I
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
V
= 24
V
, V
= 0 V
1
DSS
DS
GS
I
V
GS
= 20
V
, V
= 0 V
100
nA
GSS
DS
ON CHARACTERISTICS
V
GS(th)
Gate to Source Threshold Voltage
V
GS
= V
, I
= 1 mA
1.2
1.5
2.5
V
DS
D
D
V
/D
T
Gate to Source Threshold Voltage
T
e
m-
I =
1 mA, referenced to 25
°
C
−
5
mV/
°
C
GS(th)
J
D
perature Coefficient
r
Static Drain to Source On Resistance
m
W
V
= 10 V, I
= 30 A
0.9
1.3
1.3
188
1.3
1.8
2
DS(on)
GS
GS
GS
DS
D
V
V
V
= 4.5
V
, I
= 25 A
D
= 10 V, I
= 30 A, T
= 125
°
C
D
J
g
FS
Forward Transconductance
= 5
V
, I
= 30 A
S
D
DYNAMIC CHARACTERISTICS
V
= 15
V
, V
= 0 V,
C
Input Capacitance
4405
1570
167
5860
2090
250
pF
pF
pF
W
DS
GS
iss
f = 1 MHz
C
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
oss
C
rss
R
0.1
0.5
1.25
g
SWITCHING CHARACTERISTICS
V
= 15 V, I
= 30 A, V
= 10 V,
D GS
GEN
t
Turn
−
On Delay Time
Rise Time
15
7.5
40
27
15
64
11
94
45
ns
ns
DD
d(on)
R
= 6
W
t
r
t
Turn
−
Off Delay Time
Fall Time
ns
d(off)
t
f
5.3
67
ns
V
= 15 V
Q
Q
T
o
tal Gate Charge
T
o
tal Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
V
GS
= 0 V to 10 V
= 0 V to 4.5 V
nC
nC
nC
nC
DD
g
g
I
D
= 30 A
V
GS
32
Q
gs
Q
gd
10
9.5
DRAIN
−
SOURCE DIODE CHARACTERISTICS
V
Source to Drain Diode Forward Voltage
V =
0 V, I
= 2 A
(Note 2)
V
0.6
0.7
49
1.2
1.2
78
SD
GS
S
V
GS
= 0
V
, I
=
3
0
A
(
Note 2)
S
t
I =
30 A, di/dt = 100 A/
m
s
F
Reverse Recovery Time
ns
rr
Q
Reverse Recovery Charge
29
46
nC
rr
2
FDMC8010
NOTES:
1. R
2
is determined with the device mounted on a 1 in
pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR
−
4 material. R
is guaranteed
θ
θ
JC
JA
by design while R
is determined by the user’s board design.
θ
CA
a. 53
°
C/W when mounted
on a
1 in
pad of
2 oz
copper.
b. 125
°
C/W when mounted on
a
minimum pad of 2 oz copper.
2
2. Pulse
T
e
st: Pulse Width < 300
μ
s, Duty cycle < 2.0 %.
3. E
of 153 mJ is based on starting T
= 25
°
C, L = 0.3 mH, I
= 32 A, V
= 27
V
, V
=
1
0
V
.
1
00% test at L = 0.1 mH, I
= 47 A.
AS
J
AS
DD
GS
AS
4. As
an N
−
ch device, the negative Vgs rating is for low duty cycle pulse occurrence only. No continuous rating is implied.
3
FDMC8010
TYPICAL CHARACTERISTICS
T =
25
°
C Unless Otherwise Noted
J
120
80
40
0
5
4
V
= 10 V
GS
V
= 4.5 V
GS
V
= 4 V
GS
PULSE DURATION = 80
m
s
DUTY CYCLE = 0.5% MAX
V
GS
= 3 V
V
= 3.5 V
GS
3
V
GS
= 4 V
V
V
= 3.5 V
GS
2
1
V
GS
= 10 V
PULSE DURATION = 8
0
m
s
DUTY CYCLE = 0.5% MAX
= 4.5 V
V
GS
= 3 V
GS
0
0.0
0.2
0.4
0.6
0
40
80
120
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
I ,
DRAIN CURRENT (A)
D
Figure 1. On
−
Region Characteristics
Figure 2. Noormalized On
−
Resistance vs
Drain Current and Gate Voltage
1.6
1.4
1.2
1.0
0.8
0.6
5
4
I
V
= 30 A
D
PULSE DURATION = 80
m
s
DUTY CYCLE = 0.5% MAX
= 10 V
GS
I
D
= 30 A
3
T
= 125
°
C
= 25
°
C
J
2
1
0
T
J
−
75
−
50
−
25
0
25 50 75
100 125 150
2
4
6
8
10
T , JUNCTION TEMPERATURE (
°
C)
J
V
GS
, GATE TO SOURCE VOLTAGE (V)
Figure 3. Normalized On Resistance vs
Junction Temperature
Figure 4. On
−
Resistance vs Gate to Source
Voltage
120
80
40
0
200
100
V
GS
= 0 V
PULSE DURATION = 80
m
s
DUTY CYCLE = 0.5% MAX
10
1
V
DS
= 5 V
T
J
= 150
°
C
T
J
= 150
°
C
T
J
= 25
°
C
T
J
= 25
°
C
0.1
T
J
=
−
55
°
C
0.01
0.001
T
=
−
55
°
C
J
1.0
1.5
2.0
2.5
3.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
V
GS
, GATE TO SOURCE VOLTAGE (V)
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
Figure 6. Source to Drain Diode Forward
Voltage vs Source Current
4
FDMC8010
TYPICAL CHARACTERISTICS
(continued)
T =
25
°
C Unless Otherwise Noted
J
10
8
10000
C
iss
I
D
= 30 A
V
DD
= 12 V
C
oss
V
DD
= 15 V
V
DD
= 18 V
6
1000
100
4
C
rss
2
f = 1 MHz
V
GS
= 0 V
0
0
20
40
60
80
0.1
1
10
, DRAIN TO SOURCE VOLTAGE (V)
DS
30
Q ,
GATE CHARGE (nC)
V
g
Figure 7. Gate Charge Characteristics
Figure 8. Capacitance vs Drain to Source
Voltage
100
10
1
200
150
100
50
R
q
= 2.3
°
C/W
JA
T =
25
°
C
J
V
GS
= 10 V
T =
100
°
C
J
V
GS
= 4.5 V
T =
125
°
C
J
Limited by Package
0
0.001
0.01
0.1
1
10
100 500
25
50
75
100
125
150
t ,
TIME IN AVALANCHE (ms)
AV
T ,
CASE TEMPERATURE (
°
C)
C
Figure 9. Unclamped Inductive Switching
Capability
Figure 10. Maximum Continuous Drain
Current vs Case Temperature
200
100
3000
1000
100
m
s
SINGLE PULSE
R
= 125
°
C/W
q
JA
T
= 25
°
C
A
10
1
100
10
1 ms
THIS AREA IS
LIMITED BY r
DS(on)
10 ms
100 ms
SINGLE PULSE
T
J
= MAX RATED
1 s
0.1
0.01
R
q
JA
= 125
°
C/W
10 s
DC
T
A
= 25
°
C
1
0.5
0.01
0.1
1
10
100200
10
−
4
10
−
3
10
−
2
t, PULSE WIDTH (sec)
10
−
1
1
10
100 1000
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Figure 11. Forward Bias Safe Operating Area
Figure 12. Single Pulse Maximum Power
Dissipation
5
FDMC8010
TYPICAL CHARACTERISTICS
(continued)
T =
25
°
C Unless Otherwise Noted
J
2
1
DUTY CYCLE
−
DESCENDING ORDER
D = 0.5
0.2
0.1
0.01
0.1
0.05
0.02
0.01
P
DM
t
1
t
2
NOTES:
DUTY FACTOR: D = t
/t
SINGLE PULSE
0.001
1
2
R
= 125
°
C/W
q
JA
PEAK T
= P
x Z
x R
+ T
q
JA A
J
DM
q
JA
0.0001
10
−
4
10
−
3
10
−
2
10
−
1
t, RECTANGULAR PULSE DURATION (sec)
11
0
100
1000
Figure 13. Junction
−
to
−
Ambient Transient Thermal Response Curve
POWERTRENCH are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other
countries.
6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFN8 3.3X3.3, 0.65P
CASE 483AW
ISSUE A
DATE 10 SEP 2019
GENERIC
MARKING DIAGRAM*
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb
−
Free indicator, “G” or microdot “
G
”, may
or may not be present. Some products may
not follow the Generic Marking.
XXXX = Specific Device Code
A
Y
= Assembly Location
=
Y
e
ar
XXXX
AYWW
WW =
Work Week
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13672G
WDFN8 3.3X3.3, 0.65P
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
©
Semiconductor Components Industries, LLC, 2018
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at
www.onsemi.com/site/pdf/Patent
−
Marking.pdf
. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMEN
T
:
TECHNICAL SUPPORT
North American Technical Support:
Voice Mail: 1 800
−
282
−
9855
T
o
ll Free USA/Canada
Phone: 011 421 33 790 2910
Europe, Middle East and Africa Technical Support:
Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative
◊
