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CSD19535KTT
SLPS539B
–
M
ARCH 201
5
–
R
EVISED JANUARY 2017
CSD19535KTT 100-V N-Channel NexFET™ Power MOSFET
1 Features
Product Summary
1
•
•
•
•
•
•
•
Ultra-Low Q
g
and Q
gd
T
A
= 25°C
V
DS
TYPICAL VALUE
UNIT
V
Low-Thermal Resistance
Avalanche Rated
Drain-to-Source Voltage
Gate Charge Total (10 V)
Gate Charge Gate-to-Drain
100
75
Q
g
nC
nC
Lead-Free Terminal Plating
RoHS Compliant
Q
gd
11
V
GS
= 6 V
3.2
2.8
R
DS(on)
Drain-to-Source On Resistance
V
GS(th)
Threshold Voltage
m
Ω
V
GS
= 10 V
Halogen Free
2.7
V
D
2
PAK Plastic Package
Device Information
(1)
2 Applications
DEVICE
QTY
MEDIA
PACKAGE
SHIP
•
•
•
Hot Swap
CSD19535KTT
CSD19535KTTT
500
50
Tape
and
Reel
D
2
PAK Plastic
Package
13-Inch Reel
Motor Control
Secondary Side Synchronous Rectifier
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
3 Description
This 100-V, 2.8 m
Ω
, D
2
PAK (TO-263) NexFET™
power MOSFET is designed to minimize losses in
power conversion applications.
Absolute Maximum Ratings
T
A
= 25°C
VALUE
UNIT
V
V
DS
Drain-to-Source Voltage
V
GS
Gate-to-Source Voltage
Continuous Drain Current (Package Limited)
Continuous Drain Current (Silicon Limited),
100
±20
V
.
200
Pin Out
197
139
I
D
T
C
= 25°C
A
Drain (Pin 2)
Continuous Drain Current (Silicon Limited),
T
C
= 100°C
I
DM
P
D
Pulsed Drain Current
(1)
400
300
A
Power Dissipation, T
C
= 25°C
W
T
J
,
T
stg
Operating Junction,
Storage Temperature
–55 to 175
451
°C
Gate
(Pin 1)
Avalanche Energy, Single Pulse
I
D
= 95 A, L = 0.1 mH
E
AS
mJ
Source (Pin 3)
(1) Max
R
θ
JC
= 0.5°C/W, pulse duration
≤
100 µs, duty cycle
≤
1%.
.
.
Gate Charge
R
DS(on)
vs V
GS
10
10
I
D
= 100 A
V
DS
= 50 V
T
C
= 25°C, I
D
= 100 A
T
C
= 125°C, I
D
= 100 A
9
9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
0
2
4
6
8
10
12
14
16
18
20
0
8
16
24
32
40
48
56
64
72
80
V
GS
– Gate-to-Source Voltage (V)
Q
g
– Gate Charge (nC)
D007
D004
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD19535KTT
SLPS539B
–
M
ARCH 201
5
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EVISED JANUARY 2017
Table of Contents
6.2 Community
Resources……………………………………….
7
6.3 Trademark
s
.
……………………………………………………..
7
6.4 Electrostatic
Discharge Cautio
n
.
………………………….
7
6.5 Glossar
y
.
………………………………………………………….
7
1
2
3
4
5
Feature
s
…………………………………………………………
1
Applications
…………………………………………………..
1
Description
…………………………………………………….
1
Revision History
……………………………………………..
2
Specifications
…………………………………………………
3
5.1 Electrical
Characteristics…………………………………….
3
5.2 Thermal
Informatio
n
.
………………………………………….
3
5.3 Typical
MOSFET Characteristic
s
.
………………………..
4
Device and Documentation Support
………………..
7
6.1 Receiving
Notification of Documentation Updates….
7
7
Mechanical, Packaging, and Orderable
Information
…………………………………………………….
8
7.1 KTT
Package Dimensions ………………………………….
8
7.2 Recommended
PCB Pattern……………………………….
9
7.3 Recommended
Stencil Opening (0.125 mm Stencil
Thickness)…………………………………………………………
9
6
4 Revision
History
Changes from Revision A (May 2015) to Revision B
Page
•
•
•
•
Added
Receiving Notification of Documentation Updates
section to
Device and Documentation Support
section……………
7
Changed the drawing in
KTT Package Dimensions
section ……………………………………………………………………………………..
8
Changed the drawing in
Recommended PCB Pattern
section…………………………………………………………………………………..
9
Changed the drawing in
Recommended Stencil Opening (0.125 mm Stencil Thickness)
section ………………………………….
9
Changes from Original (March 2015) to Revision A
Page
•
Added
Community Resources
……………………………………………………………………………………………………………………………..
7
2
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5 Specifications
5.1 Electrical
Characteristics
T
A
= 25°C (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
STATIC CHARACTERISTICS
BV
DSS
I
DSS
Drain-to-source voltage
V
GS
= 0 V, I
D
= 250
μ
A
100
V
Drain-to-source leakage current
Gate-to-source leakage current
Gate-to-source threshold voltage
V
GS
= 0 V, V
DS
= 80 V
V
DS
= 0 V, V
GS
= 20 V
V
DS
= V
GS
, I
D
= 250
μ
A
V
GS
= 6 V, I
D
= 100 A
V
GS
= 10 V, I
D
= 100 A
V
DS
= 10 V, I
D
= 100 A
1
100
3.4
4.1
3.4
μ
A
nA
V
I
GSS
V
GS(th)
2.2
2.7
3.2
2.8
301
R
DS(on)
g
fs
Drain-to-source on resistance
Transconductance
m
Ω
S
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
R
G
Input capacitance
6100
1160
29
7930
1510
38
pF
pF
pF
Ω
Output capacitance
Reverse transfer capacitance
Series gate resistance
Gate charge total (10 V)
Gate charge gate-to-drain
Gate charge gate-to-source
Gate charge at V
th
Output charge
V
GS
= 0 V, V
DS
= 50 V, ƒ = 1 MHz
1.4
75
2.8
Q
g
98
nC
nC
nC
nC
nC
ns
ns
ns
ns
Q
gd
Q
gs
Q
g(th)
Q
oss
t
d(on)
t
r
11
V
DS
= 50 V, I
D
= 100 A
V
DS
= 50 V, V
GS
= 0 V
25
16
210
9
Turnon delay time
Rise time
18
V
DS
= 50 V, V
GS
= 10 V,
I
DS
= 100 A, R
G
= 0
Ω
t
d(off)
t
f
Turnoff delay time
Fall time
21
15
DIODE CHARACTERISTICS
V
SD
Q
rr
t
rr
Diode forward voltage
Reverse recovery charge
Reverse recovery time
I
SD
= 100 A, V
GS
= 0 V
0.9
435
85
1.1
V
nC
ns
V
DS
= 50 V, I
F
= 100 A,
di/dt = 300 A/
μ
s
5.2 Thermal
Information
T
A
= 25°C (unless otherwise stated)
THERMAL METRIC
Junction-to-case thermal resistance
Junction-to-ambient thermal resistance
MIN
TYP
MAX
UNIT
°C/W
°C/W
R
θ
JC
R
θ
JA
0.5
62
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5.3 Typical
MOSFET Characteristics
T
A
= 25°C (unless otherwise stated)
Figure 1. Transient Thermal Impedance
200
175
150
125
100
75
200
T
C
= 125°C
T
C
= 25°C
T
C
= -55°C
175
150
125
100
75
50
50
V
GS
= 6 V
V
GS
= 8 V
V
GS
= 10 V
25
0
25
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
2
3
4
5
6
7
V
DS
– Drain-to-Source Voltage (V)
V
GS
– Gate-to-Source Voltage (V)
D002
D003
V
DS
= 5 V
Figure 2. Saturation Characteristics
Figure 3. Transfer Characteristics
4
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Typical MOSFET Characteristics (continued)
T
A
= 25°C (unless otherwise stated)
50000
10000
10
9
8
7
6
5
4
3
2
1
0
1000
100
10
C
iss
= C
gd
+ C
gs
C
oss
= C
ds
+ C
gd
C
rss
= C
gd
1
0
10
20
30
40
50
60
70
80
90 100
0
8
16
24
32
40
48
56
64
72
80
V
DS
– Drain-to-Source Voltage (V)
Q
g
– Gate Charge (nC)
D005
D004
V
DS
= 50 V
I
D
= 100 A
Figure 5. Capacitance
Figure 4. Gate Charge
3.3
10
9
8
7
6
5
4
3
2
1
T
C
= 25°C, I
D
= 100 A
T
C
= 125°C, I
D
= 100 A
3.1
2.9
2.7
2.5
2.3
2.1
1.9
1.7
1.5
1.3
0
0
2
4
6
8
10
12
14
16
18
20
-75 -50 -25
0
25 50 75
100 125 150 175 200
V
GS
– Gate-to-Source Voltage (V)
T
C
– Case Temperature (°C)
D007
D006
I
D
= 250 µA
Figure 7. On-State Resistance vs Gate-to-Source Voltage
Figure 6. Threshold Voltage vs Temperature
100
2.4
2.2
2
T
C
= 25°C
T
C
= 125°C
V
GS
= 6 V
V
GS
= 10 V
10
1.8
1.6
1.4
1.2
1
1
0.1
0.01
0.8
0.6
0.4
0.001
0.0001
-75 -50 -25
0
25 50 75
100 125 150 175 200
0
0.2
0.4
0.6
0.8
1
T
C
– Case Temperature (°C)
V
SD
– Source-to-Drain Voltage (V)
D008
D009
I
D
= 100 A
Figure 8. Normalized On-State Resistance vs Temperature
Figure 9. Typical Diode Forward Voltage
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Typical MOSFET Characteristics (continued)
T
A
= 25°C (unless otherwise stated)
1000
500
100
T
C
= 25
è
C
T
C
= 125
è
C
100
10
1
DC
10 ms
1 ms
100 µs
10 µs
0.1
0.1
10
0.01
1
10
100
1000
0.1
1
V
DS
– Drain-to-Source Voltage (V)
T
AV
– Time in Avalanche (ms)
D010
D011
Single pulse, max R
θ
JC
= 0.5°C/W
Figure 10. Maximum Safe Operating Area
Figure 11. Single Pulse Unclamped Inductive Switching
225
200
175
150
125
100
75
50
25
0
-50 -25
0
25
50
75 100
125 150 175 200
T
C
– Case Temperature (°C)
D012
Figure 12.
Maximum Drain Current vs Temperature
6
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CSD19535KTT
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6 Device
and Documentation Support
6.1 Receiving
Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on
Alert me
to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
6.2 Community
Resources
The following links connect to TI community resources. Linked contents are provided “AS IS” by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI’s views; see TI’s
Terms of
Use
.
TI E2E™ Online Community
TI’s Engineer-to-Engineer (E2E) Community.
Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support
TI’s Design Support
Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
6.3 Trademarks
NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
6.4 Electrostatic
Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6.5 Glossary
SLYZ022
—
TI Glossary
.
This glossary lists and explains terms, acronyms, and definitions.
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7 Mechanical,
Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 KTT
Package Dimensions
15.5
14.7
9.25
9.05
A
B
3
10.26
10.06
2X 5.08
2
1
1.36
1.23
2[.0]X
0.9
2[.0]X
1.75 MAX
0.77
0.25
C
A
B
1.4
1.17
0.47
0.34
4.7
4.4
8
0
C
0.25
0
1.32
1.22
2.6
2
0.25
GAGE PLANE
7.48
7.08
8°
0°
8.55
8.15
2.6
2
0.25
GAGE PLANE
OPTIONAL LEAD FORM
EXPOSED
THERMAL PAD
NOTE 3
Notes:
1. All
linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning
and tolerancing per ASME Y14.5M.
2. This
drawing is subject to change without notice.
3. Features
may not exist and shape may vary per different assembly sites.
Table 1. Pin Configuration
POSITION
Pin 1
DESIGNATION
Gate
Pin 2 / Tab
Pin 3
Drain
Source
8
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7.2 Recommended
PCB Pattern
PKG
(3.4)
(6.9)
(R0.05) TYP
PKG
SYMM
(5.08)
(8.55)
2X (1.05)
2X (3.82)
(7.48)
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
For recommended circuit layout for PCB designs, see
Reducing Ringing Through PCB Layout Techniques
(SLPA005).
7.3 Recommended
Stencil Opening (0.125 mm Stencil Thickness)
(1.17) TYP
42X (0.97)
(0.48) TYP
2X (3.82)
2X (1.05)
42X (0.95)
(R0.05) TYP
(1.15) TYP
SYMM
(5.08)
(6.9)
PKG
Notes:
1. This
package is designed to be soldered to a thermal pad on the board. See application notes
PowerPAD™
Thermally Enhanced Package
(SLMA002) and
PowerPAD™ Made Easy
(SLMA004) for more information.
2. Laser
cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525
may have alternate design recommendations.
3. Board
assembly site may have different recommendations for stencil design.
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PACKAGE OPTION ADDENDUM
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package
Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
500
50
(1)
(2)
(3)
(4/5)
(6)
CSD19535KTT
CSD19535KTTT
ACTIVE
DDPAK/
TO-263
KTT
3
3
RoHS-Exempt
& Green
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-55 to 175
-55 to 175
CSD19535KTT
CSD19535KTT
ACTIVE
DDPAK/
TO-263
KTT
RoHS-Exempt
& Green
SN
(1)
The marketing status values are defined as follows:
ACTIVE:
Product device recommended for new designs.
LIFEBUY:
TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND:
Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW:
Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE:
TI has discontinued the production of the device.
(2)
RoHS:
TI defines “RoHS” to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, “RoHS” products are suitable for use in specified lead-free processes. TI may
reference these types of products as “Pb-Free”.
RoHS Exempt:
TI defines “RoHS Exempt” to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green:
TI defines “Green” to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. – The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a “~” will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material – Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:
The information provided on this page represents TI’s knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI’s liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
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