VBsemi-Elec-MTP2N50E-VB
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MTP2N50E
N-Channel
65
0 V (D-S)MOSFET
FEATURES
• Low
Gate Charge Q
g
Results in Simple Drive
Requirement
PRODUCT SUMMARY
V
DS
(V)
650
A
v
aila
b
le
R
DS(on)
(
Ω
)
V
GS
= 10 V
1.7
RoHS
• Improved
Gate, Avalanche and Dynamic dV/dt
Ruggedness
COMPLIANT
Q
g
(Max.) (nC)
48
12
Q
Q
gs
(nC)
gd
(nC)
• Fully Characterized Capacitance and Avalanche Voltage
and Current
19
• Compliant
to RoHS directive 2002/95/EC
Configuration
Single
TO-220AB
D
G
S
G D
S
N-Channel MOSFET
Top View
ABSOLUTE MAXIMUM RATINGS
T
C
= 25 °C, unless otherwise noted
PARAMETER
SYMBOL
LIMIT
UNIT
Drain-Source Voltage
V
DS
650
V
Gate-Source Voltage
V
GS
± 30
Continuous Drain Current
e
T
C
= 25 °C
T
C
=
1
0
0
°
C
4.
5
V
GS
at 10 V
I
D
A
Continuous Drain Current
4.2
Pulsed Drain Current
a
I
DM
18
Linear Derating Factor
0.48
W/°C
mJ
A
Single Pulse Avalanche Energy
b
Repetitive Avalanche Current
a
Repetitive Avalanche Energy
a
Maximum Power Dissipation
Peak Diode Recovery dV/dt
c
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
d
E
AS
I
AR
325
4
E
AR
6
mJ
W
T
C
= 25 °C
P
D
60
dV/dt
T
J
, T
stg
2.8
– 55 to + 150
300
V/ns
°C
for 10 s
10
lbf · in
N · m
Mounting Torque
6-32 or M3 screw
1.1
Notes
a. Repetitive
rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Starting
T
J
= 25 °C, L = 24 mH, R
G
= 25
Ω
, I
AS
=
3
.
2
A (see fig. 12).
c. I
SD
≤
3
.2 A, dI/dt
≤
90 A/µs, V
DD
≤
V
DS
, T
J
≤
150 °C.
d. 1.6
mm from case.
e. Drain
current limited by maximum junction temperature.
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1
MTP2N50E
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
65
UNIT
Maximum Junction-to-Ambient
Maximum Junction-to-Case (Drain)
R
thJA
R
thJC
–
–
°C/W
2.1
SPECIFICATIONS
T
J
= 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
V
DS
Δ
V
DS
/T
J
V
GS(th)
I
GSS
V
GS
= 0 V, I
D
= 250 µA
Reference to 25 °C, I
D
= 1 mA
d
V
DS
= V
GS
, I
D
= 250 µA
V
GS
= ± 30 V
650
–
–
–
V
mV/°C
V
V
DS
Temperature Coefficient
–
670
Gate-Source Threshold Voltage
Gate-Source Leakage
2.5
–
–
4.5
± 100
25
250
–
–
nA
V
DS
= 650 V, V
GS
= 0 V
–
–
–
Zero Gate Voltage Drain Current
I
DSS
µA
V
DS
= 520 V, V
GS
= 0 V, T
J
= 125 °C
V
GS
= 10 V
I
D
= 3.1 A
b
–
Drain-Source On-State Resistance
Forward Transconductance
Dynamic
R
DS(on)
g
fs
–
Ω
1
.
7
–
V
DS
= 50 V, I
D
= 3.1 A
3.9
–
S
Input Capacitance
C
iss
C
oss
C
rss
–
–
–
–
–
–
–
1017
170
7.0
1912
48
–
–
V
GS
= 0 V,
V
DS
= 25 V,
f = 1.0 MHz, see fig. 5
Output Capacitance
Reverse Transfer Capacitance
–
pF
V
DS
= 1.0 V, f = 1.0 MHz
–
Output Capacitance
C
oss
V
GS
= 0 V
V
DS
= 520 V, f = 1.0 MHz
V
DS
= 0 V to 520 V
c
–
Effective Output Capacitance
Total Gate Charge
C
oss
eff.
Q
g
84
–
–
48
I
D
=
3.2
A, V
DS
= 400 V
Gate-Source Charge
Gate-Drain Charge
Q
gs
Q
gd
V
GS
= 10 V
–
–
–
–
12
19
nC
ns
see fig. 6 and 13
b
Turn-On Delay Time
Rise Time
t
d(on)
t
r
t
d(off)
t
f
–
–
–
–
14
20
34
18
–
–
–
–
V
DD
= 325 V, I
D
= 3.2 A
R
G
= 9.1
Ω
, R
D
= 62
Ω
,
see fig. 10
b
Turn-Off Delay Time
Fall Time
Drain-Source Body Diode Characteristics
MOSFET symbol
showing the
integral reverse
p – n junction diode
D
Continuous Source-Drain Diode Current
Pulsed Diode Forward Current
a
I
S
–
–
–
–
4
A
G
I
SM
21
S
T
J
= 25 °C, I
S
=
3
.
2
A, V
GS
= 0 V
b
Body Diode Voltage
V
SD
t
rr
–
–
–
–
1.5
739
3.2
V
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Forward Turn-On Time
493
2.1
ns
µC
T
J
= 25 °C, I
F
=
3
.
2
A, dI/dt = 100 A/µs
b
Q
rr
t
on
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
and L
D
)
Notes
a. Repetitive
rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse
width
≤
300 µs; duty cycle
≤
2 %.
c. C
oss
eff. is a fixed capacitance that gives the same charging time as C
oss
while V
DS
is rising from 0 % to 80 % V
DS
.
d. t
= 60 s, f = 60 Hz.
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2
MTP2N50E
TYPICAL CHARACTERISTICS
25 °C, unless otherwise noted
10
10
V
GS
15
V
10
V
TOP
8
.0
V
7.0
V
6.0
V
5.5
V
5.0
V
BOTTOM 4.5
V
5
5
1
°
T =
150 C
J
°
T =
25 C
J
1
20
µ
s PULSE
W
IDTH
V
= 100
V
DS
20
µ
s PULSE
W
IDTH
4.5
V
°
T =
25 C
J
0.1
0.1
0.1
4.0
1
10
100
5.0
6.0
7.0
8
.0
9.0
V
, Drain-to-So
u
rce
V
oltage (
V
)
V
, Gate-to-So
u
rce
V
oltage (
V
)
DS
GS
Fig. 3 – Typical Transfer Characteristics
Fig. 1 – Typical Output Characteristics
10
8
.0
5
.5
5
.0
3
.5
2
.0
0.5
0.0
V
GS
3.2
A
=
I
D
TOP
15
V
10
V
8
.0
V
7.0
V
6.0
V
5.5
V
5.0
V
BOTTOM 4.5
V
5
4.5
V
1
20
µ
s PULSE
W
IDTH
T =
150 C
V
=
1
0
V
°
GS
J
0.1
-60 -40 -20
0
20 40 60
8
0 100
120 140 160
1
10
100
°
T ,
J
u
nction Temperat
u
re (
C)
V
, Drain-to-So
u
rce
V
oltage (
V
)
J
DS
Fig. 2 – Typical Output Characteristics
Fig. 4 – Normalized On-Resistance vs. Temperature
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3
MTP2N50E
2000
10
V
= 0
V
,
f = 1MHz
GS
iss
C
C
C
= C
+ C
,
C
SHORTED
gs
gd
ds
= C
rss
oss
gd
= C
+ C
ds
gd
1600
1200
8
00
400
0
iss
5
°
T =
150 C
oss
rss
J
1
°
T =
25 C
J
V
= 0
V
GS
1.0
0.1
A
0.2
0.4
0.6
0.
8
1.2
1
10
100
1000
V
,So
u
rce-to-Drain
V
oltage (
V
)
V
, Drain-to-So
u
rce
V
oltage (
V
)
SD
DS
Fig. 5 – Typical Capacitance vs. Drain-to-Source Voltage
Fig. 7 – Typical Source-Drain Diode Forward Voltage
20
10
I
D
=
3.2
A
OPERATIO
N
I
N
THIS AREA LIMITED
V
V
V
=
= 325
V
= 130
V
DS
DS
DS
BY R
DS(on)
16
12
8
10
u
s
5
100
u
s
1ms
1
10ms
4
°
T =
25 C
C
°
T =
150 C
Single P
u
lse
J
FOR TEST CIRCUIT
SEE FIGURE 13
0.1
0
10
100
1000
10000
0
10
20
30
40
50
V
, Drain-to-So
u
rce
V
oltage (
V
)
Q ,
Total Gate Charge (nC)
Fig. 6 – Typical Gate Charge vs. Gate-to-Source Voltage
DS
Fig. 8 – Maximum Safe Operating Area
G
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MTP2N50E
R
D
V
DS
6.0
5.0
4.0
3.0
2.0
1.0
V
GS
D.U.T.
R
G
+
–
V
DD
10
V
P
u
lse
w
idth
≤
1
µ
s
D
u
ty factor
≤
0.1
%
Fig. 10a – Switching Time Test Circuit
V
DS
90
%
0.0
25
50
75
100
125
°
150
10
%
T ,
Case Temperat
u
re (
C)
C
V
GS
t
t
t
t
d(off) f
d(on)
r
Fig. 9 – Maximum Drain Current vs. Case Temperature
Fig. 10b – Switching Time Waveforms
10
D = 0.50
1
0.20
0.10
P
2
DM
0.05
0.1
t
1
0.02
0.01
t
2
N
otes:
1. D
u
ty factor D =
2. Peak T
=
P
J
SI
N
GLE PULSE
t /
t
1
x Z
(THERMAL RESPO
N
SE)
+ T
C
DM
thJC
0.01
0.00001
0.0001
0.001
0.01
0.1
1
10
t ,
Rectang
u
lar P
u
lse D
u
ration (s)
1
Fig. 11 – Maximum Effective Transient Thermal Impedance, Junction-to-Case
V
DS
t
15
V
p
Dri
v
er
L
V
DS
D.U.T.
R
G
+
–
V
A
DD
I
AS
A
20
V
I
0.01
Ω
t
p
AS
Fig. 12b – Unclamped Inductive Waveforms
Fig. 12a – Unclamped Inductive Test Circuit
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MTP2N50E
8
00
600
400
200
0
I
D
TOP
2.3A
3.3A
BOTTOM
4
A
Q
Q
G
10
V
Q
GS
GD
V
G
Charge
Fig. 13a – Basic Gate Charge Waveform
25
50
75
100
125
°
150
Starting T
, J
u
nction Temperat
u
re (
C)
C
u
rrent reg
u
lator
J
Same type as D.U.T.
Fig. 12c – Maximum Avalanche Energy vs. Drain Current
50 k
Ω
12
V
0.2
µ
F
0.3
µ
F
8
00
7
8
0
760
740
720
700
+
–
V
DS
D.U.T.
V
GS
3 mA
I
G
I
D
C
u
rrent sampling resistors
Fig. 13b – Gate Charge Test Circuit
A
0
1
2
3
4
5
6
I
, A
v
alanche C
u
rrent (A)
a
v
Fig. 12d – Typical Drain-to Source Voltage vs. Avalanche
Current
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MTP2N50E
Peak Diode Recovery dV/dt Test Circuit
+
Circ
u
it layo
u
t considerations
Lo
w
stray ind
u
ctance
D.U.T.
•
•
Gro
u
nd plane
•
Lo
w
leakage ind
u
ctance
c
u
rrent transformer
–
+
–
–
+
R
G
•
d
V
/dt controlled
b
y R
G
+
–
•
Dri
v
er same type as D.U.T.
•
I
SD
controlled
b
y d
u
ty factor “D”
•
D.U.T. – de
v
ice
u
nder test
V
DD
Dri
v
er gate dri
v
e
P.
W
.
P.
W
.
Period
Period
D =
V
= 10
V
*
GS
D.U.T. I
w
a
v
eform
SD
Re
v
erse
reco
v
ery
c
u
rrent
Body diode for
w
ard
c
u
rrent
dI/dt
D.U.T.
V w
a
v
eform
DS
Diode reco
v
ery
d
V
/dt
V
DD
Re-applied
v
oltage
Body diode for
w
ard drop
Ripple
≤
5
%
Ind
u
ctor cr
u
rent
I
SD
*
V
GS
= 5
V
for logic le
v
el de
v
ices
Fig. 14 – For N-Channel
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MTP2N50E
TO-220AB
MILLIMETERS
MIN.
INCHES
A
E
DIM.
MAX.
4.65
1.01
1.73
0.61
15.49
10.51
2.67
5.28
1.40
6.48
2.92
14.02
3.82
3.94
3.00
MIN.
MAX.
0.183
0.040
0.068
0.024
0.610
0.414
0.105
0.208
0.055
0.255
0.115
0.552
0.150
0.155
0.118
F
A
b
4.25
0.69
1.20
0.36
14.85
10.04
2.41
4.88
1.14
6.09
2.41
13.35
3.32
3.54
2.60
0.167
0.027
0.047
0.014
0.585
0.395
0.095
0.192
0.045
0.240
0.095
0.526
0.131
0.139
0.102
Ø P
b(1)
c
D
E
e
e(1)
F
H(1)
J(1)
L
1
3
2
L(1)
Ø P
Q
*
M
b(1)
ECN: X12-0208-Rev. N, 08-Oct-12
DWG: 5471
Notes
* M = 1.32 mm to 1.62 mm (dimension including protrusion)
Heatsink hole for HVM
C
b
e
J(1)
e(1)
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8
MTP2N50E
Disclaimer
All products due to improve reliability, function or design or for other reasons, product specifications and
data are subject to change without notice.
Taiwan VBsemi Electronics Co., Ltd., branches, agents, employees, and all persons acting on its or their
representatives (collectively, the “
T
aiwan VBsemi”), assumes no responsibility for any errors, inaccuracies or
incomplete data contained in the table or any other any disclosure of any information related to the
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any goods or continuous production.
T
o
t
he maximum extent permitted by applicable law on
T
aiwan VBsemi
relinquished: (1) any application and all liability arising out of or use of any products; (2) any and all liability,
including but not limited to special, consequential damages or incidental ; (3) any and all implied warranties,
including a particular purpose, non-infringement and merchantability guarantee.
Statement on certain types of applications are based on knowledge of the product is often used in a typical
application of the general product VBsemi
T
aiwan demand that the Taiwan VBsemi of. Statement on whether the
product is suitable for a particular application is non-binding. It is the customer’s responsibility to verify specific
product features in the products described in the specification is appropriate for use in a particular application.
Parameter data sheets and technical specifications can be provided may vary depending on the application and
performance over time. All operating parameters, including typical parameters must be made by customer’s
technical experts validated for each customer application. Product specifications do not expand or modify
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aiwan
VBsemi purchasing terms and conditions, including but not limited to warranty herein.
Unless expressly stated in writing,
T
aiwan VBsemi products are not intended for use in medical, life saving,
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T
aiwan VBsemi such applications using client did not express their
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aiwan VBsemi people who are related to product design applications and
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Material Category Policy
Taiwan VBsemi Electronics Co., Ltd., hereby certify that all of the products are determined to be
RoHS compliant and meets the definition of restrictions under Directive of the European Parliament
2011/65 / EU, 2011 Nian. 6. 8 Ri Yue restrict the use of certain hazardous substances in electrical and
electronic equipment (EEE) – modification, unless otherwise specified as
inconsistent.(www.VBsemi.com)
Please note that some documents may still refer to Taiwan VBsemi RoHS Directive 2002/95 / EC. We
confirm that all products identified as consistent with the Directive 2002/95 / EC European Directive
2011/65 /.
Taiwan VBsemi Electronics Co., Ltd. hereby certify that all of its products comply identified as
halogen-free halogen-free standards required by the JEDEC JS709A. Please note that some Taiwanese
VBsemi documents still refer to the definition of IEC 61249-2-21, and we are sure that all products
conform to confirm compliance with IEC 61249-2-21 standard level JS709A.
