onsemi-FDC638P
| Part # | onsemi-FDC638P |
Download  | onsemi-FDC638P |
September 2001
FDC638P
P-Channel 2.5V PowerTrench
Ò
Specified MOSFET
General Description
Features
This
P
–
Channel 2.5V specified MOSFET is produced
·
–4.5 A, –20 V
.
R
DS(ON)
= 48 m
W
@ V
GS
= –4.5 V
R
DS(ON)
= 65 m
W
@ V
GS
= –2.5 V
using
Fairchild
Semiconductor’s
advanced
PowerTrench process that has been especially tailored
to minimize the on-state resistance and yet maintain
low gate charge for superior switching performance
·
Low gate charge (10 nC typical)
These devices are well suited for battery power
applications: load switching and power management,
battery charging circuits, and DC/DC conversion.
·
High performance trench technology for extremely
low R
DS(ON)
·
SuperSOT ™ –6 package: small footprint (72%
smaller than standard SO-8; low profile (1mm thick)
S
D
1
6
5
4
D
2
3
TM
G
SuperSOT
-6
D
pin
1
D
Absolute Maximum Ratings
T
A
=25
o
C unless otherwise noted
Symbol
Parameter
Ratings
Units
V
DSS
Drain-Source Voltage
–20
V
V
GSS
I
D
Gate-Source Voltage
±
8
–4.5
V
A
Drain Current
– Continuous
– Pulsed
(Note 1a)
–20
P
D
Power Dissipation for Single Operation
(Note 1a)
(Note 1b)
1.6
W
0.8
T
J
, T
STG
Operating and Storage Junction Temperature Range
–55 to +150
°
C
Thermal Characteristics
°
C/W
°
C/W
R
q
JA
Thermal Resistance, Junction-to-Ambient
(Note 1a)
(Note 1)
78
30
R
q
J
C
Thermal Resistance, Junction-to-Case
Package Marking and Ordering Information
Device Marking
Device
Reel Size
Tape width
Quantity
.638
FDC638P
7’’
8mm
3000 units
Ó
2001 Fairchild Semiconductor Corporation
FDC638P Rev F1 (W)
Electrical Characteristics
T
A
= 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min Typ Max Units
Off Characteristics
BV
DSS
Drain–Source Breakdown Voltage
V
GS
= 0 V, I
D
= –250
m
A
–20
V
Breakdown Voltage Temperature
Coefficient
D
BV
DSS
D
T
J
I
D
= –250
m
A,Referenced to 25
°
C
V
DS
= –16 V,
V
GS
= 0 V
–14
mV/
°
C
I
DSS
Zero Gate Voltage Drain Current
Gate–Body Leakage, Forward
Gate–Body Leakage, Reverse
–1
m
A
nA
nA
I
GSSF
I
GSSR
V
GS
= 8 V,
V
DS
= 0 V
V
DS
= 0 V
100
V
GS
= –8 V,
–100
On Characteristics
(Note 2)
V
GS(th)
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coefficient
V
DS
= V
G
S
,
I
D
= –250
m
A
–0.4
–20
–0.8
3
–1.5
V
D
V
GS(th)
D
T
J
R
DS(on)
I
D
= –250
m
A,Referenced to 25
°
C
mV/
°
C
m
W
Static Drain–Source
On–Resistance
39
52
54
48
65
72
V
GS
= –4.5 V,
I
D
= –4.5 A
V
GS
= –2.5 V,
I
D
= –3.8 A
V
GS
= –4.5 V, I
D
= –4.5 T
J
=125
°
C
I
D(on)
g
FS
On–State Drain Current
V
GS
= –4.5 V,
V
DS
= –5 V
A
S
Forward Transconductance
V
DS
= –10 V,
I
D
= –4.5 A
15
Dynamic Characteristics
C
Input Capacitance
1160
195
pF
pF
pF
iss
V
DS
= –10 V,
f = 1.0 MHz
V
GS
= 0 V,
C
oss
Output Capacitance
C
rss
Reverse Transfer Capacitance
105
Switching Characteristics
(Note 2)
t
d(on)
t
r
t
d(off)
t
f
Turn–On Delay Time
Turn–On Rise Time
Turn–Off Delay Time
Turn–Off Fall Time
Total Gate Charge
Gate–Source Charge
Gate–Drain Charge
V
DD
= –5 V,
V
GS
= –4.5 V,
R
GEN
= 6
W
I
D
= –1 A,
12
9
22
18
53
22
14
ns
ns
33
12
10
2.2
1.5
ns
ns
Q
g
V
DS
= –10 V,
V
GS
= –4.5 V
I
D
= –4.5 A,
nC
nC
nC
Q
gs
Q
gd
Drain–Source Diode Characteristics and Maximum Ratings
I
S
Maximum Continuous Drain–Source Diode Forward Current
–1.3
A
V
Drain–Source Diode Forward
V
SD
V
GS
= 0 V,
I
S
= –1.3 A
(Note 2)
–0.73 –1.2
Voltage
Notes:
1.
R
q
J
A
is the sum of the j
u
n
ction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins.
R
q
J
C
is guaranteed by design while R
q
C
A
is determined by the user’s board design.
a)
78°C/W when
mounted on a 1in
pad
of 2 oz copper
b)
156°C/W when mounted
on a minimum pad of 2 oz
copper
2
Scale 1 : 1 on letter size paper
2.
Pulse Test: Pulse Width < 300
m
s, Duty Cycle < 2.0%
FDC638P Rev F (W)
Typical Characteristics
20
1.6
1.4
1.2
1
V
GS
= -4.5V
-2.5V
-3.0V
15
V
GS
= -2.5V
-2.0V
10
5
-3.0V
-3.5V
-4.0V
-4.5V
0
0.8
0
1
2
3
4
0
5
10
-I
D
, DRAIN CURRENT (A)
15
20
–
V
D
S
, DRAIN TO SOURCE VOLTAGE (V)
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
1.6
0.15
I
D
= -4.5A
I
D
= -2.2A
V
GS
= -4.5V
1.4
0.12
0.09
0.06
0.03
0
1.2
1
T
A
= 125
o
C
T
A
= 25
o
C
0.8
0.6
-50
-25
0
25
50
75
100
125
150
1
2
3
4
5
T
J
, JUNCTION TEMPERATURE
(
o
C)
–
V
GS
, GATE TO SOURCE VOLTAGE (V)
Figure 3. On-Resistance Variation with
Temperature.
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
15
100
V
D
S
= -5V
T
A
= -55
o
C
V
GS
= 0V
25
o
C
125
o
C
10
12
9
1
T
A
= 12
5
o
C
0.1
25
o
C
6
0.01
-55
o
C
3
0.001
0
0.0001
0.5
1
1.5
2
2.5
0
0.2
0.4
0.6
0.8
1
1.2
–
V
GS
, GATE TO SOURCE VOLTAGE (V)
–
V
S
D
, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics.
Figure 6. Body Diode Forward Voltage Variation
with Source Current and Temperature.
FDC638P Rev F (W)
Typical Characteristics
5
1500
1200
900
600
300
0
V
D
S
= -5V
f = 1 MHz
V
GS
= 0 V
I
D
= -4.5A
-10V
C
ISS
4
3
2
1
0
-15V
C
OSS
C
RSS
0
3
6
9
12
0
5
10
15
20
Q
g
, GATE CHARGE (nC)
–
V
D
S
, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics.
Figure 8. Capacitance Characteristics.
100
10
50
40
30
20
10
0
SINGLE PULSE
R
q
JA
= 156°C/W
T
A
= 25°C
R
DS(ON)
LIMIT
1ms
10ms
100ms
1s
1
10s
DC
V
GS
= -4.5V
SINGLE PULSE
0.1
0.01
R
q
JA
= 156
o
C/W
T
A
= 25
o
C
0.1
1
10
100
0.001
0.01
0.1
1
10
100
–
V
D
S
, DRAIN-SOURCE VOLTAGE (V)
t
1
, TIME (sec)
Figure 9. Maximum Safe Operating Area.
Figure 10. Single Pulse Maximum
Power Dissipation.
1
D = 0.5
R
q
J
A
(t) = r(t) +
R
q
JA
R
q
JA
= 156
o
C/W
0.2
0.1
0.1
0.05
P(pk)
0.02
0.01
t
1
t
2
0.01
T
J
– T
A
= P *
R
q
JA
(t)
SINGLE PULSE
Duty Cycle, D = t
1
/
t
2
100 1000
0.001
0.0001
0.001
0.01
0.1
1
10
t
1
, TIME (sec)
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1b
Transient thermal response will change depending on the circuit board design.
FDC638P Rev F (W)
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
â
SMART START™
STAR*POWER™
Stealth™
VCX™
FAST
ACEx™
Bottomless™
CoolFET™
OPTOLOGIC™
OPTOPLANAR™
PACMAN™
FASTr™
FRFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
GlobalOptoisolator™
GTO™
HiSeC™
ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™
MICROWIRE™
CROSSVOL
T
™
DenseTrench™
DOME™
POP™
Power247™
PowerTrenc
h
â
QFET™
EcoSPARK™
E
2
CMOS
TM
TinyLogic™
QS™
EnSigna
TM
TruTranslation™
UHC™
QT Optoelectronics™
Quiet Series™
SILEN
T
S
WITCHE
R
â
FACT™
FACT Quiet Series™
UltraFE
T
â
STAR*POWER is used under license
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILIT
Y
,
F
UNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILIT
Y
A
RISING OUT OF THE APPLICATION OR USE O
F
A
NY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICE
S
O
R
S
YSTEM
S
W
ITHOU
T
T
H
E
E
XPRES
S
W
RITTE
N
A
PPROVA
L
O
F
F
AIRCHIL
D
S
EMICONDUCTO
R
C
ORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H4
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FDC638P
Single P-Channel 2.5V Specified PowerTrench MOSFET
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Contents
•
General description
•
Features
•
Models
Product Change Notices
(PCNs)
•
Qualification Support
Datasheet
•
Product status/pricing/packaging
•
Order Samples
Download this
datasheet
Support
Sales support
Quality and reliability
Design center
General description
This P-Channel 2.5V specified MOSFET is produced using Fairchild
Semiconductor’s advanced PowerTrench process that has been especially
tailored to minimize the on-state resistance and yet maintain low gate
charge for superior switching performance These devices are well suited
for battery power applications: load switching and power management,
battery charging circuits, and DC/DC conversion.
e-mail this datasheet
This page
Print version
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This product
Use in FETBench
Analysis
Features
z
-4.5 A, -20 V
{
R
= 48 m
Ω
@ V
= -4.5 V
DS(ON)
GS
{
R
= 65 m
Ω
@ V
= -2.5 V
DS(ON)
GS
z
z
Low gate charge (10nC typical).
High performance trench technology for extremely low R
.
DS(ON)
z
SuperSOT™-6 package: small footprint (72% smaller than standard
SO-8); low profile (1mm thick).
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Product status/pricing/packaging
Product
Product status
Pb-free Status
Pricing* Package
type Leads Packing
method
Package Marking Convention**
Line 1: &E&
(Binary Calendar Year Coding)
Y
FDC638P
Full Production
$0.316
N/A
SSOT-6
SSOT-6
6
6
TAPE REEL
TAPE REEL
Line 2: .638
Line 1: &E&
(Binary Calendar Year Coding)
Y
FDC638P_NF073 Full
Production
Line 2: .638
* Fairchild 1,000 piece Budgetary Pricing
** A sample button will appear if the part is available through Fairchild’s on-line samples program. If there is no sample button, please
contact a
to obtain samples
Indicates product with Pb-free second-level interconnect. For more information
click here.
Package marking information for product FDC638P is available.
Click here for more information
.
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Models
Package & leads
SSOT-6-6
Condition
Temperature range
PSPICE
Software version
Revision date
Electrical
25°C to 125°C
Orcad 9.1
Jan 23, 2001
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Qualification Support
Click on a product for detailed qualification data
Product
FDC638P
FDC638P_NF073
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