Vishay-Intertech-VS-P103KW

VS-P100 Series  

Vishay Semiconductors  

Power Modules,  

Passivated Assembled Circuit Elements, 25 A  

FEATURES  

• Glass passivated junctions for greater reliability  

• Electrically isolated base plate  

• Available up to 1200 V

RRM

/V

DRM  

• High dynamic characteristics  

• Wide choice of circuit configurations  

• Simplified mechanical design and assembly  

• UL E78996 approved  

• Material

 

categorization: for definitions of compliance  

please see

PACE-PAK (D-19)  

DESCRIPTION  

The VS-P100 series of integrated power circuits consists of  

PRIMARY CHARACTERISTICS  

power thyristors and power diodes configured in a single  

package. With its isolating base plate, mechanical designs  

are greatly simplified giving advantages of cost reduction  

and reduced size.  

I

O  

25 A  

Type  

Modules – thyristor, standard  

PACE-PAK (D-19)  

Package  

Applications include power supplies, control circuits and  

battery chargers.  

MAJOR RATINGS AND CHARACTERISTICS  

SYMBOL  

CHARACTERISTICS  

VALUES  

25  

UNITS  

I

O  

85 °C  

A

50 Hz  

60 Hz  

50 Hz  

60 Hz  

357  

I

TSM  

A

375  

637  

I

2

t  

A

2

s  

580  

I

2



t  

6365  

A

2



s  

V

V

DRM

, V

RRM  

400 to 1200  

2500  

V

ISOL  

T

J  

V

Range  

-40 to +125  

-40 to +125  

°C  

°C  

T

Stg  

ELECTRICAL SPECIFICATIONS  

VOLTAGE RATINGS  

V

RRM

/V

DRM

, MAXIMUM  

V

I

REPETITIVE PEAK REVERSE AND  

NON-REPETITIVE PEAK  

TYPE NUMBER  

AT T

J

MAXIMUM  

mA  

PEAK OFF-STATE VOLTAGE  

V

REVERSE VOLTAGE  

V

VS-P101, VS-P121, VS-P131  

VS-P102, VS-P122, VS-P132  

VS-P103, VS-P123, VS-P133  

VS-P103, VS-P124, VS-P134  

VS-P105, VS-P125, VS-P135  

400  

600  

500  

700  

800  

900  

10  

1000  

1200  

1100  

1300  

Revision: 27-Jul-2018  

Document Number: 93754  

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,

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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT  

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH

A

T

VS-P100 Series  

Vishay Semiconductors  

ON-STATE CONDUCTION  

PARAMETER  

SYMBOL  

TEST CONDITIONS  

VALUES  

25  

UNITS  

A

Maximum DC output current at case  

temperature  

I

O  

Full bridge  

85  

°C  

t = 10 ms  

t = 8.3 ms  

t = 10 ms  

t = 8.3 ms  

t = 10 ms  

t = 8.3 ms  

t = 10 ms  

t = 8.3 ms  

357  

375  

300  

315  

637  

580  

450  

410  

No voltage  

reapplied  

Maximum peak, one-cycle non-repetitive  

on-state or forward current  

I

TSM  

I

FSM  

,

A

100 % V

RRM  

reapplied  

Sinusoidal half wave,

  

initial T

J

= T

J

maximum  

No voltage  

reapplied  

Maximum I

2

t for fusing  

I

2

t  

A

2

s  

100 % V

RRM  

reapplied  

t = 0.1 ms to 10 ms, no voltage reapplied

  

I

2

t for time tx = I

2



t ·



tx  

Maximum I

2



t for fusing  

I

2



t  

V

T(TO)  

r

t1  

6365  

0.82  

12  

A

2



s  

V

Maximum value of threshold voltage  

T

J

= 125 °C  

Maximum level value of on-state slope  

resistance  

2

T

J

= 125 °C, average power = V

T(TO)

x I

T(AV)

+ r

t

+ (I

T(RMS)  

)

m

  

Maximum on-state voltage drop  

Maximum forward voltage drop  

V

TM  

V

FM  

I

TM

=



x I

T(AV)  

T

J

= 25 °C  

T

J

= 25 °C  

1.35  

1.35  

V

V

I

FM

=



x I

F(AV)  

Maximum non-repetitive rate of rise of  

turned-on current  

T

J

= 125 °C from 0.67 V

DRM

  

dI/dt  

200  

A/μs  

mA  

I

Maximum holding current  

Maximum latching current  

I

H  

I

L  

T

J

= 25 °C anode supply = 6 V, resistive load, gate open  

T

J

= 25 °C anode supply = 6 V, resistive load  

130  

250  

BLOCKING  

PARAMETER  

SYMBOL  

TEST CONDITIONS  

VALUES  

UNITS  

Maximum critical rate of rise of off-state  

voltage  

dV/dt  

T

J

= 125 °C, exponential to 0.67 V

DRM

gate open  

200  

V/μs  

Maximum peak reverse and off-state  

leakage current at V

RRM

, V

DRM  

I

RRM  

I

DRM  

,

T

J

= 125 °C, gate open circuit  

T

J

= 25 °C  

10  

mA  

μA  

V

Maximum peak reverse leakage current  

I

RRM  

100  

50 Hz, circuit to base, all terminals shorted,

  

T

J

= 25 °C, t = 1 s  

RMS isolation voltage  

V

ISOL  

2500  

TRIGGERING  

PARAMETER  

SYMBOL  

P

GM  

TEST CONDITIONS  

VALUES  

UNITS  

Maximum peak gate power  

Maximum average gate power  

Maximum peak gate current  

Maximum peak negative gate voltage  

8

2

W

P

G(AV)  

I

GM  

2

A

V

-V

GM  

10  

3

T

J

= -40 °C  

T

J

= 25 °C  

Maximum gate voltage required to trigger  

Maximum gate current required to trigger  

V

GT  

2

V

T

J

= 125 °C  

1

Anode supply =

  

6 V resistive load  

T

J

= -40 °C  

90  

60  

35  

0.2  

2

I

GT  

T

J

= 25 °C  

mA  

T

J

= 125 °C  

Maximum gate voltage that will not trigger  

Maximum gate current that will not trigger  

V

GD  

I

GD  

V

T

J

= 125 °C, rated V

DRM

applied  

mA  

Revision: 27-Jul-2018  

Document Number: 93754  

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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT  

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A

T

VS-P100 Series  

Vishay Semiconductors  

THERMAL AND MECHANICAL SPECIFICATIONS  

PARAMETER  

SYMBOL  

TEST CONDITIONS  

VALUES  

UNITS  

Maximum junction operating

  

and storage temperature range  

T

J

, T

Stg  

-40 to +125  

°C  

Maximum thermal resistance,

  

R

thJC  

R

thCS  

DC operation  

Mounting surface, smooth and greased  

2.24  

0.10  

junction to case per junction  

K/W  

Maximum thermal resistance,

  

case to heatsink  

Mounting torque, base to heatsink

(1)  

4

Nm  

g

58  

2.0  

Approximate weight  

oz.  

Case style  

PACE-PAK (D-19)  

Note  

(1)  

A mounting compound is recommended and the torque should be checked after a period of 3 hours to allow for the spread of the compound  

60  

50  

40  

30  

20  

10  

0

60  

50  

40  

30  

20  

10  

0

+

–

~

180°  

(

s

ine)  

T

J

= 125 °C  

20  

25  

0

25  

50  

75  

100  

125  

0

5

10  

15  

93754_01a  

Total Output Current (A)  

93754_01b  

Maximum Allowa

b

le  

Am

b

ient Temperature (°C)  

Fig. 1 – Current Ratings Nomogram (1 Module Per Heatsink)  

20  

15  

DC  

180°  

180°  

120°  

90°  

60°  

30°  

15  

10  

5

120°  

90°  

60°  

30°  

10  

5

RM

S

limit  

RM

S

limit  

Ø

Ø

Conduction period  

Conduction angle  

T

J

= 125 °C  

Per junction  

T

J

= 125 °C  

Per junction  

0

0

0

5

10  

15  

0

5

10  

15  

20  

93754_02  

Average On-

S

tate Current (A)  

Fig. 2 – On-State Power Loss Characteristics  

93754_03  

Average On-

S

tate Current (A)  

Fig. 3 – On-State Power Loss Characteristics  

Revision: 27-Jul-2018  

Document Number: 93754  

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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT  

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A

T

VS-P100 Series  

Vishay Semiconductors  

130  

120  

110  

100  

90  

350  

300  

250  

200  

150  

At any rated load condition and with  

rated V

RRM

applied following

s

urge.  

Initial T

J

= 125 °C  

Fully turned-on  

at 60 Hz 0.0083

s  

at 50 Hz 0.0100

s  

180°  

(Rect.)  

180°  

(

S

ine)  

80  

Per junction  

Per module  

5

70  

0

10  

15  

20  

25  

30  

1

10  

100  

Num

b

er of Equal Amplitu

d

e Half  

93754_04  

Total Output Current (A)  

93754_06  

Cycle Current Pulses (N)  

Fig. 4 – Current Ratings Characteristics  

Fig. 6 – Maximum Non-Repetitive Surge Current  

1000  

100  

10  

400  

Maximum non-repetitive

s

urge current  

ver

s

u

s

pul

s

e train duration. Control of  

conduction may not be maintained.  

Initial T

J

= 125 °C  

T

J

= 25 °C  

350  

T

J

= 125 °C  

No voltage reapplied  

Rated V

RRM

reapplied  

300  

250  

200  

150  

100  

Per junction  

Per junction  

1

0

1

2

3

4

5

6

0.01  

0.1  

1

Instantaneous On-

S

tate Voltage (V)  

93754_05  

Pulse Train Duration (s)  

93754_07  

Fig. 5 – On-State Voltage Drop Characteristics  

Fig. 7 – Maximum Non-Repetitive Surge Current  

10  

S

teady

s

tate value  

R

thJC

= 2.24 K/W  

(DC operation)  

1

0.1  

Per junction  

0.01  

0.0001  

0.001  

0.01  

0.1  

1

10  

93754_08  

S

quare Wave Pulse Duration (s)  

Fig. 8 – Thermal Impedance Z

thJC

Characteristics  

Revision: 27-Jul-2018  

Document Number: 93754  

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T

VS-P100 Series  

Vishay Semiconductors  

100  

(1) P

G

M

= 10 W,

 

t

p

= 5 m

s  

(2) P

G

M

= 20 W,

 

t

p

= 25 m

s  

(3) P

G

M

= 50 W,

 

t

p

= 1 m

s  

(4) P

G

M

= 100 W,

 

t

p

= 500 μ

s  

Rectangular gate pul

s

e  

(a) Recommended load line for  

rated dI/dt: 10 V, 20

Ω

, t

r

≤ 1 μ

s  

(b) Recommended load line for  

rated dI/dt: 10 V, 65

Ω

, t

r

≤ 1 μ

s  

(a)  

10  

(b)  

1

(1)  

(2)  

(3)  

(4)  

V

G

D  

Fre

q

uency limited by P

G

(AV)  

I

G

D  

0.1  

0.001  

0.01  

0.1  

1

10  

100  

93754_09  

Instantaneous

G

ate Current (A)  

Fig. 9 – Gate Characteristics  

ORDERING INFORMATION TABLE  

Device code  

VS-  

P

1

0

2

K

W

1

2

3

4

5

6

7

1

2

3

–

–

–

Vi

s

hay

S

emiconductor

s

product  

Module type  

Current rating  

1 = 25 A DC (P100

s

erie

s

)  

4 = 40 A DC (P400

s

erie

s

)  

–

–

Circuit configuration  

4

5

0 =

s

ingle pha

s

e, hybrid bridge common cathode  

2 =

s

ingle pha

s

e, hybrid bridge doubler connection  

3 =

s

ingle pha

s

e, all

S

CR Bridge  

Voltage code  

1 =

 

400 V  

2 =

 

600 V  

3 =

 

800 V  

4 = 1000 V  

5 = 1200 V  

6

7

–

–

K = optional voltage

s

uppre

ss

ion  

W = optional freewheeling diode  

Revision: 27-Jul-2018  

Document Number: 93754  

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T

VS-P100 Series  

Vishay Semiconductors  

CIRCUIT CONFIGURATION  

CIRCUIT  

CONFIGURATION  

CODE  

CIRCUIT DESCRIPTION  

SCHEMATIC DIAGRAM  

TERMINAL POSITIONS  

G

1  

AC1  

AC2  

AC1

G

1  

AC2

G

2  

–

Single phase, hybrid bridge  

common cathode  

0

2

3

+

G

2  

(-)  

(+)  

G

1  

G

2  

AC2  

AC1  

AC1

G

1  

AC2

G

2  

–

Single phase, hybrid bridge  

doubler connection  

+

(-)  

(+)  

G

3  

G

1  

AC1  

AC2  

AC2

G

2  

G

1

G

4  

AC1

G

3  

–

Single phase, all SCR bridge  

+

G

4

G

2  

(-)  

(+)  

CODING

(1)  

WITH BOTH  

VOLTAGE SUPPRESSION  

AND FREEWHEELING  

DIODE  

CIRCUIT  

CONFIGURATION  

CODE  

WITH  

FREEWHEELING  

DIODE  

BASIC  

SERIES  

WITH VOLTAGE  

SUPPRESSION  

CIRCUIT DESCRIPTION  

Single phase, hybrid bridge  

common cathode  

0

P10.  

P10.K  

P10.W  

P10.KW  

Single phase, hybrid bridge  

doubler connection  

2

3

P12.  

P13.  

P12.K  

P13.K  

–

–

–

–

Single phase, all SCR bridge  

Note  

(1)  

To complete code refer to Voltage Ratings table, i.e.: for 600 V P10.W complete code is P102W  

LINKS TO RELATED DOCUMENTS  

Dimensions  

Revision: 27-Jul-2018  

Document Number: 93754  

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Outline Dimensions  

Vishay Semiconductors  

D-19 PACE-PAK  

DIMENSIONS

in millimeters (inches)  

0.9 x 45°  

(0.035 x 45°)  

Ø 1.65 (0.06)  

12.7 (0.50)

 

12.7 (0.50)  

4.6 (0.18)  

25 (0.98) MAX.  

15.5 (0.61)  

MAX.  

2.5 (0.10)  

MAX.  

63.5 (2.50)  

45 (1.77)  

Fast-on 6.35 x 0.8 (0.25 x 0.03)  

23.2 (0.91)  

32.5 (1.28) MAX.  

5.2 (0.20)  

33.8 (1.33)  

48.7 (1.91)  

Document Number: 95335  

Revision: 24-Jul-08  

For technical questions, contact:

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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other  

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about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular product  

with the properties described in the product specification is suitable for use in a particular application. Parameters provided in  

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Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited  

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Revision: 01-Jan-2023  

Document Number: 91000  

1