Alpha—Omega-Semicon-AO4266E
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AO4266E
60V N-Channel AlphaSGT
TM
General Description
Product Summary
• Trench Power AlphaSGT
TM
technology
• Low R
DS(ON)
• Logic Level Gate Drive
• ESD Protected
V
DS
60V
I
D
(at V
GS
=10V)
R
DS(ON)
(at V
GS
=10V)
11A
< 13.5mΩ
< 18mΩ
R
DS(ON)
(at V
GS
=4.5V)
• Excellent Gate Charge x R
DS(ON)
Product (FOM)
• RoHS and Halogen-Free Compliant
Typical ESD protection
HBM Class 2
Applications
100% UIS Tested
100% Rg
Tested
• High Frequency Switching and Synchronous
Rectification
SOIC-8
D
Top View
Bottom View
D
D
D
D
G
G
PIN1
S
S
S
S
PIN1
Orderable Part Number
Package Type
Form
Minimum Order Quantity
Absolute Maximum Ratings
T
A
=25°C unless otherwise noted
Parameter
Symbol
V
DS
Maximum
Units
Drain-Source Voltage
Gate-Source Voltage
60
±20
11
V
V
V
GS
T
A
=25°C
T
A
=70°C
Continuous Drain
Current
I
D
A
8.5
Pulsed Drain Current
C
Avalanche Current
C
Avalanche energy
V
DS
Spike
G
I
DM
44
I
AS
14
A
mJ
V
C
L=0.3mH
10µs
E
AS
V
SPIKE
29
72
T
A
=25°C
T
A
=70°C
3.1
P
D
W
Power Dissipation
B
2.0
Junction and Storage Temperature Range
T
J
, T
STG
-55 to 150
°C
Thermal Characteristics
Parameter
Symbol
Typ
31
Max
40
Units
°C/W
°C/W
°C/W
Maximum Junction-to-Ambient
A
t ≤
10s
R
θ
JA
Maximum Junction-to-Ambient
A D
Maximum Junction-to-Lead
Steady-State
Steady-State
59
75
R
θ
JL
16
24
Rev.1.0: February 2017
Page 1 of 5
AO4266E
Electrical Characteristics (T
J
=25°C unless otherwise noted)
Symbol Parameter
Conditions
Min
Typ
Max
Units
STATIC PARAMETERS
I
D
=250
µ
A, V
GS
=0V
BV
DSS
Drain-Source Breakdown Voltage
60
V
V
DS
=60V, V
GS
=0V
1
I
DSS
Zero Gate Voltage Drain Current
µA
T
J
=55°C
5
V
DS
=0V, V
GS
=±20V
I
GSS
Gate-Body leakage current
Gate Threshold Voltage
±10
2.2
13.5
21.9
18
µA
V
V
GS(th)
V
DS
=V
GS,
I
D
=250
µ
A
1.2
1.7
11
V
GS
=10V, I
D
=11A
mΩ
R
DS(ON)
Static Drain-Source On-Resistance
T
J
=125°C
17.8
14.3
35
V
GS
=4.5V, I
D
=9A
V
DS
=5V, I
D
=11A
I
S
=1A, V
GS
=0V
mΩ
S
g
FS
V
SD
I
S
Forward Transconductance
Diode Forward Voltage
0.72
1
4
V
Maximum Body-Diode Continuous Current
A
DYNAMIC PARAMETERS
C
iss
C
oss
C
rss
R
g
Input Capacitance
755
220
20
pF
pF
pF
Ω
V
GS
=0V, V
DS
=30V, f=1MHz
Output Capacitance
Reverse Transfer Capacitance
Gate resistance
f=1MHz
0.6
1.3
2.0
SWITCHING PARAMETERS
Q
g
(10V)
Q
g
(4.5V)
Q
gs
Total Gate Charge
13.5
6.5
2.5
3.0
11
5
20
10
nC
nC
nC
nC
nC
ns
Total Gate Charge
V
GS
=10V, V
DS
=30V, I
D
=11A
V
GS
=0V, V
DS
=30V
Gate Source Charge
Gate Drain Charge
Q
gd
Q
oss
t
D(on)
t
r
Output Charge
Turn-On DelayTime
Turn-On Rise Time
V
GS
=10V, V
DS
=30V, R
L
=2.75
Ω
,
GEN
3
ns
t
D(off)
t
f
Turn-Off DelayTime
19
3
ns
Turn-Off Fall Time
ns
t
rr
I
F
=11A, di/dt=500A/
µ
s
I
F
=11A, di/dt=500A/
µ
s
15
45
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
ns
Q
rr
nC
A. The value of R
θ
JA
is measured with the device mounted on 1in
2
FR-4 board with 2oz. Copper, in a still air environment with T
A
=25
°
C. The
value in any given application depends on the user’s specific board design.
B. The power dissipation P
D
is based on T
J(MAX)
=150
°
C, using
≤
10s junction-to-ambient thermal resistance.
C. Repetitive
rating, pulse width limited by junction temperature T
J(MAX)
=150
°
C. Ratings are based on low frequency and duty cycles to keep
initialT
J
=25
°
C.
D. The R
θ
JA
is the sum of the thermal impedance from junction to lead R
θ
JL
and lead to ambient.
E. The static characteristics in Figures 1 to 6 are obtained using <300
µ
s pulses, duty cycle 0.5% max.
F. These curves are based on the junction-to-ambient thermal impedance which is measured with the device mounted on 1in
2
FR-4 board with
2oz. Copper, assuming a maximum junction temperature of T
J(MAX)
=150
°
C. The SOA curve provides a single pulse rating.
APPLICATIONS OR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. AOS DOES NOT
ASSUME ANY LIABILITY ARISING OUT OF SUCH APPLICATIONS OR USES OF ITS PRODUCTS.
AOS RESERVES THE RIGHT TO IMPROVE
PRODUCT DESIGN,FUNCTIONS AND RELIABILITY WITHOUT NOTICE.
Rev.1.0: February 2017
Page 2 of 5
AO4266E
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS
50
50
40
30
20
10
0
10V
4V
V
DS
=5V
3.5V
4.5V
40
30
20
10
0
3V
125
°
C
25
°
C
V
GS
=2.5V
1
2
3
4
5
0
1
2
3
4
5
V
GS
(Volts)
V
DS
(Volts)
Figure 2: Transfer Characteristics (Note E)
Figure 1: On-Region Characteristics (Note E)
25
20
15
10
5
2
1.8
1.6
1.4
1.2
1
V
GS
=10V
I
D
=11A
V
GS
=4.5V
V
GS
=10V
V
GS
=4.5V
I
D
=9A
0.8
0
0
25
50
75
100
125
150
175
0
3
6
9
12
15
I
D
(A)
Temperature (°C)
Figure 3: On-Resistance vs. Drain Current and Gate
Voltage (Note E)
Figure 4: On-Resistance vs. Junction Temperature
(Note E)
40
35
30
25
20
15
10
5
1.0E+01
1.0E+00
1.0E-01
1.0E-02
1.0E-03
1.0E-04
1.0E-05
I
D
=11A
125
°
C
125
°
C
25
°
C
25
°
C
2
4
6
8
10
0.0
0.2
0.4
0.6
0.8
1.0
V
GS
(Volts)
V
SD
(Volts)
Figure 5: On-Resistance vs. Gate-Source Voltage
(Note E)
Figure 6: Body-Diode Characteristics
(Note E)
Rev.1.0: February 2017
Page 3 of 5
AO4266E
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS
10
1000
V
DS
=30V
I
D
=11A
C
iss
8
800
600
400
200
0
6
4
C
oss
2
C
rss
0
0
3
6
9
12
15
0
10
20
30
40
50
60
Q
g
(nC)
V
DS
(Volts)
Figure 7: Gate-Charge Characteristics
Figure 8: Capacitance Characteristics
1000.0
100.0
10.0
1.0
1000
100
10
T
J(Max)
=150
°
C
T
A
=25
°
C
10
µ
s
R
DS(ON)
limited
100
µ
s
1ms
10ms
T
J(Max)
=150
°
C
T
A
=25
°
C
0.1
DC
0.0
1
0.01
0.1
1
10
100
1E-05
0.001
0.1
Pulse Width (s)
10
V
DS
(Volts)
V
GS
> or equal to 4.5V
Figure 9: Maximum Forward Biased Safe
Operating Area (Note F)
Figure 10: Single Pulse Power Rating Junction-to-
Ambient (Note F)
10
1
D=T
on
/T
T
J,PK
=T
A
+P
DM
.Z
θ
JA
.R
θ
JA
In descending order
D=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse
R
θ
JA
=75
°
C/W
0.1
P
DM
0.01
0.001
Single Pulse
0.001
T
on
T
1E-05
0.0001
0.01
0.1
1
10
100
Pulse Width (s)
Figure 11: Normalized Maximum Transient Thermal Impedance (Note F)
Rev.1.0: February 2017
Page 4 of 5
AO4266E
Figure A: Gate Charge Test Circuit & Waveforms
Vgs
Qg
10V
+
VDC
+
Qgs
Qgd
Vds
VDC
–
–
DUT
Vgs
Ig
Charge
Figure B: Resistive Switching Test Circuit & Waveforms
RL
Vds
Vds
90%
10%
+
DUT
Vdd
Vgs
VDC
Rg
–
Vgs
Vgs
t
d(on)
t
r
t
d(off)
t
f
t
on
t
off
Figure C: Unclamped Inductive Switching (UIS) Test Circuit & Waveforms
L
E
AR
= 1/2 L
I
A
2
R
BV
DSS
Vds
Id
Vds
+
Vgs
Vdd
I
AR
Vgs
VDC
Id
Rg
–
DUT
Vgs
Vgs
Figure D: Diode Recovery Test Circuit & Waveforms
Q
rr
= –
Idt
Vds +
Vds –
Ig
DUT
Vgs
Isd
t
rr
L
I
F
Isd
Vgs
dI/dt
I
RM
+
Vdd
VDC
Vdd
–
Vds
Rev.1.0: February 2017
Page 5 of 5
