Alpha—Omega-Semicon-AON7403

Part #Alpha—Omega-Semicon-AON7403
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Alpha—Omega-Semicon-AON7403
AON7403  
30V P-Channel
 
MOSFET  
General Description  
Product Summary  
V

DS  

-30V  
The AON7403 uses advanced trench technology to  
provide excellent R

DS(ON)

, and ultra-low low gate charge  
with a 25V gate rating. This device is suitable for use as a  
load switch or in PWM applications.  
I

D

(at V

GS

=-10V)  
R

DS(ON)

(at V

GS

=-10V)  
R

DS(ON)

(at V

GS

=-5V)  
-29A  
< 18m
W
 
< 36m
W  
100% UIS Tested  
DFN 3x3_EP  
D
Top View  
Bottom View  
Top View  
1
2
3
4
8
7
6
5
D
D
D
S
S
S
G
D
G
Pin 1  
S
Absolute Maximum Ratings
 
T

A

=25°C unless otherwise noted  
Parameter  
Symbol  
Maximum  
Units  
Drain-Source Voltage  
V

DS  

-30  
V
V
Gate-Source Voltage  
V

GS  

±2 5  
-29  
T

C

=25°C  
Continuous Drain  
Current  
Pulsed Drain Current

C  

I

D  

T

C

=100°C  
A
A
-18  
I

DM  

-80  
T

A

=25°C  
T

A

=70°C  
-11  
Continuous Drain  
Current  
Avalanche Current

C  

Repetitive avalanche energy L=0.1mH

C  

I

DSM  

-8.5  
24  
I

AR  

A
E

AR  

29  
mJ  
T

C

=25°C  
Power Dissipation

B  

T

C

=100°C  
25  
P

D  

W
10  
T

A

=25°C  
4.1  
P

DSM  

W
Power Dissipation

A  

2.6  
T

A

=70°C  
Junction and Storage Temperature Range  
T

J

, T

STG  

-55 to 150  
°C  
Thermal Characteristics  
Parameter  
Symbol  
Typ  
22  
Max  
30  
60  
5
Units  
°C/W  
°C/W  
°C/W  
Maximum Junction-to-Ambient

A  

t ≤
 
10s  
R

q
JA  

Maximum Junction-to-Ambient

A D  

Maximum Junction-to-Lead  
Steady-State  
Steady-State  
47  
R

q
JC  

4.2  
Rev.4.0: November. 2013  
Page 1 of 5  

Electrical Characteristics (T

J

=25°C unless otherwise noted)  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max Units  
STATIC PARAMETERS  
I

D

=-250
m
A, V

GS

=0V  
BV

DSS  

Drain-Source Breakdown Voltage  
-30  
V
V

DS

=-30V, V

GS

=0V  
-1  
I

DSS  

Zero Gate Voltage Drain Current  
m
A  
-5  
T

J

=55°C  
V

DS

=0V, V

GS

= ±25V  
V

DS

=V

GS

I

D

=-250
m
A  
V

GS

=-10V, V

DS

=-5V  
V

GS

=-10V, I

D

=-8A  
I

GSS  

Gate-Body leakage current  
Gate Threshold Voltage  
On state drain current  
100  
-3  
nA  
V
V

GS(th)  

I

D(ON)  

-1.7  
-80  
-2.2  
A
14  
20  
18  
25  
36  
m
W  
R

DS(ON)  

Static Drain-Source On-Resistance  
T

J

=125°C  
V

GS

=-5V, I

D

=-5A  
V

DS

=-5V, I

D

=-8A  
I

S

=-1A,V

GS

=0V  
26  
m
W  
S
g

FS  

V

SD  

I

S  

Forward Transconductance  
Diode Forward Voltage  
20  
-0.7  
-1  
V
Maximum Body-Diode Continuous Current  
-22  
A
DYNAMIC PARAMETERS  
C

iss  

C

oss  

C

rss  

R

g  

Input Capacitance  
1130 1400  
pF  
pF  
pF  
W
V

GS

=0V, V

DS

=-15V, f=1MHz  
Output Capacitance  
Reverse Transfer Capacitance  
Gate resistance  
240  
155  
V

GS

=0V, V

DS

=0V, f=1MHz  
5.8  
8
SWITCHING PARAMETERS  
Q

g

(10V) Total
 
Gate Charge  
18  
5.5  
3.3  
8.7  
8.5  
18  
7
24  
nC  
nC  
nC  
ns  
ns  
ns  
ns  
V

GS

=-10V, V

DS

=-15V, I

D

=-8A  
Q

gs  

Q

gd  

t

D(on)  

t

r  

Gate Source Charge  
Gate Drain Charge  
Turn-On DelayTime  
Turn-On Rise Time  
Turn-Off DelayTime  
Turn-Off Fall Time  
V

GS

=-10V, V

DS

=-15V, R

L

=1.8
W
,  
R

GEN

=3
W  
t

D(off)  

t

f  

t

rr  

I

F

=-8A, dI/dt=500A/
m
s  
I

F

=-8A, dI/dt=500A/
m
s  
Body Diode Reverse Recovery Time  
Body Diode Reverse Recovery Charge  
12  
26  
16  
ns  
Q

rr  

nC  
A. The value of R

q
JA

is measured with the device mounted on 1in

2

FR-4 board with 2oz. Copper, in a still air environment with T

A

=25
°
C. The  
Power dissipation P

DSM

is based on R

q
JA

t
≤
10s value and the maximum allowed junction temperature of 150
°
C. The value in any given  
application depends on the user’s specific board design, and the maximum temperature of 150
°
C may be used if the PCB allows it.  
B. The power dissipation P

D

is based on T

J(MAX)

=150
°
C, using junction-to-case thermal resistance, and is more useful in setting the upper  
dissipation limit for cases where additional heatsinking is used.  
C. Repetitive rating, pulse width limited by junction temperature T

J(MAX)

=150
°
C. Ratings are based on low frequency and duty cycles to keep  
initial T

J

=25
°
C.  
D. The R

q
JA

is the sum of the thermal impedence from junction to case R

q
JC

and case to ambient.  
E. The static characteristics in Figures 1 to 6 are obtained using <300
m
s pulses, duty cycle 0.5% max.  
F. These curves are based on the junction-to-case thermal impedence which is measured with the device mounted to a large heatsink, assuming  
a maximum junction temperature of T

J(MAX)

=150
°
C. The SOA curve provides a single pulse rating.  
G. The maximum current rating is package limited.  
H. These tests are performed with the device mounted on 1 in

2

FR-4 board with 2oz. Copper, in a still air environment with T

A

=25
°
C.  
THIS PRODUCT HAS BEEN DESIGNED AND QUALIFIED FOR THE CONSUMER MARKET. APPLICATIONS OR USES AS CRITICAL  
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. AOS DOES NOT ASSUME ANY LIABILITY ARISING  
OUT OF SUCH APPLICATIONS OR USES OF ITS PRODUCTS.
 
AOS RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN,  
FUNCTIONS AND RELIABILITY WITHOUT NOTICE.  
Rev.4.0: November. 2013  
Page 2 of 5  

TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS  
80  
60  
40  
20  
0
80  
60  
40  
20  
0
-10V  
V

DS

=-5V  
-8V  
-6V  
-4.5V  
125
°
C  
25
°
C  
V

GS

=-4V  
1
2
3
4
5
6
0
1
2
3
4
5
-V

GS

(Volts)  
Figure 2: Transfer Characteristics (Note E)  
-V

DS

(Volts)  
Fig 1: On-Region Characteristics (Note E)  
40  
1.6  
1.4  
1.2  
1
V

GS

=-10V  
I

D

=-8A  
35  
30  
25  
20  
15  
10  
V

GS

=-5V  
V

GS

=-10V  
V

GS

=-5V  
I

D

=-5A  
0.8  
0
5
10  
-I

D

(A)  
15  
20  
0
25  
50  
75  
100  
125  
150  
175  
Temperature (°C)  
Figure 3: On-Resistance vs. Drain Current and Gate  
Voltage (Note E)  
Figure 4: On-Resistance vs. Junction Temperature  
(Note E)  
50  
1.0E+01  
I

D

=-8A  
40  
30  
20  
10  
1.0E+00  
125
°  
1.0E-01  
1.0E-02  
1.0E-03  
125
°  
25
°  
25
°  
0.0  
0.2  
0.4  
0.6  
0.8  
1.0  
1.2  
2
4
6
8
10  
-V

SD

(Volts)  
-V

GS

(Volts)  
Figure 6: Body-Diode Characteristics (Note E)  
Figure 5: On-Resistance vs. Gate-Source Voltage  
(Note E)  
Rev.4.0: November. 2013  
Page 3 of 5  

TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS  
1600  
10  
V

DS

=-15V  
I

D

=-8A  
1400  
1200  
1000  
800  
600  
400  
200  
0
C

iss  

8
6
4
C

oss  

2
C

rss  

0
0
5
10  
15  
20  
0
5
10  
15  
20  
25  
30  
Q

g

(nC)  
-V

DS

(Volts)  
Figure 7: Gate-Charge Characteristics  
Figure 8: Capacitance Characteristics  
1000.0  
10000  
1000  
100  
10  
T

A

=25
°  
100.0  
10.0  
1.0  
10
m
s  
R

DS(ON)  

100
m
s  
1ms  
10ms  
DC  
T

J(Max)

=150
°
C  
T

A

=25
°
C  
100ms  
10s  
0.1  
0.0  
0.01  
1
0.1  
1
10  
100  
0.00001  
0.001  
0.1  
10  
1000  
-V

DS

(Volts)  
Pulse Width (s)  
Figure 10: Single Pulse Power Rating Junction-to-  
Ambient (Note F)  
Figure 9: Maximum Forward Biased Safe  
Operating Area (Note F)  
10  
D=T

on

/T  
In descending order  
D=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse  
T

J,PK

=T

A

+P

DM

.Z

q
JA

.R

q
JA  

R

q
JA

=60
°
C/W  
1
0.1  
P

D  

0.01  
0.001  
T

on  

T
Single Pulse  
0.00001  
0.0001  
0.001  
0.01  
0.1  
Pulse Width (s)  
1
10  
100  
1000  
Figure 11: Normalized Maximum Transient Thermal Impedance (Note F)  
Rev.4.0: November. 2013  
Page 4 of 5  

Gate Charge Test Circuit & Waveform  
Vgs  
Qg  
–
-10V  
–
VDC  
Qgs  
Qgd  
+
Vds  
VDC  
+
DUT  
Vgs  
Ig  
Charge  
Resistive Switching Test Circuit & Waveforms  
RL  
Vds  
t

off  

t

on  

t
t

d(off)  

t

d(on)  

t
r
f
Vgs  
–
90%  
10%  
DUT  
Vdd  
Vgs  
VDC  
+
Rg  
Vgs  
Vds  
Unclamped Inductive Switching (UIS) Test Circuit & Waveforms  
E

AR

= 1/2 LI

A

2

R  

L
Vds  
Id  
Vgs  
Vds  
–
BV

DSS  

Vgs  
Vdd  
VDC  
+
Id  
Rg  
I

AR  

DUT  
Vgs  
Vgs  
Diode Recovery Test Circuit & Waveforms  
Q

rr

= –
 
Idt  
Vds +  
Vds –  
Ig  
DUT  
Vgs  
t

rr  

L
-Isd  
-I

F  

Isd  
Vgs  
dI/dt  
-I

RM  

+
Vdd  
VDC  
Vdd  
–
-Vds  
Rev.4.0: November. 2013  
Page 5 of 5