AMICCOM-Elec-A71X06AQFI-Q

A7106  

2.4G FSK/GFSK Transceiver  

Document Title  

A7106 Data Sheet, 2.4GHz FSK/GFSK Transceiver with 500Kbps data rate  

Revision History  

Rev. No.

 

History  

Issue Date  

Aug., 2009  

Feb., 2010  

Jun., 2010  

May, 2010  

Jul., 2011  

Remark  

0.0  

0.1  

0.2  

0.3  

0.4  

Initial issue.  

Objective  

Add chapter 11, add 15.5 RSSI calibration  

Update

BD info  

Preliminary  

Prelimin

ary  

Prelimin

ary  

Prelimin

ary  

Add WO

R function  

Add Sh

enzhen office address and modify tape reel information.  

1.0  

1.1  

1.2  

Update

WOR procedure in page 81. Full production.  

Update

Xtal tolerance in Ch8.  

Sep., 2011  

Oct., 2011  

Full pro

duction.  

Full pro

duction.  

Full pro

duction.  

Modify

order info A71C06BH to A71C06AH and configurations of

 

Nov., 2011  

table 14

.5.  

Important Notice

:  

AMICCOM reserves the right to make changes to its products or to discontinue any integrated circuit product or service  

without notice. AMICCOM integrated circuit products are not designed, intended, authorized, or warranted to be suitable for  

use in life-support applications, devices or systems or other critical applications. Use of AMICCOM products in such  

applications is understood to be fully at the risk of the customer.  

NOV. 2011, Version 1.2  

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AMICCOM Electronics Corporation  

A7106  

2.4G FSK/GFSK Transceiver  

Table of Contents  

9.2.43 Rx DEM test Register II (Address: 2Ah) ……………………………………………………………………………………….28  

NOV. 2011, Version 1.2  

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AMICCOM Electronics Corporation  

A7106  

2.4G FSK/GFSK Transceiver  

15.2 IF Filter Bank Calibration……………………………………………………………………………………………………………………63  

NOV. 2011, Version 1.2  

3

AMICCOM Electronics Corporation  

A7106  

2.4G FSK/GFSK Transceiver  

NOV. 2011, Version 1.2  

4

AMICCOM Electronics Corporation  

A7106  

2.4G FSK/GFSK Transceiver  

1. General Description  

A7106 is a high performance and low cost 2.4GHz ISM band wireless transceiver. This device integrates both high sensitivity  

receiver (- 95dBm @ 500Kbps) and high efficiency power amplifier (up to 1dBm). In low data rate application, A7106 has  

special strength for long LOS (line-of-sight) distance because of its ultra high sensitivity (-107 dBm @ 2Kbps, – 104 dBm @  

25Kbps) with no requirement of external LNA or PA. Based on Data Rate Register (0x0E), user can configure on-air data  

rates from 2Kbps to 500Kbps.  

A7106 supports fast settling time (130 us) for frequency hopping system. For packet handling, A7106 has built-in separated  

64-bytes TX/RX FIFO (could be extended to 256 bytes) for data buffering and burst transmission, CRC for error detection,  

FEC for 1-bit data correction per code word, RSSI for clear channel assessment, data whitening for data encryption /  

decryption, the internal

RC oscillator for WOR (Wake-On-RX) to support periodically wake up from sle

ep and listen  

(auto-enter RX mode) for

incoming packets without MCU interaction. Those functions are very easy to use while

developing a  

wireless system. All featu

res are integrated in a small QFN 4X4 20 pins package.  

A7106’s control registers

can be easily accessed via 3-wire or 4-wire SPI bus. For power saving, A7106 support

s sleep mode,  

idle mode, standby mode

. For easy-to-use, A7106 has an unique SPI command set called

Strobe command

th

at are used to  

control internal state ma

chine. Based on Strobe commands via SPI bus, MCU can control everything from pow

er saving, TX  

delivery, RX receiving, c

hannel monitoring, frequency hopping to auto calibrations. In addition, A7106 support

s two general  

purpose I/O pins, GIO1

and GIO2, to inform MCU its status so that MCU could use either polling or interrupt

scheme to do  

radio control. Hence, it is

very easy to monitor radio transmission between MCU and A7106 because of its digit

al interface.  

2. Typical Applica

tions  

n

2400 ~ 2483.5 MHz ISM system  

n

Wireless keyboard an

d mice  

n

Wireless metering and building automatio

n  

n

Remote control  

n

Wireless toys and game controllers  

n

Helicopter and airplan

e radio controller  

3. Feature  

n

n

n

n

n

n

n

n

n

Small size

(QFN4 X4, 20 pins).  

Frequency

band: 2400 ~ 2483.5MHz.  

FSK or GF

SK modulation  

Low curren

t consumption:

 

RX 16mA, TX 20mA (at 0dBm output power).  

Low sleep

current (1.5 uA).  

On chip reg

ulator, support input voltage 2.0 ~ 3.6 V.  

Programma

ble data rate from 2Kbps to 500Kbps.  

Programma

ble TX power level from – 20 dBm to 1 dBm.  

Ultra High s

ensitivity:  

u

u

u

u

-95dB

m at 500Kbps on-air data rate.  

-97dB

m at 250Kbps on-air data rate  

-104d

Bm at 25Kbps on-air data rate  

-107d

Bm at 2Kbps on-air data rate  

n

n

n

n

n

n

Fast settlin

g time (130 us) synthesizer for frequency hopping system.  

Built-in Battery Detector.  

Support low cost crystal (6 / 8 /12 / 16 / 20 / 24MHz).  

Support crystal sharing, (1 / 2 / 4 / 8MHz) to MCU.  

Auto Frequency Compensation  

Easy to use.  

u

u

u

u

u

u

u

Support 3-wire or 4-wire SPI.  

Unique Strobe command via SPI.  

ONE register setting for new channel frequency.  

8-bits Digital RSSI for clear channel indication.  

Fast exchange mode during TRX role switching.  

Auto RSSI measurement.  

Auto Calibrations.  

NOV. 2011, Version 1.2  

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AMICCOM Electronics Corporation  

A7106  

2.4G FSK/GFSK Transceiver  

u

u

u

u

u

u

u

u

u

Auto IF function.  

Auto CRC Check.  

Auto FEC by (7, 4) Hamming code (1 bit error correction / code word).  

Data Whitening for encryption and decryption.  

Separated 64 bytes RX and TX FIFO.  

Easy FIFO / Segment FIFO / FIFO Extension (up to 256 bytes).  

Support direct mode with recovery clock output to MCU.  

Support direct mode with frame sync signal to MCU.  

Support WOR (Wake-On-RX) to periodically wake up from sleep to RX mode.  

4. Pin Configura

tions  

RSSI  

15  

14  

13  

12  

1

2

GND  

SDIO  

DVDD  

SCK  

BPBG  

RFI  

3

4

5

RFO  

VDA2  

11  

SCS  

Fig 4-1. A7106 QFN 4×4 Package Top View  

NOV. 2011, Version 1.2  

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AMICCOM Electronics Corporation  

A7106  

2.4G FSK/GFSK Transceiver  

5. Pin Description (I: input; O: output, I/O: input or output)  

Pin No.  

1

Symbol  

RSSI  

BPBG  

RFI  

I/O  

O

O

I

Function Description  

Connected to a bypass capacitor for RSSI reading.  

Connected to a bypass capacitor for internal Regulator bias point  

Low noise amplifier input.  

2

3

4

RFO  

VDA2  

VT  

O

Power amplifier output.  

5

I/O Voltage

 

supply

(from VDA1, pin 20)

for RX & TX analog part.  

6

I

G

I

VCO frequency control input, internal connected to PLL charge pump.  

Ground  

7

GND  

XI  

8

Crystal oscillator input node  

9

XO  

O

I

Crystal oscillator output node  

10  

11  

12  

13  

14  

15  

16  

17  

18  

19  

20  

VDA3  

SCS  

SCK  

DVDD  

SDIO  

GND  

GIO1  

GIO2  

CKO  

REGI  

VDA1  

Voltage supply

(from VDA1, pin 20)

for PLL part  

3 wire SPI chip select.  

I

I

3 wire SPI clock input pin.  

I

Connected to a bypass capacitor to supply voltage for digital part.  

I/O 3

 

wire SPI read/write data pin.  

Ground  

G

I/O Multi-function

 

GIO1 / 4-wire SPI data output.  

I/O Multi-function

 

GIO2 / 4-wire SPI data output.  

Multi-function clock output.  

O

I

Internal Regulator input

(External Power Input)  

Internal Regulator output to supply

VDA2 (pin 5), VDA2 (pin 10) and

RFO (pin 4).  

I/O  

Ground.  

Back side

plate  

G

Back side plate shall be well-solder to ground; otherwise, it will impact

RF performance.  

NOV. 2011, Version 1.2  

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AMICCOM Electronics Corporation  

A7106  

2.4G FSK/GFSK Transceiver  

6. Chip Block Diagram  

Fig 6-1. A7106 Block Diagram  

NOV. 2011, Version 1.2  

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AMICCOM Electronics Corporation  

A7106  

2.4G FSK/GFSK Transceiver  

7. Absolute Maximum Ratings  

Parameter  

Supply voltage range (VDD)  

Digital IO pins range  

With respect to  

GND  

Rating  

-0.3 ~ 3.6  

-0.3 ~ VDD+0.3  

-0.3 ~ 2.1  

5

Unit  

V

GND  

V

Voltage on the analog pins range  

Input RF level  

GND  

V

dBm  

°

C  

V

Storage Temperature range  

ESD Rating  

-55 ~ 125  

± 2K  

HBM  

MM  

± 100  

V

*Stresses above those

listed under “Absolute Maximum Rating” may cause permanent damage to the dev

ice. These are  

stress ratings only; func

tional operation of the device at these or any other conditions above those indicated in

the operational  

sections of this specific

ation is not implied. Exposure to absolute-maximum-rated conditions for extended peri

ods may affect  

device reliability.  

*Device is ESD sensitiv

e. Use appropriate ESD precautions. HBM (Human Body Mode) is tested under MIL-S

TD-883F  

Method 3015.7. MM (M

achine Mode) is tested under JEDEC EIA/JESD22-A115-A.  

*Device is Moisture Sen

sitivity Level III (MSL 3).  

NOV. 2011, Version 1.2  

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AMICCOM Electronics Corporation  

A7106  

2.4G FSK/GFSK Transceiver  

8. Electrical Specification  

(Ta=25

℃

, VDD=3.0V, data rate= 500Kbps, IF bandwidth = 500KHz, F

XTAL

=16MHz, with Match Networking and low pass  

filter, On Chip Regulator = 2.1V, unless otherwise noted.)  

Parameter  

Description  

Min.  

Type  

Max.  

Unit  

General  

Operating Temperature  

Supply Voltage (VDD)  

Current Consumption  

-40  

2.0  

85  

°

C  

V

with internal regulator  

3.6  

1.5

*

1  

0.3

*

1  

1.9  

Sleep mode (RC OSC off)  

Idle Mode (Regulator on)  

m

A  

mA  

mA  

Standby Mode  

(XOSC on,clock generator on)  

PLL mode  

9

mA  

mA  

mA  

mA  

mA  

mA  

mA  

RX Mode  

16  

TX Mode (@0dBm output)  

TX Mode (@-3dBm output)  

TX Mode (@-6dBm output)  

TX Mode (@-11dBm output)  

TX Mode (@-20dBm output)  

20  

16  

14.5  

13.9  

12.5  

PLL block  

Crystal start up time

*

2  

Crystal frequency  

Crystal tolerance  

0.6  

8, 12,

16

, 20, 24  

±20  

ms  

MHz  

ppm  

ppm  

ohm  

MHz  

dBc  

without AFC  

with AFC  

±30  

Crystal ESR  

80  

VCO Operation Freque

ncy  

PLL phase noise  

2400  

2483.5  

Offset 10k  

Offset 100K  

Offset 1M  

80  

85  

90  

PLL settling time

*

3  

Transmitter  

70  

@Loop BW = 500Khz  

m

S  

Output power range  

Out Band Spurious Em

ission

*

4  

-20  

0

dBm  

dBm  

dBm  

dBm  

dBm  

30MHz~1GHz  

1GHz~12.75GHz  

-36  

-30  

-47  

-47  

1.8GHz~ 1.9GHz  

5.15GHz~ 5.3GHz  

Data rate > 50Kbps  

Date rate <=50Kbps  

Frequency deviation

*

5  

Data rate  

TX ready time

*

6  

(PLL to WPLL + WPLL to TX)  

186K  

124K  

Hz  

Hz  

2K  

500K  

Bps  

m

S  

@Loop BW = 500 KHz,  

LO fixed  

10+60  

70+60  

@Loop BW = 500 KHz,  

Hopping  

m

S  

Receiver  

dBm  

dBm  

Receiver sensitivity  

@ BER = 0.1%  

Data rate 500K (F

IF

= 500KHz)  

Data rate 250K (F

IF

= 500KHz)  

-95  

-97  

NOV. 2011, Version 1.2  

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AMICCOM Electronics Corporation  

A7106  

2.4G FSK/GFSK Transceiver  

dBm  

dBm  

KHz  

KHz  

dB  

Data rate 25K (F

IF

= 500KHz)  

Data rate 2K (F

IF

= 500KHz)  

-104  

-107  

IF frequency bandwidth  

IF center frequency  

Interference

*

7  

250/500  

250/500  

Co-Channel (C/I

0

)  

11  

– 20  

– 30  

– 40  

– 12  

dB  

±

1MHz Adjacent Channel  

±

2MHz Adjacent Channel  

dB  

dB  

> ±

5MHz Adjacent Channel  

Image (C/I

IM

)  

dB  

Maximum Operating In

put Power  

Spurious Emission

*

4  

@RF input (BER=0.1%)  

30MHz~1GHz  

0

dBm  

dBm  

-57  

-47  

-50  

1GHz~12.75GHz  

@RF input  

RSSI Range  

RX Ready Time

*

8  

(PLL to WPLL + WPLL

to RX)  

-105  

dBm  

m

s  

Data rate < = 125 Kbps  

10+40  

10+100  

10+60  

70+40  

70+100  

70+60  

Data rate = 250 Kbps  

Data rate = 500 Kbps  

Data rate < = 125 Kbps  

LO fixed  

m

s  

m

s  

m

s  

Hopping

Data rate = 250 Kbps  

Data rate = 500 Kbps  

above 1GHz  

m

s  

m

s  

RX Spurious Emission  

-47  

2.3  

dBm  

Regulator  

Regulator settling time

*

9  

Band-gap reference vo

ltage  

Regulator output voltag

e  

Line regulation  

Pin 2 connected to 1.5 nF  

Load current 30mA  

500  

m

s  

V

1.23  

2.1  

40  

1.8  

35  

V

dBc  

Digital IO DC charac

teristics  

High Level Input Voltag

e (V

IH

)  

Low Level Input Voltag

e (V

IL

)  

0.8*VDD  

VDD  

0.2*VDD  

VDD  

V

V

V

V

0

VDD-0.4  

0

High Level Output Volta

ge (V

OH  

)

@I

OH

= -0.5mA  

@I

OL

= 0.5mA  

Low Level Output Volta

ge (V

OL

)  

0.4  

Note 1: When digital I/O

pins are configured as input, those pins shall NOT be floating but pull either high or lo

w (SCS shall  

be pulled high o

nly); otherwise, leakage current will be induced.  

Note 2: Refer to Delay

Register II (17h) to set up crystal settling delay.  

Note 3: Refer to Delay

Register I (17h) to set up PDL (PLL settling delay).  

Note 4: With external R

F filter that provides minimum 17dB of attenuation in the band: 30MHz ~ 2GHz and 3G

Hz ~12.75GHz.  

Note 5: Refer to TX Re

gister II (15h) to set up FD [4:0].  

Note 6: Refer to Delay Register I (17h) to set up PDL and TDL delay.  

Note 7: The power level of wanted signal is set at sensitivity level +3dB. The modulation data for wanted signal and interferer  

are PN9 and PN15, respectively. Channel spacing is 500KHz.  

Note 8: For 250K/500Kbps, set DCM[1:0]= [10b] by ID, (29h). For <= 125Kbps, set DCM[1:0]= [01b] by Preamble, (29h).  

Note 9: When VDD < 2.1V and temperature < -30 degree C, the regulator settling time will arise up to

20ms

.  

NOV. 2011, Version 1.2  

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AMICCOM Electronics Corporation  

A7106  

2.4G FSK/GFSK Transceiver  

9. Control Register  

A7106 contains 52 x 8-bit control registers. MCU can access those control registers via 3-wire (SCS, SCK, SDIO) or 4-wire  

(SCS, SCK, SDIO, GIO1/GIO2) SPI interface (support max. SPI data rate up to 10 Mbps). User can refer to chapter 10 for  

details of SPI timing. A7106 is simply controlled by registers and outputs its status to MCU by GIO1 and GIO2 pins.  

9.1 Control register table  

Address /  

Name  

R/W  

Bit 7  

Bit 6  

Bit 5  

Bit 4  

Bit 3  

Bit 2  

Bit 1  

Bit 0  

00h  

Mode  

01h  

Mode control  

02h  

Calc  

03h  

FIFO I  

04h  

FIFO II  

05h  

FIFO Data  

06h  

ID Data  

07h  

W

R

W

R

RESETN  

—  

DDPC  

DDPC  

RESETN  

FECF  

ARSSI  

ARSSI  

RESETN  

CRCF  

AIF  

RESETN  

CER  

DFCD  

CD  

RESETN  

XER  

WORE  

WORE  

RESETN  

PLLER  

FMT  

RESETN  

TRSR  

FMS  

RESETN  

TRER  

ADCM  

ADCM  

AIF  

FMT  

FMS  

R/W  

W

—  

—  

—  

—  

RSSC  

FEP3  

PSA3  

FIFO3  

ID3  

VCC  

FEP2  

PSA2  

FIFO2  

ID2  

VBC  

FEP1  

PSA1  

FIFO1  

ID1  

FBC  

FEP0  

PSA0  

FIFO0  

ID0  

FEP7  

FPM1  

FIFO7  

ID7  

FEP6  

FPM0  

FIFO6  

ID6  

FEP5  

PSA5  

FIFO5  

ID5  

FEP4  

PSA4  

FIFO4  

ID4  

W

R/W  

R/W  

W

R

WOR_SL7 WOR_SL6 WOR_SL5 WOR_SL4 WOR_SL3 WOR_SL2 WOR_SL1

WOR_SL0  

CALR RCOC6

 

RCOC5 RCOC4 RCOC3 RCOC2 RCOC1

RCOC0  

RC OSC I  

08h  

RC OSC II  

09h  

W

W

WOR_SL9 WOR_SL8 WOR_AC5

 

WOR_AC4 WOR_AC3 WOR_AC2 WOR_AC1

WOR_AC0  

BBCKS1  

ECKOE  

—  

BBCKS0  

CKOS3  

—  

RCOT1  

CKOS2  

GIO1S3  

GIO2S3  

GRC1  

RCOT0  

CKOS1  

GIO1S2  

GIO2S2  

GRC0  

CALW  

CKOS0  

GIO1S1  

GIO2S1  

CSC1  

RCOSC_E  

CKOI  

TSEL  

CKOE  

GIO1I  

GIO2I  

CGS  

TWOR_E  

SCKI  

RC OSC III  

0Ah  

CKO Pin  

0Bh  

W

W

GIO1S0  

GIO2S0  

CSC0  

GIO1OE  

GIO2OE  

XS  

GPIO1 Pin I  

0Ch  

GPIO2 Pin II  

0Dh  

Clock  

0Eh  

Data rate  

0Fh  

PLL I  

10h  

PLL II  

11h  

PLL III  

12h  

PLL IV  

13h  

PLL V  

14h  

TX I  

15h  

TX II  

16h  

Delay I  

17h  

Delay II  

W

—  

—  

R/W  

R/W  

R/W  

R/W  

R/W  

GRC3  

SDR7  

CHN7  

DBL  

GRC2  

SDR6  

CHN6  

RRC1  

IP6  

SDR5  

SDR4  

SDR3  

SDR2  

SDR1  

CHN1  

CHR0  

IP1  

SDR0  

CHN0  

IP8  

CHN5  

CHN4  

CHN3  

CHN2  

RRC0  

CHR3  

CHR2  

CHR1  

IP7  

IP5  

IP4  

IP3  

IP2  

IP0  

W

R

W

R

FP15  

RAC15  

FP7  

FP14  

RAC14  

FP6  

FP13  

RAC13  

FP5  

FP12  

RAC12  

FP4  

FP11  

RAC11  

FP3  

FP10  

RAC10  

FP2  

FP9  

RAC9  

FP1  

FP8  

RAC8  

FP0  

RAC7  

RAC6  

RAC5  

RAC4  

RAC3  

RAC2  

RAC1  

RAC0  

W

W

W

W

TXSM1  

—  

TXSM0  

PDV1  

TXDI  

PDV0  

TME  

FD4  

FS  

FD3  

FDP2  

FD2  

FDP1  

FD1  

FDP0  

FD0  

DPR2  

WSEL2  

DPR1  

DPR0  

WSEL0  

TDL1  

TDL0  

PDL2  

PDL1  

PDL0  

WSEL1  

AGC_D1  

AGC_D0  

RS_DLY2 RS_DLY1  

RS_DLY0  

NOV. 2011, Version 1.2  

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AMICCOM Electronics Corporation  

A7106  

2.4G FSK/GFSK Transceiver  

18h  

RX  

19h  

W

QDLS  

MVGS  

RXSM1  

AGLNE  

RXSM0  

IGC  

AFC  

RXDI  

DMG  

B

W

S  

ULS  

R/W  

MGC1  

MGC0  

LGC2  

LGC1  

LGC0  

RX Gain I  

W

R

RH7  

RHR7  

RL7  

RH6  

RHR6  

RL6  

RH5  

RHR5  

RL5  

RH4  

RHR4  

RL4  

RH3  

RHR3  

RL3  

RH2  

RHR2  

RL2  

RH1  

RHR1  

RL1  

RH0  

RHR0  

RL0  

1Ah  

RX Gain II  

W

R

1Bh  

RX Gain III  

RLR7  

RLR6  

RLR5  

RLR4  

RLR3  

RLR2  

RLR1  

RLR0  

1Ch  

RX Gain IV  

1Dh  

W

ENGC  

CRCD  

MVSEL1  

MVSEL0  

MHC  

LHC1  

LHC0  

VGCE  

W

R

RTH7  

ADC7  

RTH6  

ADC6  

RTH5  

ADC5  

RTH4  

ADC4  

RTH3  

ADC3  

RTH2  

ADC2  

RTH1  

ADC1  

RTH0  

ADC0  

RSSI Threshold  

1Eh  

ADC  

1Fh  

Code I  

20h  

Code II  

21h  

Code III  

W

W

W

W

RSM1  

RSM0  

MCS  

ERSS  

WHTS  

DCL1  

WS5  

FSARS  

FECS  

DCL0  

WS4  

—  

XADS  

IDL  

RSS  

PML1  

PMD1  

WS1  

CDM  

PML0  

PMD0  

WS0  

—  

—  

—  

CRCS  

ETH1  

WS3  

DCL2  

WS6  

ETH0  

WS2  

W

R

—  

—  

—  

—  

—  

—  

MFBS  

FBCF  

MFB3  

FB3  

MFB2  

FB2  

MFB1  

FB1  

MFB0  

FB0  

22h  

IF Calibration I  

23h  

R

—  

—  

—  

FCD4  

FCD3  

FCD2  

FCD1  

FCD0  

IF Calibration II  

24h  

W

R

—  

—  

—  

—  

—  

—  

—  

—  

VCCS  

—  

MVCS  

FVCC  

—  

VCOC3  

VCB3  

VCOC2  

VCB2  

MVB2  

VB2  

VCOC1  

VCB1  

MVB1  

VB1  

VCOC0  

VCB0  

MVB0  

VB0  

VCO current  

Calibration  

25h  

VCO Single band  

Calibration I  

26h  

W

R

—  

MVBS  

VBCF  

DVT1  

DVT0  

W

—  

—  

VTH2  

VTH1  

VTH0  

VTL2  

VTL1  

VTL0  

VCO Single band  

Calibration II  

W

R

RGS  

RGS  

RGV1  

RGV1  

RGV0  

RGV0  

QDS  

BDF  

BVT2  

BVT2  

BVT1  

BVT1  

BVT0  

BVT0  

BDS  

BDS  

27h  

Battery detect  

28h  

TX test  

29h  

W

W

—  

DMT  

DCV7  

ROSCS  

RSIS  

PRS  

—  

TXCS  

DCM0  

DCV5  

RGC1  

PKT0  

PRIC1  

—  

PAC1  

MLP1  

DCV4  

RGC0  

PKS  

PAC0  

MLP0  

DCV3  

STS  

TBG2  

SLF2  

DCV2  

LVR  

TBG1  

SLF1  

DCV1  

CPC1  

XCP1  

SDPW  

RLB  

TBG0  

SLF0  

DCV0  

CPC0  

XCP0  

NSDO  

VCBS  

RFT0  

LIMC  

RSC0  

FT0  

DCM1  

DCV6  

CELS  

PKT1  

PMPE  

—  

Rx DEM test I  

2Ah  

Rx DEM test II  

2Bh  

CPC  

2Ch  

Crystal test  

W

W

W

DBD  

XCC  

2Dh  

PLL test  

2Eh  

W

PRIC0  

TLB  

PRRC1  

TLB  

PRRC0  

RLB  

W

MQDL  

—  

VCO test I  

2Fh  

VCO test II  

30h  

IFAT  

31h  

Rscale  

32h  

W

—  

—  

—  

RFT3  

IGFQ1  

RSC3  

FT3  

RFT2  

IGFQ0  

RSC2  

FT2  

RFT1  

IFBC  

RSC1  

FT1  

W

IGFI2  

RSC7  

FT7  

IGFI1  

RSC6  

FT6  

IGFI0  

RSC5  

FT5  

IGFQ2  

RSC4  

FT4  

R/W  

W

Filter test  

NOV. 2011, Version 1.2  

13  

AMICCOM Electronics Corporation  

A7106  

2.4G FSK/GFSK Transceiver  

33h  

TMV  

W

—  

TRT2  

TRT1  

TRT0  

ASMV2  

ASMV1  

ASMV0  

ASMV  

Legend: — = unimplemented  

9.2 Control register description  

9.2.1 Mode Register

 

(Address: 00h)  

Name  

R/W  

Bit 7  

Bit 6  

Bit 5  

Bit 4  

Bit 3  

Bit 2  

Bit 1  

Bit 0  

R

—  

RESETN  

—  

FECF  

CRCF  

CER  

XER  

PLLER  

TRSR  

TRER  

Mode  

Reset  

RESETN RESETN RESETN RESETN RESETN RESETN

RESETN  

W

—  

—  

—  

—  

—  

—  

—  

RESETN: Write to this

register by 0x00 to issue reset command, then it is auto clear  

FECF: FEC flag.  

[0]:

FEC pass.

[1]:

FEC

error. (FECF is read only, it is updated internally while receiving every packet.)  

CRCF: CRC flag.  

[0]:

CRC pass.

[1]:

CR

C error. (CRCF is read only, it is updated internally while receiving every packet.)  

CER: RF chip enable

status.  

[0]:

RF chip is disabled

.

[1]:

RF chip is enabled.  

XER: Internal crystal o

scillator enabled status.  

[0]:

Crystal oscillator is

disabled.

[1]:

Crystal oscillator is enabled.  

PLLE: PLL enabled st

atus.  

[0]:

PLL is disabled.

[1]

:

PLL is enabled.  

TRER: TRX state enab

led status.  

[0]:

TRX is disabled.

[1

]:

TRX is enabled.  

TRSR: TRX Status Re

gister.  

[0]:

RX state.

[1]:

TX st

ate.  

Serviceable if TRER=1

(TRX is enable).  

9.2.2 Mode Control

Register (Address:

 

01h)  

Name  

R

/W  

Bit 7  

Bit 6  

Bit 5  

Bit 4  

Bit 3  

Bit 2  

Bit 1  

Bit 0  

R

W

DDPC  

DDPC  

0

ARSSI  

ARSSI  

0

AIF  

AIF  

0

DFCD  

CD  

WORE  

WORE  

0

FMT  

FMT  

0

FMS  

FMS  

0

ADCM  

ADCM  

0

Mode Control I  

Reset  

0

DDPC (Direct mode da

ta pin control): In Direct mode, If DDPC=1, MCU delivers / receives raw data of p

acket via SDIO  

pin instead of GIO1 or

GIO2 pin.  

[0]:

Disable.

[1]:

Enabl

e.  

ARSSI: Auto RSSI measurement while entering RX mode.  

[0]:

Disable.

[1]:

Enable.  

AIF (Auto IF Offset): RF LO frequency will auto offset one IF frequency while entering RX mode.  

[0]:

Disable.

[1]:

Enable.  

CD / DFCD: DFCD (Data Filter by CD): The received packet will be filtered out if CD is inactive.  

[0]:

Disable.

[1]:

Enable.  

CD (Read only): Carrier detector signal.  

[0]:

Input power below threshold.

[1]:

Input power above threshold.  

WORE: Enable WOR (Wake-On Radio) in RX mode.  

[0]:

Disable.

[1]:

Enable. (Auto-clear after wake-up.)  

NOV. 2011, Version 1.2  

14  

AMICCOM Electronics Corporation  

A7106  

2.4G FSK/GFSK Transceiver  

FMT: Reserved for internal usage only. Shall be set to [0].  

FMS: Direct/FIFO mode select.  

[0]:

Direct mode.

[1]:

FIFO mode.  

ADCM: ADC measurement enable (Auto clear when done).  

[0]:

Disable measurement or measurement finished.

[1]:

Enable measurement.  

ADCM  

[0]  

[1]  

A7106 @ Standby mode  

Disable ADC  

No function  

A7106 @ RX mode  

Disable ADC  

Measure RSSI, carrier detect  

Refer to chapter 17 for

details.  

9.2.3 Calibration Co

ntrol Register

 

(Address: 02h)  

Name  

R

/W  

Bit 7  

Bit 6  

Bit 5  

Bit 4  

Bit 3  

Bit 2  

Bit 1  

Bit 0  

Mode Control II  

Reset  

R

/W  

—  

—  

—  

—  

—  

—  

—  

—  

RSSC  

0

VCC  

0

VBC  

0

FBC  

0

VCC: VCO Current ca

libration enable (Auto clear when done).  

[0]:

Disable.

[1]:

Enabl

e.  

VBC: VCO Bank calib

ration enable (Auto clear when done).  

[0]:

Disable.

[1]:

Enabl

e.  

FBC: IF Filter Bank ca

libration enable (Auto clear when done).  

[0]:

Disable.

[1]:

Enabl

e.  

RSSC: RSSI calibratio

n enable (Auto clear when done).  

[0]:

Disable.

[1]:

Enabl

e.  

9.2.4 FIFO Register

I (Address:

 

03h)  

Name  

R/W  

Bit 7  

Bit 6  

Bit 5  

Bit 4  

Bit 3  

Bit 2  

Bit 1  

Bit 0  

FIFO I  

Reset  

W

FEP7  

0

FEP6  

0

FEP5  

1

FEP4  

1

FEP3  

1

FEP2  

1

FEP1  

1

FEP0  

1

FEP [7:0]: FIFO End P

ointer for TX FIFO and Rx FIFO.  

Refer to chapter 16 for

details.  

9.2.5 FIFO Register

II (Address:

 

04h)  

Name  

R/W  

Bit 7  

Bit 6  

Bit 5  

Bit 4  

Bit 3  

Bit 2  

Bit 1  

Bit 0  

FIFO II  

Reset  

W

FPM1  

0

FPM0  

1

PSA5  

0

PSA4  

0

PSA3  

0

PSA2  

0

PSA1  

0

PSA0  

0

FPM [1:0]: FIFO Pointer Margin  

PSA [5:0]: Used for Segment FIFO.  

Refer to chapter 16 for details.  

9.2.6 FIFO DATA Register

 

(Address: 05h)  

Name  

R/W  

Bit 7  

Bit 6  

Bit 5  

Bit 4  

Bit 3  

Bit 2  

Bit 1  

Bit 0  

FIFO DATA  

Reset  

R/W  

FIFO7  

0

FIFO6  

0

FIFO5  

0

FIFO4  

0

FIFO3  

0

FIFO2  

0

FIFO1  

0

FIFO0  

0

FIFO [7:0]: FIFO data. TX FIFO (Write only) and RX FIFO (Read only).  

TX FIFO and RX FIFO share the same address (05h).  

Refer to chapter 16 for details.  

NOV. 2011, Version 1.2  

15  

AMICCOM Electronics Corporation  

A7106  

2.4G FSK/GFSK Transceiver  

9.2.7 ID DATA Register (Address: 06h)  

Name  

R/W  

Bit 7  

Bit 6  

Bit 5  

Bit 4  

Bit 3  

Bit 2  

Bit 1  

Bit 0  

ID DATA  

Reset  

R/W  

ID7  

0

ID6  

0

ID5  

0

ID4  

0

ID3  

0

ID2  

0

ID1  

0

ID0  

0

ID [7:0]: ID data.  

When this address is accessed, ID Data is input or output sequential (ID Byte 0,1, 2 and 3) corresponding to Write or Read.  

Recommend to set ID Byte 0 = 5xh or Axh.  

Refer to section 10.6 for details.  

9.2.8 RC OSC Regis

ter I (Address: 07h)  

Name  

R

/W  

Bit 7  

Bit 6  

Bit 5  

Bit 4  

Bit 3  

Bit 2  

Bit 1  

Bit 0  

RCOC5  

RCOC4  

RCOC3  

RCOC2  

RCOC1  

RCOC0  

RCOC6  

R

W

CALR  

RC OSC I  

Reset  

WOR_SL7 WOR_SL6 WOR_SL5 WOR_SL4 WOR_SL3 WOR_SL2 WOR_SL1

WOR_SL0  

0

0

0

0

0

0

0

0

Refer to chapter 20 for

details.  

RCOC [6:0]:

 

RC-osc

illator calibration value reading.  

CALR: RC-oscillator c

alibration status (Need 3 ms for calibration).  

[0]:

calibration finished.

[1]:

not yet.  

Parameter  

Min  

3.8K  

Typ  

Max  

4.2K  

± 5%  

Unit  

Hz  

Note  

Calibrated Freq.  

Freq. accuracy afte

r  

calibration  

Temperature coeffic

ient  

+0.46  

3

% /

℃  

Frequency drift when temperat

ure  

changes after calibration.  

Initial calibration tim

e  

Wake-up period  

Sleep period  

ms  

ms  

ms  

0.25  

8

16  

8192  

Programmable, see WOR_AC [

5:0]  

Programmable, see WOR_AC [

9:0]  

9.2.9 RC OSC Regis

ter II (Address: 08h)  

Name  

R

/W  

Bit 7  

Bit 6  

Bit 5  

Bit 4  

Bit 3  

Bit 2  

Bit 1  

Bit 0  

WOR_SL9 WOR_SL8 WOR_AC5 WOR_AC4 WOR_AC3 WOR_AC2 WOR_AC1

WOR_AC0  

RC OSC II  

Reset  

W

0

0

0

0

0

0

0

0

WOR_AC [5:0]: WOR

Acitve Period (250 us ~ 16 ms).  

active time = (WOR_AC+1) * 250us  

WOR_SL [9:0]: WOR Sleep Period (8 ms ~ 8.192 s).  

sleep time = (WOR_SL+1) * 8ms  

9.2.10 RC OSC Register III (Address: 09h)  

Name  

R/W  

Bit 7  

Bit 6  

Bit 5  

Bit 4  

Bit 3  

Bit 2  

Bit 1  

Bit 0  

RCOSC_E  

1

TSEL  

0

WOR_MS  

1

RC OSC III  

Reset  

W

BBCKS1 BBCKS0

 

RCOT1  

RCOT0  

0

CALW  

0

0

0

0

BBCKS [1:0]: Clock select for internal digital block  

[00]:

F

SYCK

/ 2.

[01]:

F

SYCK

/ 4.

[10]:

F

SYCK

/ 8.

[11]:

F

SYCK

/ 16.  

F

SYCK

is A7106’s System clock. Refer to chapter 13 for details  

NOV. 2011, Version 1.2  

16  

AMICCOM Electronics Corporation  

A7106  

2.4G FSK/GFSK Transceiver  

RCOT [1:0]: current select for RC-oscillator.  

Refer to chapter 20 for details  

CALW: RC-oscillator calibration (Auto clear when done).  

[0]

: disable,

[1]:

enable.  

RCOSC_E: RC-oscillator enable.  

[0]:

Disable.

[1]:

Enable.  

TSEL: Timer select for TWOR function.  

[0]:

Use WOR_AC.

[1]:

Use WOR_SL.  

WOR_MS: WOR Mode Select.  

[0]:

WOR.

[1]:

TWOR.  

9.2.11 CKO Pin Con

trol Register (Address: 0Ah)  

Name  

R

/W  

Bit 7  

Bit 6  

Bit 5  

Bit 4  

Bit 3  

Bit 2  

Bit 1  

Bit 0  

CKO Pin Control  

Reset  

W

ECKOE  

1

CKOS3  

0

CKOS2  

1

CKOS1  

1

CKOS0  

1

CKOI  

0

CKOE  

1

SCKI  

0

ECKOE: External Cloc

k Output Enable for CKOS [3:0]= [0100] ~ [0111].  

[0]:

Disable.

[1]:

Enabl

e.  

CKOS [3:0]: CKO pin

output select.  

[0000]:

DCK (TX data c

lock) in TX mode, RCK (RX recovery clock) in RX mode.  

[0001]:

DCK (TX data c

lock) in TX mode, RCK (RX recovery clock) in RX mode.  

[0010]:

FPF (FIFO poin

ter flag).  

[0011]:

EOP, EOVBC,

EOFBC, EOADC, EOVCC, OKADC (Internal usage only).  

[0100]:

External clock o

utput= F

SYCK  

.

[0101]:

External clock o

utput / 2= F

SYCK

/ 2.  

[0110]:

External clock o

utput / 4= F

SYCK

/ 4.  

[0111]:

External clock o

utput / 8= F

SYCK

/ 8.  

[1xxx]:

Reserved.  

CKOI: CKO pin outpu

t signal invert.  

[0]:

Non-inverted outpu

t.

[1]:

Inverted output.  

CKOE: CKO pin Outp

ut Enable.  

[0]:

High Z.

[1]:

Enable

.  

SCKI: SPI clock input

invert.  

[0]:

Non-inverted input.

[1]:

Inverted input.  

9.2.12 GIO1 Pin Con

trol Register I (Address: 0Bh)  

Name  

R

/W  

Bit 7  

Bit 6  

Bit 5  

Bit 4  

Bit 3  

Bit 2  

Bit 1  

Bit 0  

GIO1 Pin Control I  

Reset  

W

—  

—  

—  

—  

GIO1S3 GIO1S2 GIO1S1 GIO1S0  

GIO1I  

0

GIO1OE  

1

0

0

0

0

GIO1S [3:0]: GIO1 pin function select.  

GIO1S [3:0]  

[0000]  

TX state  

RX state  

WTR (Wait until TX or RX finished)  

[0001]  

[0010]  

[0011]  

[0100]  

[0101]  

[0110]  

[0111]  

[1000]  

[1001]  

EOAC (end of access code)  

TMEO (TX modulation enable)  

FSYNC (frame sync)  

CD (carrier detect)  

Preamble Detect Output (PMDO)  

WAK (for WOR and TWOR)  

In phase demodulator input (DMII)  

SDO ( 4 wires SPI data out)  

TRXD In/Out (Direct mode)  

RXD (Direct mode)  

TXD (Direct mode)  

NOV. 2011, Version 1.2  

17  

AMICCOM Electronics Corporation  

A7106  

2.4G FSK/GFSK Transceiver  

[1010]  

[1011]  

[1100]  

[1101]  

[1110]  

[1111]  

In phase demodulator external input (EXDI0)  

External FSYNC input in RX direct mode  

Reserved  

FPF (FIFO extension)  

PDN_RX  

PDN_TX  

GIO1I: GIO1 pin output signal invert.  

[0]:

Non-inverted output.

[1]:

Inverted output.  

GIO1OE: GIO1pin output enable.  

[0]:

High Z.

[1]:

Enable.  

9.2.13 GIO2 Pin Con

trol Register II (Address: 0Ch)  

Name  

R

/W  

Bit 7  

Bit 6  

Bit 5  

Bit 4  

Bit 3  

Bit 2  

Bit 1  

Bit 0  

GIO2 Pin Control II  

Reset  

W

—  

—  

—  

—  

GIO2S3 GIO2S2 GIO2S1 GIO2S0  

GIO2I  

0

GIO2OE  

1

0

1

0

0

GIO2S [3:0]: GIO2 pin

function select.  

GIO2S  

[0000]  

TX state  

RX state  

WTR (Wait until TX or RX finished)  

[0001]  

[0010]  

[0011]  

[0100]  

[0101]  

[0110]  

[0111]  

[1000]  

[1001]  

[1010]  

[1011]  

[1100]  

[1101]  

[1110]  

[1111]  

EOAC

(end of access code)  

TMEO (

TX modulation enable)  

FSYNC (frame sync)  

CD (carrier detect)  

Preamble Detect Output (PMDO)  

WAK (for WOR and TWOR)  

Quadrature phase demodulator input (DMIQ)  

SDO (4 wires SPI data out)  

TRXD In/Out (Direct mode)  

RXD (Direct mode)  

TXD (Direct mode)  

Qua

drature phase demodulator external input (EXDI1)  

External FSYNC input in RX direct mode  

Reserved  

FPF (FIFO extension)  

PDN_RX  

PDN_TX  

GIO2I: GIO2 pin outpu

t signal invert.  

[0]:

Non-inverted outpu

t.

[1]:

Inverted output.  

GIO2OE: GIO2 pin Ou

tput Enable.  

[0]:

High Z.

[1]:

Enable

.  

In TX mode  

NOV. 2011, Version 1.2  

18  

AMICCOM Electronics Corporation  

A7106  

2.4G FSK/GFSK Transceiver  

SPI  

TX-Strobe  

PLL Mode  

Next Instruction  

No Command Required  

(SCS,SCK,SDIO)  

(dummy bits)  

Auto Back  

PDL+TDL  

PLL Mode  

RF Port  

(Output)  

Preamble +  

ID Code + Payload  

+ CRC  

GIO1 Pin – WTR  

(GIO1S[3:0]=0000)  

GIO2 Pin – TMOE  

(GIO2S[3:0]=0010)  

2-bits  

T0  

< 1us  

T2  

T1  

T3  

In RX mode  

SPI  

RX-

Strobe  

PLL Mod

e  

Next Instruction  

No Command Required  

(SCS,SCK,SDIO)  

Auto Back  

PLL Mode  

PDL+TDL  

RF Port  

(Input)  

Preamble +  

ID Code + Payload  

+ CRC  

GIO1 Pin – WTR  

(GIO1S[3:0]=0000)  

GIO2 Pin – FSYNC  

(GIO2S[3:0]=0001)  

ID-Matched  

T0  

< 1us  

T2  

T1  

9.2.14 Clock Regist

er (Address: 0Dh)  

Name  

R

/W  

Bit 7  

Bit 6  

Bit 5  

Bit 4  

Bit 3  

Bit 2  

Bit 1  

Bit 0  

Clock  

Reset  

R

/W  

GRC3  

1

GRC2  

1

GRC1  

1

GRC0  

1

CSC1  

0

CSC0  

1

CGS  

0

XS  

1

Refer to chapter 14 for details.  

CGS: Clock generator enable. Recommend CGS = [0]  

[0]:

Disable.

[1]:

Enable.  

CGS = 0 (recommend)  

Disable internal 32MHz PLL  

clock  

CGS = 1  

F

MCLK

= 32 MHz  

XS: Crystal oscillator select. Recommend XS = [1]  

[0]:

External clock.

[1]:

Crystal.  

GRC [3:0]: Clock generation reference counter.  

NOV. 2011, Version 1.2  

19  

AMICCOM Electronics Corporation  

A7106  

2.4G FSK/GFSK Transceiver  

GRC[3:0]  

Note  

Don’t care  

Recommend when CGS = 0  

F

XTAL

x (DBL+1) / (GRC+1) = 2M

 

When CGS = 1  

CSC [1:0]: system clock F

SYCK

divider select.  

CSC [1:0]  

System Clock F

SYCK  

Note  

F

SYCK

is used to determine  

1. Data

 

rate (0Eh)  

2. ADC

 

clock (1Eh)  

3. Internal

 

digital clock (09h)  

4.

CKO pin (0Ah)  

00  

F

MCLK  

01 (Recommend)  

10  

11  

F

MCLK

/ 2  

F

MCLK

/ 2  

F

MCLK

/ 4  

9.2.15 Data Rate Re

gister (Address: 0Eh)  

Name  

R

/W  

Bit 7  

Bit 6  

Bit 5  

Bit 4  

Bit 3  

Bit 2  

Bit 1  

Bit 0  

Data Rate  

Reset  

R

/W  

SDR7  

0

SDR6  

0

SDR5  

0

SDR4  

0

SDR3  

0

SDR2  

0

SDR1  

0

SDR0  

0

SDR [7:0]: Data rate d

ivision selection.  

Data rate =

F

SYCK

/ 32 /

(SDR [7:0]+1). Refer to chapter 13 for details.  

9.2.16 PLL Register

I (Address: 0Fh)  

Name  

R

/W  

Bit 7  

Bit 6  

Bit 5  

Bit 4  

Bit 3  

Bit 2  

Bit 1  

Bit 0  

PLL I  

Reset  

R

/W  

CHN7  

0

CHN6  

0

CHN5  

0

CHN4  

0

CHN3  

0

CHN2  

0

CHN1  

0

CHN0  

0

CHN [7:0]: LO channe

l number select.  

Refer to chapter 14 for

details.  

9.2.17 PLL Register

II (Address: 10h)  

Name  

R

/W  

Bit 7  

Bit 6  

Bit 5  

Bit 4  

Bit 3  

Bit 2  

Bit 1  

Bit 0  

R

W

DBL  

DBL  

1

RRC1  

RRC1  

0

RRC0  

RRC0  

0

CHR3  

CHR3  

1

CHR2  

CHR2  

1

CHR1  

CHR1  

1

CHR0  

CHR0  

1

IP8  

BIP8  

0

PLL II  

Reset  

DBL: Crystal frequenc

y doubler selection. Recommend DBL = [1]  

[0]:

Disable. F

XREF

= F

X

TAL  

.

[1]:

Enable. F

XREF

=2 * F

XTAL  

.

RRC [1:0]: RF PLL ref

erence counter setting.  

CHR [3:0]: PLL chann

el step setting.  

Refer to chapter 14 for

details.  

9.2.18 PLL Register

III (Address: 11h)  

Name  

R/W  

Bit 7  

Bit 6  

Bit 5  

Bit 4  

Bit 3  

Bit 2  

Bit 1  

Bit 0  

R

W

IP7  

BIP7  

0

IP6  

BIP6  

1

IP5  

BIP5  

0

IP4  

BIP4  

0

IP3  

BIP3  

1

IP2  

BIP2  

0

IP1  

BIP1  

1

IP0  

BIP0  

1

PLL III  

Reset  

BIP [8:0]: LO base frequency integer part setting. Recommend BIP[8:0] = [0x04B]  

BIP [8:0] are from address (0Fh) and (10h),  

IP [8:0]: LO frequency integer part value.  

IP [8:0] are from address (0Fh) and (10h),  

Refer to chapter 14 for details.  

NOV. 2011, Version 1.2  

20  

AMICCOM Electronics Corporation  

A7106  

2.4G FSK/GFSK Transceiver  

9.2.19 PLL Register IV (Address: 12h)  

Name  

R/W  

Bit 7  

Bit 6  

Bit 5  

Bit 4  

Bit 3  

Bit 2  

Bit 1  

Bit 0  

R

W

RAC15  

BFP15  

0

RAC14  

BFP14  

0

RAC13  

BFP13  

0

RAC12  

BFP12  

0

RAC11  

BFP11  

0

RAC10  

BFP10  

0

RAC9  

BFP9  

0

RAC8  

BFP8  

0

PLL IV  

Reset  

9.2.20 PLL Register V

 

(Address: 13h)  

Name  

R/W  

Bit 7  

Bit 6  

Bit 5  

Bit 4  

Bit 3  

Bit 2  

Bit 1  

Bit 0  

R

W

RAC7  

BFP7  

0

RAC6  

BFP6  

0

RAC5  

BFP5  

0

RAC4  

BFP4  

0

RAC3  

BFP3  

0

RAC2  

BFP2  

0

RAC1  

BFP1  

1

RAC0  

BFP0  

1

PLL V  

Reset  

BFP [15:0]: LO base fr

equency fractional part setting.  

BFP [15:0] are from ad

dress (11h) and (12h),  

RAC [15:0] (Read): Aut

o Frequency compensation value when FC is enabled  

RAC represented below  

{PRS(2Dh), FC(18h)}

 

RAC [15:0]  

1x  

01  

00  

PLLFF [15:0]  

{0, ACO [14:0]}  

{SYNCF, AC [14:0]}  

PLLFF [15:0]: fraction

al part in PLL,  

ACO [14:0] : Accumul

ated frequency compensated value,  

SYNCF : SYNC word d

etection flag.  

[0]

: not detected,

[1]:

d

etected.  

AC [14:0] : updated fr

equency compensated value.  

FP [15:0] (Read): LO f

requency fractional part setting.  

Refer to chapter 14 for

details.  

9.2.21 TX Register I

(Address: 14h)  

Name  

R

/W  

Bit 7  

Bit 6  

Bit 5  

Bit 4  

Bit 3  

Bit 2  

Bit 1  

Bit 0  

TX I  

Reset  

W

TXSM1  

0

TXSM0  

0

TXDI  

0

TME  

1

FS  

0

FDP2  

1

FDP1  

1

FDP0  

0

TXSM [1:0]: Moving a

verage for non-filter select. Recommend TXSM = [00]  

[00]:

not average.

[01]:

2 bit average.

[10]:

4 bit average.

[11]:

8 bit average  

TXDI: TX data invert. R

ecommend TXDI = [0].  

[0]:

Non-invert.

[1]:

Inv

ert.  

TME: TX modulation enable.  

[0]:

Disable.

[1]:

Enable.  

FS: Filter select. Recommend FS = [0]  

Gaussian filter (BT=0.7).  

[0]:

disable.

[1]:

enable.  

FDP [2:0]: Frequency deviation power setting. Refer to control register (15h). Recommend FDP = [110].  

9.2.22 TX Register II (Address: 15h)  

Name  

R/W  

Bit 7  

Bit 6  

Bit 5  

Bit 4  

Bit 3  

Bit 2  

Bit 1  

Bit 0  

TX II  

Reset  

W

—  

—  

PDV1  

0

PDV0  

0

FD4  

0

FD3  

1

FD2  

0

FD1  

1

FD0  

1

NOV. 2011, Version 1.2  

21  

AMICCOM Electronics Corporation  

A7106  

2.4G FSK/GFSK Transceiver  

PDV [1:0]: Reserved for internal usage onl

y

.

S

hall be set to [01].  

FD [4:0]: Frequency deviation setting.  

(FDP [2:0] )  

24  

F

DEV

= F

PFD

x 127 x (FD [4:0] + 1) x 2  

/ 2

 

.  

Where F

PFD

= F

XTAL

* (DBL+1) / (RRC [1:0]+1), PLL comparison frequency.  

Data Rate (Kbps)  

<= 50Kbps  

F

PFD  

FDP [2:0]  

110b  

PDV [1:0]  

01b  

FD[4:0]  

Fdev (KHz)  

122  

124  

127  

124  

12MHz  

16MHz  

24MHz  

32MHz  

F

PFD  

16MHz  

24MHz  

32MHz  

10110b (0x16)  

01111b (0x0F)  

01010b (0x0A)  

00111b (0x07)  

FD[4:0]  

10111b (0x17)  

01111b (0x0F)  

01011b (0x0B)  

Data Rate (Kbps)  

> 50Kbps  

FDP [2:0]  

110b  

PDV [1:0]  

01b  

Fdev (

KHz)  

186  

9.2.23 Delay Registe

r I (Address: 16h)  

Name  

R

/W  

Bit 7  

Bit 6  

Bit 5  

Bit 4  

Bit 3  

Bit 2  

Bit 1  

Bit 0  

Delay  

Reset  

W

DPR2