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A8105
2.4GHz FSK/GFSK SoC
Document Title
A8105 Data Sheet, 2.4GHz FSK/GFSK SOC
Revision History
Rev. No.
History
Issue Date
June, 2012
Sep, 2012
Sep, 2013
Remark
Objective
Obj
ctive
eliminary
0.0
0.1
0.2
Initial issue.
Add RF register
Modify RF register
0.3
0.4
0.5
0.6
Remove
RCADC
Oct,, 2013
Jan., 2014
Apr., 2014
Se
., 20
Preliminary
Preliminary
Preliminary
Preliminary
Revise Order information
Add 32Kbytes Flash version and related information.
Add die form and QFN48L in order information.
Add reset timing of stable power and RESETN pin
Add P2 registers for extra 4 GPIO for 32KB flash version
Important Notice
:
AMICCOM reserves the right to make changes to its products or to discontinue any integrated circuit product or service without
notice. AMICCOM integrated circuit products are not designed, intended, authorized, or warranted to be suitable for use in
life-support applications, devices or systems or other critical applications. Use of AMICCOM products in such applications is
understood to be fully at the risk of the customer.
Sep., 2014, Version 0.6 (Preliminary)
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AMICCOM Electronics Corporation
A8105
2.4GHz FSK/GFSK SoC
Table of Contents
5. Pin Description (I: input; O: output, I/O: input or output) …………………………………………………………………………………………..
.
5
Sep., 2014, Version 0.6 (Preliminary)
2
AMICCOM Electronics Corporation
A8105
2.4GHz FSK/GFSK SoC
Sep., 2014, Version 0.6 (Preliminary)
3
AMICCOM Electronics Corporation
A8105
2.4GHz FSK/GFSK SoC
Sep., 2014, Version 0.6 (Preliminary)
4
AMICCOM Electronics Corporation
A8105
2.4GHz FSK/GFSK SoC
Sep., 2014, Version 0.6 (Preliminary)
5
AMICCOM Electronics Corporation
A8105
2.4GHz FSK/GFSK SoC
Sep., 2014, Version 0.6 (Preliminary)
6
AMICCOM Electronics Corporation
A8105
2.4GHz FSK/GFSK SoC
1. General Description
A8105 is a high performance and low cost 2.4GHz FSK/GFSK system-on-chip (SOC) wireless transceiver. With on chip
fraction-N synthesizer, it can support the application of data rate from 5Kbps to 2Mbps and frequency hopping system and it
can support peripheral mode of Bluetooth Low Energy. It is a Bluetooth smart device. This device integrates high speed
pipeline 8051 MCU, 32/16KBytes In-system programmable flash memory, 2KB SRAM, various powerful functions and
excellent performance of a leading 2.4GHz FSK/GFSK RF transceiver. It can be operated with wide voltage from 2.0V ~ 3.6V.
A8105 has various operating modes, making it highly suited for systems where ultra-low power consumption is required.
Besides, A8105 has two flash memory sizes. One is 16KBytes (A8105F4) and the other is 32Kbytes (A8105F5) that supports
AES128 engine and CCM. The device has two package sizes. A8105F4 and A8105F5 are QFN5X5 40 pin package and only
A8105F5 has QFN5x5 48pin package.
2. Typical Applications
2400 ~ 2483.5 MHz ISM frequency hopping system
Smart remote controller
Home and building automation
Wireless toy and gaming
Helicopter and airplane radio controller
Bluetooth smart device
Wireless keyboard and mouse
3. Feature
Package size (QFN5 X5, 40 pins/ 48 pins).
High performance pipeline complicated 8051
Operation clock: 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 of crystal oscilla
or.
32/16KB Flash memory with copy protection, 2KB SARM
UART, I
2
C, SPI serial communication
Three 16/8-bit counter/timers
Two Channel PWM
Watchdog timer
Sleep timer
In-Circuit Debugger
In-System programming/ In-Application p
ogramming
24/ 28 GPIO(28 I/O only in QFN48)
RX current consumption with MCU in oper
tion mode :18mA
TX current consumption with MCU
n operation mode (18.5mA @ 0dBm, 21mA @ 6 dBm output power).
Deep sleep current (0.8 uA)
Low sleep current (3 uA)
Frequency band: 2400
–
MH
.
FSK and GFSK modula
High sensitivity:
-96dBm at 500Kbps data rate
-92dBm at 1Mbps
ata rate
-90dBm at 2Mbps data rate
Programma
le da
rate 4K ~ 2Mbps.
Fast settl
ng time synthesizer for frequency hopping system.
Built-
ther
al sensor for monitoring relative temperature.
B
ilt-in one channel 8-bits ADC for external analog voltage (0V ~ 1.2V).
Bu
t-in
ight channels 12-bits ADC for general purpose analog input (0V ~ 1.8 V).
Built-
n Low Battery Detector.
upport low cost crystal (8 /12 / 16 / 24MHz).
Low cost BLE application
Easy to use.
Change frequency channel by ONE register setting.
8-bits Digital RSSI for clear channel indication.
Auto RSSI measurement.
Auto WOR (wake up when receive RX packet).
Auto WOT (wake up to transmit TX packet).
Auto Calibrations.
Auto IF function.
Auto Frequency Compensation.
Auto CRC Check.
Auto FEC by (7, 4) Hamming code (1 bit error correction / code word).
Data Whitening for encryption and decryption.
Sep., 2014, Version 0.6 (Preliminary)
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AMICCOM Electronics Corporation
A8105
2.4GHz FSK/GFSK SoC
Separated 64 bytes RX and TX FIFO
Sep., 2014, Version 0.6 (Preliminary)
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AMICCOM Electronics Corporation
A8105
2.4GHz FSK/GFSK SoC
4. Pin Configurations
36
35
34
P1.5
1
N.C.
P1.4
P1.3
P1.2
P1.1
P3.7
GND
2
3
RESETN
VDD_S
4
5
33
32
VDD_D
BP_BG
VDD_R
6
7
8
P1.0
P0.7
31
30
29
28
P0.6
P0.5
P0.4
9
VDD_A
RFI
10
11
12
27
26
P0.3
2.0
RFO
N.C.
25
Fig 4-1. A8105 QFN 5×5 48 pin Package Top View
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AMICCOM Electronics Corporation
A8105
2.4GHz FSK/GFSK SoC
30
29
P1.4
P1.3
P1.2
P1.1
P3.7
GND
1
2
RESETN
VDD_S
3
4
28
27
VDD_D
BP_BG
VDD_R
5
6
7
P1.0
P0.7
26
25
24
P0.6
P0.5
P0.4
8
9
VDD_A
RFI
23
22
10
P0.3
RFO
21
Fig 4-2. A8105 QFN 5×5 40 pin Package Top View
Sep., 2014, Version 0.6 (Preliminary)
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AMICCOM Electronics Corporation
A8105
2.4GHz FSK/GFSK SoC
5. Pin Description (I: input; O: output, I/O: input or output)
Pin No.
Symbol
I/O
Function Description
1
NC
2
P3.7
NC
DIO/AI
RTC_O
No connection
3
4
RESETN
VDD_S
VDD_D
BP_BG
VDD_R
VDD_A
RFI
DI
RESETN
5
AO
AO
AO
AO
AO
AI
Voltage supply for SARM
6
VDD_D
BP_BG
VDD_R
VDD_A
RFI
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
RFO
NC
AO
RFO
NC
NC
VDD_V
CP
AI
VDD_VCO
AO
CP
XI
XI
AI
XO
XO
AO
VDD_PLL
REGI
VDD_P
REGI
P0.0
P0.1
P0.2
GND
P2.0
P0.3
P0.4
P0.
0.6
P
.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P3.0
P3.1
AO
AI
SPI_SCLK
SPI
MOSI
SPI_MISO
GND
DIO
DIO
DIO
D
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
P2.0
SPI_SSEL
GPIO/ ICE mode
I2C_SCL
I2C_SDA
INT2 /GIO1
Timer2_T2
Timer2_T2EX
INT3 /GIO2
INT4/ CKO
TTAG_TTDIO
TTAG_TTCK
PWM0/ADC4
PWM1/ADC5
UART0_RX/ADC6
UART0_TX/ADC7
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AMICCOM Electronics Corporation
A8105
2.4GHz FSK/GFSK SoC
41
42
43
44
45
46
47
48
P3.2
P2.1
P2.2
P2.3
P3.3
P3.4
P3.5
P3.6
DIO/AI
DIO
INT0/ADC0
P2.1
DIO
P2.2
DIO
P2.3
DIO/AI
DIO/AI
DIO/AI
DIO/AI
INT1/ADC1
Timer0_T0/ADC2
Timer1_T1/ADC3
RTC_I
Table 5-1 QFN5x5 48 Pin
Pin No.
1
Symbol
P3.7
I/O
Function Description
DIO/AI
RTC_O
No connection
2
NC
3
RESETN
VDD_S
VDD_D
BP_BG
VDD_R
VDD_A
RFI
DI
RESETN
Voltage supply for SARM
VDD_D
4
AO
AO
AO
AO
AO
AI
5
6
BP_BG
7
VDD_R
8
VDD_A
9
RFI
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
RFO
AO
AI
RFO
VDD_VCO
CP
VDD_VC
AO
AI
CP
I
XI
XO
XO
AO
A
AI
VDD_PLL
REGI
VDD_PLL
REGI
P0.0
SPI_SCLK
SPI_MOSI
SPI_MISO
GND
D
O
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
P0.1
P0.2
GND
SPI_SSEL
GPIO/ ICE mode
I2C_SCL
P
3
P0.4
P0.5
P0.6
I2C_SDA
P0.7
INT2 /GIO1
Timer2_T2
Timer2_T2EX
INT3 /GIO2
INT4/ CKO
TTAG_TTDIO
TTAG_TTCK
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
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AMICCOM Electronics Corporation
A8105
2.4GHz FSK/GFSK SoC
32
33
34
35
36
37
38
39
40
P1.6
P1.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
DIO
DIO
PWM0/ADC4
PWM1/ADC5
UART0_RX/ADC6
UART0_TX/ADC7
INT0/ADC0
DIO
DIO
DIO/AI
DIO/AI
DIO/AI
DIO/AI
DIO/AI
INT1/ADC1
Timer0_T0/ADC2
Timer1_T1/ADC3
RTC_I
Table 5-1 QFN5x5 40 Pin
6. Chip Block Diagram
35
34
3
32
31
40
39
38
37
36
1
2
P3.7
NC
30
29
P1.4
P1.3
Regulator
UART
1
it SA
ADC
PWM
0/1
interface
RTC
CLK GEN
3
4
Debug
ICE
RESETN
VDD_S
32/16KB
Flash
Memory
28
27
P1.2
P1.1
Timer
0/1/2
interface
80
Cor
2KB
SRAM
5
6
VDD_D
BP_BG
26
25
P1.0
P0.7
AD
AGC
Battery
Detect
AES128
CCM*
AFC
24
I2C
interface
7
8
VDD_R
VDD_A
P0.6
CRC
Filtering
23
22
P0.5
P0.4
P0.3
LNA
Fractional-
N PLL
Radio
Control
9
R
PA
VCO
SPI
interface
21
10
XOSC
CLK GEN
Sigma-Delta
Modulator
RFO
Gaussian
Filter
11
12
13
14
15
16
17
18
19
20
Fig 6-1. A8105 QFN5x5 40 pin Block Diagram
Note*: Only 32KByes version (A8105F5) support AES128/CCM*.
Sep., 2014, Version 0.6 (Preliminary)
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AMICCOM Electronics Corporation
A8105
2.4GHz FSK/GFSK SoC
7. Absolute Maximum Ratings
Parameter
Supply voltage range (VDD)
Digital IO pins range
With respect to
GND
Rating
-0.3 ~ 3.6
-0.3 ~ VDD+0.3
-0.3 ~ 2.1
14
Unit
V
GND
V
Voltage on the analog pins range
Input RF level
GND
V
dBm
C
V
Storage Temperature range
ESD Rating
-55 ~ 125
± 2K
HBM
MM
± 100
V
*Stresses above those listed under “Absolute Maximum Rating” may cause permanent dam
e to the device. These are
stress ratings only; functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
*Device is ESD sensitive. Use appropriate ESD precautions. HBM (Human Body
) is tested under MIL-STD-883F Method
3015.7. MM (Machine Mode) is tested under JEDEC EIA/JESD22-A115-A.
*Device is Moisture Sensitivity Level III (MSL 3).
Sep., 2014, Version 0.6 (Preliminary)
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AMICCOM Electronics Corporation
A8105
2.4GHz FSK/GFSK SoC
8. Electrical Specification
(Ta=25
℃
,
REGI = 3.3V, internal regulator voltage = 1.8V,
unless otherwise noted)
Parameter
Description
Min.
Type
Max.
Unit
General
Operating Temperature
-40
2.0
85
C
V
Supply Voltage
With internal regulator
Deep Sleep
3
6
Current Consumption
(MCU only, RF in sleep mode)
0.8
3
uA
uA
uA
mA
mA
Sleep(WOR/TWOR off)
Sleep (WOR /TWOR wake)
Normal
5
2.5
Current Consumption
Standby Mode
(RF with MCU in normal mode)
PLL Mode
9.5
1
.5
18
mA
mA
mA
mA
mA
RX Mode (AGC Off)
RX Mode (AGC On)
TX Mode (@0dBm output)
TX Mode (@6dBm output)
18.5
23.5
Synthesizer block
(includes crystal oscillator, PLL and VCO.)
Crystal start up time
Idle to standby (Xtal, 49US typ
,
is stable at 40ppm)
0.6
ms
16
Crystal frequency
Crystal ESR
MHz
ohm
MHz
dBc
80
VCO Operation Frequency
PLL phase noise
2400
2483.5
80
95
105
Offset 100k
Offset 5
0K
Offset 1M
PLL settling time
75
0
@Lo
p BW = 100Khz
S
TX
Output power range
Out Band Spurious Emission
-10
10
-36
-30
-47
-47
dBm
dBm
dBm
dBm
dBm
30MHz~1GHz
1GHz~12.75GHz
1.8GHz~ 1.9GHz
5.15GHz~ 5.3GHz
500Kbps
Frequency deviati
n
186K
250K
500K
Hz
Hz
1M
2M
Hz
Data rate
4K
2M
Bps
S
TX settling time
70
Loop bandwidth 100K
RX
dBm
dBm
dBm
KHz
KHz
dB
Receiver sensitivity
@ BER = 0.1%
Data rate 2M (F
IF
= 2MHz)
Data rate 1M (F
IF
= 1MHz)
Data rate 500K (F
IF
= 1MHz)
-90
-92
-96
IF frequency bandwidth
IF center frequency
Interference
1200/2400
1000/2000
11
Co-Channel (C/I
0
)
1
st
Adjacent Channel (C/I
1
)
2
dB
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AMICCOM Electronics Corporation
A8105
2.4GHz FSK/GFSK SoC
2
nd
Adjacent Channel (C/I
2
)
3
rd
Adjacent Channel (C/I
3
)
-18
-28
-12
dB
dB
Image (C/I
IM
)
dB
Maximum Operating Input Power
Spurious Emission
@RF input (BER=0.1%)
30MHz~1GHz
0
dBm
dBm
dBm
dBm
-52
-47
-10
1GHz~12.75GHz
@RF input
RSSI Range with AGC turn on
-100
0
12Bit SAR ADC
Input voltage range
External reference voltage
Input capacitor
1.
V
V
1.8
25
pF
Bandwidth
200
0
KHz
bit
EOB, effective number of bits
INL
+/- 2
+/-1
LSB
LSB
uS
DNL
Conversion time
Current consumption
1
8
0.4
mA
Regulator
Regulator settling time
Band-gap reference voltage
Regulator output voltage
Pin 19 connected to 1nF
200
1.21
1.8
s
V
V
Digital IO DC characteristics
High Level Input Voltage (V
IH
)
Low Level Input Voltage (V
IL
)
0.8*VDD
VDD
0.2*VDD
VDD
V
V
V
V
0
VDD-0.4
0
High Level Output Voltage (V
OH
)
@I
OH
= -0.5mA
@I
OL
=
mA
Low Level Output Voltage (V
OL
)
0.4
Sep., 2014, Version 0.6 (Preliminary)
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AMICCOM Electronics Corporation
9. SFR & RFR(Radio Frequency Register)
A8105 contains standard 8051 SFRs(special function registers) and RFR (RF control registers). A8051
’
s SFR location is almost
the same as the standard 8052 SFR location. RFR is Radio Frequency Registers are located in XDATA spaces and located in
0x0800 ~ 0x08FF. For more detail information, please reference Section 9.2.
9.1 SFR Overview
Table 9.1 A8105 Special Function Registers (SFRs) table
0/8
1/9
2/A
3/B
4/C
5/D
6/E
7/F
0xF8
0xF0
0xE8
0xE0
0xD8
0xD0
0xC8
0xC0
0xB8
0xB0
0xA8
0xA0
0x98
0x90
0x88
0x80
EIP
B
OSCCON
I2CSADR
I2CSCR
I2CSBUF
I2CMSA
SPCR
I2CMCR
SPSR
I2CMBU
SP
R
I2C
TP
SSCR
EIE
ACC
P3OE
P1OE
P0OE
T2IF
P3PUN
P1PUN
P0PUN
RLDL
P3WUN
P1WUN
P0WUN
RLDH
SPCR1
SPSR1
PDR1
SSCR1
WDCON
PSW
T2CON
TL2
TH2
DEVICR
IP
P3
PCONE
PWM1CON
PWM0CON
P2OE
RSFLAG
PWM1H
PWM0H
P2PUN
IOSEL
PWM1L
PWM0L
P2WU
AD
CH
IE
P2
SOCN0
P1
SBUF0
EIF
FLASHCTRL
MR
USBADDR USBDATA
TCON
P0
TMOD
SP
TL0
TL1
TH0
TH1
CKCON
DPS
DMAIR
PCON
DPL0
DPH0
DPL1
DPH1
: It means bit-addressab
: It means reserved.
Following are description of S
Rs related to the operation of A8105 System Controller. Detailed descriptions of the remaining
SFRs are including the sections of the datasheet associated with their corresponding system function. The arithmetic section of
the processor performs extensive data manipulation and is comprised of the 8-bit arithmetic logic unit (ALU), an ACC(0xE0)
register, B(0xF0) registe
and
SW(0xD0) register.
PSW (Address:
h)
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
D0h
PSW
Reset
R/W CY
0
AC
0
F0
0
RS1 RS2
OV
F1
0
P
0
0
0
0
Program Status Word register
The ALU performs typical arithmetic operations as: addition, subtraction, multiplication, division and additional operations such
as: increment, decrement, BCD-decimal-add-adjust and compare. Within logic unit are performance: AND, OR, Exclusive OR,
complement and rotation. The Boolean processor performance the bit operations as: set, clear, complement, jump-if-not-set,
jump-if-set-and-clear and move to/from carry.
CY
– Carry flag
AC
– Auxiliary carry
F0
–
General purpose flag 0
RS[1:0]
– Register bank select bits
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AMICCOM Electronics Corporation
A8105
2.4GHz FSK/GFSK SoC
OV
– Overflow flag
F1
– General purpose flag 1
P
– Parity flag
The PSW contains several bits that reflect the current state of the CPU.
ACC (Address: E0h)
Address/Name R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
E0h
ACC
Reset
R/W
0
0
0
0
0
0
0
0
Accumulator ACC Register
B (Address: F0h)
Address/Name R/W Bit
7 Bit
6 Bit
5 Bi
4 Bit
3 Bit
2 Bit
1 Bit
0
F0h
R/W
B
Reset
0
0
0
0
0
0
0
0
ter
The B register is used during multiply and divide operations.
ther cases may be used as normal SFR.
Sep., 2014, Version 0.6 (Preliminary)
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AMICCOM Electronics Corporation
A8105
2.4GHz FSK/GFSK SoC
9.2 RFR Overview
Address /
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
Name
0x800h
MODE
0x801h
MODEC1
0x802h
—
W
R
W
R
W
R
RESETN FWPRN
FRPRN ADC12RN
CRCF
STRB5
—
XER
STRB3
FPF
WWSE
WWSE
BFCRN
PLLER
STRB2
—
FMT
FMT
—
—
FECF
STRB6
CER
STRB4
TRSR
STRB1
—
FMS
FMS
TRER
STRB0
—
ADCM
ADCM
STRB7
WTR
P_CKO P_IRQ1O
P_IRQ2O
ARSSI
ARSSI
AIF
AIF
DFCD
CD
MODEC2
WWS_AC WWS_AC
0x803h
CALC
0x804h
FIFO I
0x805h
FIFO II
R/W
W
FIFOREV
FEP5
RSSC
FEP4
PSA4
VDC
FEP3
PSA3
VCC
FEP2
PSA2
VBC
FEP1
PSA1
F
C
FEP0
PSA0
7
6
FEP7
FEP6
W
FPM1
FPM0
PSA5
0x806h
RC OSC 1
W
WWS_SL7 WWS_SL6 WWS_SL5 WWS_SL4 WWS_SL3 WW
SL2 WWS_SL1 WWS_SL0
0x807h
RC OSC 2
0x808h
RC OSC 3
0x809h
WWS_AC WWS_AC WWS_AC WWS_AC WWS_AC WWS_AC
WWS_SL9 WWS_SL8
W
5
4
3
2
1
0
W
BBCKS1 BBCKS0
RCOT[2:0]
—
CRCSW BL
RCTS
TSEL
TWOR_E
W
R
W
R
WCKSEL[
:0]
–
MVS[1:0]
RCOC[9:8]
TMRE MAN
ENCAL
ENCAL
MCALS
RC OSC 4
NUMLH[11:8]
MRCT8 —
MRCT9
—
—
0x80Ah
RC OSC 5
NUMLH7 NUMLH6 NUMLH5 NUMLH4 NUMLH3 NUMLH2 NUMLH1 NUMLH0
W
R
MRCT7
RCOC7
MRCT6
RCOC6
MRCT5
RCOC5
M
CT4
COC4
MRCT3
RCOC3
MRCT2
RCOC2
MRCT1
RCOC1
MRCT0
RCOC0
0x80Bh
RC OSC 6
0x80Ch
RC OSC 7
0x80Dh
RC OSC 8
0x80Eh
CKO Pin
0x80Fh
GPIO1 Pin I
0x810h
GPIO2 Pin II
0x811h
Clock
0x812h
Data rate
0x813h
PLL I
0x814h
PLL II
W
W
TGNUM[11:8]
TGNUM[7:0]
WAKEBBI
E
W
DOCKOE CKOS
CKOS2
GIO1S3
GIO2S3
GRC1
SDR5
CHN5
RRC0
IP5
CKOS1
GIO1S2
GIO2S2
GRC0
SDR4
CHN4
CHR3
IP4
CKOS0
GIO1S1
GIO2S1
IDREV
SDR3
CHN3
CHR2
IP3
CKOI
GIO1S0
GIO2S0
CSC0
SDR2
CHN2
CHR1
IP2
INTT1IE
—
W
VGC1
HBW
GRC3
SDR7
CHN7
DBL
VGC0
GIO1I
GIO2I
CGS
_AC
8
W
—
R/W
R/W
R/W
R/W
R/W
GRC2
SDR6
CHN6
RRC1
IP6
XS
SDR1
CHN1
CHR0
IP1
SDR0
CHN0
IP8
0x
5h
PL
IP7
IP0
W
R
W
R
FP15
—
FP7
AC7
FP14
AC14
FP6
FP13
AC13
FP5
FP12
AC12
FP4
FP11
AC11
FP3
FP10
AC10
FP2
FP9
AC9
FP1
AC1
FP8
AC8
FP0
AC0
0x81
h
PLL IV
0x817h
PLL V
AC6
AC5
AC4
AC3
AC2
0x818h
TX I
0x819h
TX II
0x81Ah
Delay I
0x81Bh
Delay II
W
W
W
W
GDR
FD7
TMDE
FD6
TXDI
FD5
TME
FD4
FS
FDP2
FD2
FDP1
FD1
FDP0
FD0
FD3
TDL0
DPR2
WSEL2
DPR1
WSEL1
DPR0
WSEL0
TDL1
PDL2
PDL1
PDL0
AGC_D1 AGC_D0
RS_DLY2 RS_DLY1 RS_DLY0
Sep., 2014, Version 0.6 (Preliminary)
13
AMICCOM Electronics Corporation
A8105
2.4GHz FSK/GFSK SoC
0x81Ch
RX
W
MSCRC
RXSM1
RXSM0
AFC
RXDI
DMG
BWS
ULS
W
R
W
R
W
R
AGCE
ADC8
PKIS1
—
IFPK
RH7
MIC
MICR
PKIS0
—
VRSEL
RH6
IGC1
IGCR1
PKT1
—
MS
RH5
IGC0
IGCR0
PKT0
—
MSCL4
RH4
MGC1
MGCR1
DCH1
—
MSCL3
RH3
MGC0
MGCR0
DCH0
—
MSCL2
RH2
LGC1
LGCR1
RSAGC1 RSAGC0
VTB1
MSCL1
RH1
LGC0
LGCR0
0x81Dh
RX Gain I
0x81Eh
RX Gain II
VTB0
MSCL0
RH0
0x81Fh
RX Gain III
W
R
W
R
MXD
RL7
RTH7
ADC7
CSS
RL6
RTH6
ADC6
HPLS
RL5
RTH5
ADC5
MHC1
RL4
RTH4
ADC4
MHC0
RL3
RTH3
ADC3
LHC1
RL2
RTH2
ADC2
LHC0
RL1
RTH
ADC1
XADSP
RL0
RTH0
ADC0
0x820h
RX Gain IV
0x821h
RSSI Threshold
0x822h
ADC
0x823h
Code I
0x824h
Code II
0x825h
Code III
W
W
W
W
RSM1
XDS
DCL2
IDL
RSM0
MCS
DCL1
WS6
ERSS
WHTS
DCL0
WS5
FSARS
FECS
ETH2
WS4
SYNCS
CRCS
ETH1
WS3
XADS
PML2
ETH0
WS2
RS
PML1
PMD1
WS1
CDM
PML0
PMD0
WS0
W
R
RNUM0_2 RNUM0_1 RNUM0_0
MFBS
FBCF
M
FB
MFB2
FB2
MFB1
FB1
MFB0
FB0
0x826h
IF Calibration I
—
—
—
RNUM1_
1
FCD1
VCOC1
W
PWORS
TRT2
TRT1
TRT0
MRCKS RNUM1_2
RNUM1_0
0x827h
IF Calibration II
R
W
—
—
—
PKS
—
FC
4
MVCS
FCD3
FCD2
FCD0
VCOC0
0x828h
VCO current
Calibration
0x829h
VCO band
Calibration I
0x82Ah
VCCS
VCOC3
VCOC2
TWORF
DCD1
—
R
W
R
—
DCD0
—
—
DAGS
—
FVCC
DV
—
VCB3
MVBS
VBCF
VCB2
MVB2
VB2
VCB1
MVB1
VB1
VCB0
MVB0
VB0
VCO band
Calibration II
0x82Bh
W
DAMV1
DAMV
VTH2
VTH1
VTH0
VTL2
VTL1
VTL0
W
R
RGS
—
R
1
GV
RGV0
RGV0
PACTL
BDF
BVT2
BVT2
BVT1
BVT1
BVT0
BVT0
BDS
BDS
Battery detect
0x82Ch
TX test
0x82Dh
W
W
W
IFBC1
MT
C0
DCM1
DCV6
TXCS
DCM0
DCV5
PAC1
MLP1
DCV4
PAC0
MLP0
DCV3
TBG2
SLF2
DCV2
TBG1
SLF1
DCV1
TBG0
SLF0
DCV0
Rx DEM test I
0x82Eh
Rx DEM test II
0x82Fh
DCV7
Charge Pump
Current
0x830h
Crys
test
0x8
PLL t
st
0x832h
VCO test I
0x833h
VCO test II
0x834h
IFAT
0x835h
W
CPM3
CPM2
CPM1
CPM0
CPT3
CPT2
CPT1
CPT0
W
W
W
W
W
W
PRS
QDS
QCLIM
PRIC1
DBD
XCC1
PRRC1
TLB0
XCC0
PRRC0
RLB1
XCP1
SDPW
RLB0
RFT1
—
XCP0
NSDO
MGS
RFT0
LIMC
CPS
MDEN
PMPE
PRIC0
TLB1
DEVGD2 DEVGD1 DEVGD0
CHD3
MPDT5
ASMV2
CHD2
MPDT4
ASMV1
CHD1
MPDT3
ASMV0
CHD0
MPDT2
SDMS
RFT3
RFT2
MPDT1
OLM
MPDT0
CPCS
CPH
RF test I
W
R
W
—
—
—
CRS3
CRSR3
STMP
CRS2
CRSR2
STM5
CRS1
CRSR1
STM4
CRS0
CRSR0
STM3
SRS2
SRSR2
STM2
SRS1
SRSR1
STM1
SRS0
SRSR0
STM0
0x836h
RF test II
0x837h
Sep., 2014, Version 0.6 (Preliminary)
14
AMICCOM Electronics Corporation
A8105
2.4GHz FSK/GFSK SoC
RF test III
0x838h
RF test IV
R
W
R
—
—
—
—
DVI1
—
STMR5
DVI0
—
STMR4
FBG4
FBGR4
CTR4
STMR3
FBG3
FBGR3
CTR3
STMR2
FBG2
FBGR2
CTR2
STMR1
FBG1
FBGR1
CTR1
STMR0
FBG0
FBGR0
CTR0
W
FGC1
FGC0
CTR5
0x839h
RF test V
R
FGCR1
FGCR0
CTRR5
CTRR4
CTRR3
CTRR2
CTRR1
CTRR0
0x83Ah
Channel Index
0x83Bh
W
W
W
W
W
W
—
—
CHIDX[5:0]
CRCINIT2 CRCINIT2 CRCINIT2 CRCINIT2 CRCINIT1 CRCINIT1 CRCINIT1 CRCINIT1
CRC1
0x83Ch
CRC2
0x83Dh
CRC3
0x83Eh
CRC4
0x83Fh
CRC5
0x840h
CRC6
0x841h
3
2
1
0
9
8
7
6
CRCINIT1 CRCINIT1 CRCINIT1 CRCINIT1 CRCINIT1 CRCINIT1
CRCINIT9 CRCIN
T8
5
4
3
2
1
0
CRCINIT7 CRCINIT6 CRCINIT5 CRCINIT4 CRCINIT3 CRCINIT2 CRCINIT
CRCINIT0
CRCINR2 CRCINR2 CRCINR2 CRCINR2 CRCINR1 CRCINR1 CRCINR1 CRCINR1
3
2
1
0
9
8
7
6
CRCINR1 CRCINR1 CRCINR1 CRCINR1 CRCINR1 CRCINR
CRCINR9 CRCINR8
CRCINR7 CRCINIR6 CRCINIR5 CRCINIR4 CRCINIR3 CRCINIR2 CRCINIR1 CRCINIR0
5
4
3
2
1
W
W
R
MDAG7
ADAG7
MDAG6
ADAG6
MDAG5
ADAG5
MDAG4
ADAG4
MDAG3
AD
MDAG2
ADAG2
MDAG1
ADAG1
MDAG0
ADAG0
VCO band
Calibration III
0x842h
VCO deviation
Calibration I
0x843h
VCO deviation
Calibration II
0x844h
W
R
DEVS3
DEVA7
MVDS
ADEV7
DEVS2
DEVA6
DEVM6
ADEV6
DEVS1
DEVA5
DEVM5
ADEV5
DEVS0 DAMR_M
VMTE_M VMS_M
MSEL
DEVA0
DEVM0
ADEV0
DEVA4
DEVM
ADEV4
DEVA3
DEVM3
ADEV3
DEVA2
DEVM2
ADEV2
DEVA1
DEVM1
ADEV1
W
R
VCO deviation
W/R
Calibration III
VMG7
VMG6
VMG5
MG4
VMG3
VMG2
FPS2
VMG1
FPS1
VMG0
FPS0
0x845h
ADC Control
W
AVSEL1
—
AVSEL0 MVSEL1 MVSEL0
RADC
WN0
0x846h
WOT
W
SPSS
GL
GH6
WMODE
CHGL5
CHGH5
WN1
0x847h
Channel Group I
0x848h
Channel Group II
0x849h
R/W CHGL7
R/W CHGH7
CHGL4
CHGH4
CHGL3
CHGH3
CHGL2
CHGH2
CHGL1
CHGH1
CHGL0
CHGH0
Charge Pump
Current II
0x84Ah
VCO modulatio
Delay
W
CPTX3
—
CPTX2
CPTX1
CPTX0
CPRX3
CPRX2
DEVD2
CPRX1
DEVD1
CPRX0
DEVD0
W
W
INTPRC DEVFD2 DEVFD1 DEVFD0
VRPL0
0x84Bh
INTC
VRPL1
VCOSC5 VCOSC4 VCOSC3 VCOSC2 VCOSC1 VCOSC0
W
R
DC_SEL
RXDCS PREDN2
PREDN1 PREDN0 PREUP2 PREUP1 PREUP0
DCOUT[7:0]
0x8
DE
TX_HEAD TX_HEAD TX_HEAD TX_HEAD TX_HEAD TX_HEAD TX_HEAD TX_HEAD
ER15 ER14 ER13 ER12 ER11 ER10
ER9 ER8
RX_HEAD RX_HEAD RX_HEAD RX_HEAD RX_HEAD RX_HEAD RX_HEAD RX_HEAD
ER15 ER14 ER13 ER12 ER11 ER10
ER9 ER8
TX_HEAD TX_HEAD TX_HEAD TX_HEAD TX_HEAD TX_HEAD TX_HEAD TX_HEAD
ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0
RX_HEAD RX_HEAD RX_HEAD RX_HEAD RX_HEAD RX_HEAD RX_HEAD RX_HEAD
W
R
0x84Dh
BLE_HEADER0
W
0x84Eh
BLE_HEADER1
R
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
0x84Fh
ID0
0x850h
ID1
W/R
W/R
ID31
ID30
ID29
ID28
ID27
ID26
ID25
ID24
ID23
ID22
ID21
ID20
ID19
ID18
ID17
ID16
Sep., 2014, Version 0.6 (Preliminary)
15
AMICCOM Electronics Corporation
A8105
2.4GHz FSK/GFSK SoC
0x851h
ID2
0x852h
ID3
0x853h
DID0
0x854h
DID1
0x855h
DID2
0x856h
DID3
0x857h
EXT1
0x858h
EXT2
W/R
W/R
R
ID15
ID7
ID14
ID6
ID13
ID5
ID12
ID4
ID11
ID3
ID10
ID2
ID9
ID1
ID8
ID0
DID31
DID23
DID15
DID7
—
DID30
DID22
DID14
DID6
XEC
DID29
DID21
DID13
DID5
DID28
DID20
DID12
DID4
BGS
DID27
DID19
DID11
DID3
DID26
DID18
DID10
DID2
DID25
DID17
DID9
DID1
B
D
DID24
DID16
DID8
R
R
R
DID0
W/R
W
BREV
VTRB1
CGC
LIMB
VMRB3
IWC
ADCCS
VMRB2
L
REGR
VMRB0
VCSW
VTRB3
—
VTRB2
IFAS
VTRB0
IWA
VMRB1
VCS
0x859h
EXT3
W
W
R
W
R
BUFS
—
ADCIE
CKS
—
—
—
—
—
MODE
MODE
—
MVS2
MVS2
AD
AD
MVS1
MVS1
ADCYC
ADC10
MVS0
MVS0
ENADC
ADC9
ADCE
ADCE
DTMP
ADC8
0x85Ah
ADCCTL
0x85Bh
ADCAVG1
MVADC11 MVADC10
MVADC9 MVADC8
0x85Ch
ADCAVG2
0x85Dh
R
R
MVADC7 MVADC6 MVADC5 MVADC4 MVADC3 MVADC2 MVADC1 MVADC0
ADC7
ADC6
ADC5
ADC
ADC3
ADC2
ADC1
ADC0
ADCAVG3
0x85Eh
TMRITV1
0x85Fh
TMRITV2
0x860h
TMRWOR0
0x861h
TMRWOR1
W
W
W
W
MR_ITV[15:8]
TMR_ITV[7:0]
—
TMRWORS
—
–
TMR_OFS4 TMR_OFS3 TMR_OFS2 TMR_OFS1 TMR_OFS0
W
R
TMRON
—
T
IE
TMRIF
TMRCOR TMRWOR
TMRCKS1 TMRCKS0
TMR_CE
0x862h
TMRCTL
0x863h
PWRCTL0
0x864h
PWRCTL1
0x865h
PWRCTL2
MRIE
TMRIF
—
—
TMRCKS1 TMRCKS0
TMR_CE
W
W
CBG2
EBOD
G1
ENAV
—
CBG0
QDSA
—
PDNS
STA
ENDL2
CEL
ENDL1
SVREF
RGC0
ENDL0
CELA
ENDV
RCR1
QDSD
RCR0
W
P3PUNIE
RGC1
RCHC
0x866h
PWRCTL3
0x867h
PWRCTL4
0x
8h
W
MR[7:0] (analog)
MS[7:0] (analog)
dc_shift[7:0]
W
W
DC
0x86
h
TX5DY
0x87Ch
ACKRT
W/R
W
HDRSW
—
EARTS
EACKS
TX_5DLY[4:0]
—
LL_TIME_OUT[5:0]
Legend: – = unimplemented
Sep., 2014, Version 0.6 (Preliminary)
16
AMICCOM Electronics Corporation
A8105
2.4GHz FSK/GFSK SoC
9.2.1 Mode Register (Address: 0x800h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
R
RESETN
FWPRN
FECF
—
FRPRN
CRCF
—
ADC12RN
—
XER
—
BFCRN
PLLER
—
—
TRSR
—
—
TRER
—
MODE
Reset
—
—
CER
—
RESETN: Write to this register by 0x00 to issue reset command, then it is auto clear
FWPRN: FIFO Write Point Software Reset.
FRPRN: FIFO Read Point Software Reset.
ADC12RN: 12-bits ADC Software Reset.
BFCRN: IF Filter Bank Calibration Software Reset.
FECF: FEC flag.
[0]:
FEC pass.
[1]:
FEC error.
CRCF: CRC flag.
[0]:
CRC pass.
[1]:
CRC error.
CER: RF chip enable status.
[0]:
RF chip is disabled.
[1]:
RF chip is enabled.
XER: Internal crystal oscillator enabled status.
[0]:
Crystal oscillator is disabled.
[1]:
Crystal oscillator is enabled.
PLLER: PLL enabled status.
[0]:
PLL is disabled.
[1]:
PLL is enabled.
TRSR: TRX Status Register.
[0]:
RX state.
[1]:
TX state.
Serviceable if TRER=1 (TRX is enable).
TRER: TRX state enabled status.
[0]:
TRX is disabled.
[1]:
TRX is ena
9.2.2 Mode Control Regis
er 1 (Address: 0x801h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
R
STRB7
STRB6
STRB5
STRB4
STRB3
FSYNC
0
STRB2
STRB1
STRB0
MODEC1
Reset
ARCWTR P_CKO P_IRQ1O
P_IRQ2O
1
0
1
0
0
0
0
STRB[7:0]: St
obe
ommand register.
[80]:
Sle
p mode
[90]:
Idle
e.
[A0]:
Stan
by mode.
[B0]:
PLL mode.
[C0]:
TX mode.
[D0]:
RX mode.
Reverse for other settings.
ARCWTR: Read ARCWTR output signal.
P_CKO: Read P_CKO pin output signal.
P_IRQ1O: Read P_IRQ1O pin output signal.
P_IRQ2O: Read P_IRQ2O pin output signal.
Sep., 2014, Version 0.6 (Preliminary)
17
AMICCOM Electronics Corporation
A8105
2.4GHz FSK/GFSK SoC
FSYNC: Read Frame sync ok output signal.
9.2.3 Mode Control Register 2 (Address: 0x802h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
R
ARSSI
ARSSI
0
AIF
AIF
0
DFCD
CD
WWSE
WWSE
0
FMT
FMT
0
FMS
FMS
0
ADCM
ADCM
0
MODEC2
Reset
0
ARSSI: Auto RSSI measurement while entering RX mode.
[0]:
Disable.
[1]:
Enable.
AIF (Auto IF Offset): RF LO frequency will auto offset one IF frequency while entering RX mode.
[0]:
Disable.
[1]:
Enable.
CD / DFCD:
DFCD (Data Filter by CD):
The received package will be filtered out if Carrier Detector sign
l is inactive.
[0]:
Disable.
[1]:
Enable.
CD (Read): Carrier detector signal.
[0]:
Input power below threshold.
[1]:
Input power above threshold.
WWSE: Reserved for internal usage only. Shall be set to [0].
FMT: Reserved for internal usage only. Shall be set to [0].
FMS: Direct/FIFO mode select.
[0]:
Direct mode.
[1]:
FIFO mode.
ADCM: ADC measurement enable (Auto clear when do
[0]:
Disable measurement or measurement finished.
[1]:
En
measurement.
ADCM
A8105 @ Standby mode
A8105 @ RX mode
[0] Disable
ADC
D
i
s
a
b
l
e
A
D
C
Measure temperature, external A
alog D
gital
Convert
[1]
Measure RSSI, carrier detect
9.2.4 Calibration Control Regist
Address: 0x803h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WWS_AC WWS_AC
W
R
RSSC
VDC
VCC
VBC
FBC
FIFOREV
7
6
CALC
Reset
—
—
—
0
0
0
0
0
WWS_AC [7:6]
Se
9.2.8
FIFOREV
FO reverse enable.
[0]:
Disabl
[1]:
Enable
RSSC: RSSI calibration enable (Auto clear when done).
[0]:
Disable.
[1]:
Enable.
VCC: VCO Current calibration enable (Auto clear when done).
[0]:
Disable.
[1]:
Enable.
VBC: VCO Bank calibration enable (Auto clear when done).
[0]:
Disable.
[1]:
Enable.
VDC: VCO Deviation calibration enable (Auto clear when done).
[0]:
Disable.
[1]:
Enable.
Sep., 2014, Version 0.6 (Preliminary)
18
AMICCOM Electronics Corporation
A8105
2.4GHz FSK/GFSK SoC
FBC: IF Filter Bank calibration enable (Auto clear when done).
[0]:
Disable.
[1]:
Enable.
9.2.5 FIFO Register I (Address: 0x804h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FIFO I
Reset
W
FEP7
0
FEP6
0
FEP5
1
FEP4
1
FEP3
1
FEP2
1
FEP1
1
FEP0
1
FEP [7:0]: FIFO End Pointer for TX FIFO and Rx FIFO.
Refer to chapter chapter 21 for details.
9.2.6 FIFO Register II (Address: 0x805h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FIFO II
Reset
W
FPM1
0
FPM0
1
PSA5
0
PSA4
0
PSA3
0
PSA2
0
PSA1
0
PSA0
0
FPM [1:0]: FIFO Pointer Margin
PSA [5:0]: Used for Segment FIFO.
Refer to chapter 21 for details.
9.2.7 RC OSC Register I (Address: 0x806h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit
Bit 3
Bit 2
Bit 1
Bit 0
RC OSC I
Reset
W
WWS_SL7 WWS_SL6 WWS_SL5 W
S_SL4 WWS_SL3 WWS_SL2 WWS_SL1 WWS_SL0
0
0
0
0
0
0
0
0
WWS_SL [9:0]: 10-bits WWS_SL Timer for TWWS Functio
(7.8ms ~ 7.99s).
WWS_SL [9:0] are from address (0x806h) and (0x8
7h).
9.2.8 RC OSC Register II (Address: 0x8
7h)
Name
R/W
Bit 7
it 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RC OSC II
Reset
W
WWS_SL9
WS
SL8 WWS_AC5 WWS_AC4 WWS_AC3 WWS_AC2 WWS_AC1 WWS_AC0
0
0
0
0
0
0
0
0
WWS_SL [9:0]: 10-bits WWS_SL Timer for TWWS Function (7.8ms ~ 7.99s).
WWS_SL [9:0] are from addre
s (0x
06h) and (0x807h).
WWS_AC [8:0]: 9-bits WWS_AC Timer for TWWS Function (244us ~ 15.6ms).
9.2.9 RC OSC
gister III (Address: 0x808h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RC
SC III
R
W
BBCKS1
0
BBCKS0
0
—
—
CRCSW
—
BLE_ON
—
RCTS
1
TSEL
0
TWWS_E
1
BBCKS [1:0]: Clock select for internal digital block
[00]: F
SYCK
/ 8.
[01]:
F
SYCK
/ 16.
[10]:
F
SYCK
/ 32.
[11]:
F
SYCK
/ 64.
F
SYCK
:System clock. Should be set to 8MHz.
CRCSW
: CRC select (BLE_ON=0).
[0]:
Select CRC-16, CCITT.
[1]:
Select CRC-24 (BLE).
BLE_ON: Bluetooth Low-Energy Mode enable.
[0]:
Disable.
[1]:
Enable.
RCTS: Internal / External 32.768k Hz oscillator selection.
[0]:
Internal.
[1]:
External.
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2.4GHz FSK/GFSK SoC
TSEL: Timer select for TWWS function.
[0]:
Use WWS_AC.
[1]:
Use WWS_SL.
TWWS_E: Enable TWWS function.
[0]:
Disable.
[1]:
Enable.
9.2.10 RC OSC Register IV (Address: 0x809h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
R
RCOT2
RCOT1
RCOT0
WCKSEL1 WCKSEL0
MVS1
RCOC9
0
MVS0
RCOC
0
NCAL
ENCAL
0
RC OSC IV
Reset
NUMLH11 NUMLH10
NUMLH9
— — —
NUMLH8
0
—
0
RCOT[2:0]: RCOSC current select for RC oscillator calibration.
WSEL [1:0]: Clock select for internal RC oscillator Calibration
[00]
: 16 MHz
[01]
: 8 MHz
[10]
: 4 MHz
[11]
: 2MHz
ENCAL: WOR calibration enable.
[0]:
Disable
[1]:
Enable.
RCOC [9:0]: WOR Calibration value.
NUMLH[11:0]: WOR calibration latch number.
9.2.11 RC OSC Register V (Address: 0x80Ah)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
R
MRCT9
NUMLH7
0
MRCT8
NUM
H6
0
—
NUMLH5
—
—
NUMLH4
—
—
NUMLH3
—
TMRE
NUMLH2
—
MAN
NUMLH1
0
MCALS
NUMLH0
0
RC OSC V
Reset
MRCT[9:0]: Manual RC-OSC calibr
value setting.
MAN: Enable Manual RC-OSC Cali
n.
[0]
: Auto
[1]:
Manual.
TMRE: RC-oscillator e
able.
[0]:
Disable.
[1]:
Enable
MCALS: Enable
onti
uous RC-OSC Calibration.
[0]:
Continuou
mo
e.
[1]:
Single mode.
NUMLH[
1:0]: RC-OSC calibration latch number.
9.2.12 RC OSC Register VI (Address: 0x80Bh)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
R
MRCT7
RCOC7
0
MRCT6
RCOC6
0
MRCT5
RCOC5
0
MRCT4
RCOC4
0
MRCT3
RCOC3
0
MRCT2
RCOC2
0
MRCT1
RCOC1
0
MRCT0
RCOC0
0
RC OSC VI
Reset
MRCT [9:0]: Manual RC-OSC calibration value setting.
RCOC [9:0]: RC-OSC calibration value.
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2.4GHz FSK/GFSK SoC
9.2.13 RC
OSC Register VII (Address: 0x80Ch)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
—
—
—
—
TGNUM11 TGNUM10
TGNUM9
TGNUM8
0
RCOSC7
Reset
—
—
—
—
0
0
0
TGNUM[11:0]: Target Number for RC OSC Calibration.
9.2.14 RC
OSC Register VIII (Address: 0x80Dh)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
TGNUM7
0
TGNUM6
0
TGNUM5
0
TGNUM4
0
TGNUM3
0
TGNUM2
0
TGNU
0
TGNUM0
0
RCOSC8
Reset
TGNUM[11:0]: Target Number for RC OSC Calibration.
9.2.15 CKO Pin Control Register (Address: 0x80Eh)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WAKEBBI
CKO Pin Control
Reset
W
ECKOE
1
CKOS3
0
CKOS2
1
CKOS1
1
CKOS0
CKOI
0
INTT1IE
—
E
—
ECKOE: External Clock Output Enable for CKOS [3:0]= [0100] ~ [0111].
[0]:
Disable.
[1]:
Enable.
CKOS[3:0]: CKO pin output select.
[0000]:
DCK (TX data clock).
[0001]:
RCK (RX recovery clock).
[0010]:
FPF (FIFO pointer flag).
[0011]:
EOP, EOVBC, EOFBC, EOADC, EOVCC, OKADC,
C_OK (Internal usage only).
[0100]:
External clock output= F
SYCK
.
[0101]:
External clock output / 2= F
SYCK
/ 2.
[0110]:
External clock output / 4= F
SYCK
/ 4.
[0111]:
External clock output / 8= F
SYCK
/ 8.
[1000]:
WCK.(4Khz)
[1001]:
PF8M(8MHz)
[1010]:
TMRCK(32Khz)
[1011]:
SYCK(8Mhz)
[1100]:
TMRCK_OVF(Timer c
ock)
CKOI: CKO pin output signal invert.
[0]:
Non-inverted outpu
[1]:
Inverted output.
WAKEBBIE: Wa
BB interrupt enable.
[0]:
Disable.
[1]:
Enable.
INTT1IE: ARCWTR interrupt enable.
[0]:
Disa
]:
Enable.
9.2.16 GIO1 Pin Control Register I (Address: 0x80Fh)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GPIO1 Pin I
Reset
W
VGC1
0
VGC0
0
GIO1S3
0
GIO1S2
0
GIO1S1
0
GIO1S0
0
GIO1I
0
—
—
GIO1S [3:0]: GIO1 pin function select.
GIO1S [3:0]
[0000]
TX state
RX state
WTR (Wait until TX or RX finished)
[0001]
EOAC (end of access code)
TMEO or TMDEO (TX
modulation enable)
FSYNC (frame sync)
CD (carrier detect)
[0010]
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2.4GHz FSK/GFSK SoC
[0011]
[0100]
[0101]
[0110]
[0111]
[1000]
[1001]
[1010]
[1011]
[1100]
[1101]
[1110]
[1111]
Preamble Detect Output (PMDO)
MCU wakeup signal (TWWS)
In phase demodulator input (DMII)
Reserved
TRXD In/Out (Direct mode)
RXD (Direct mode)
TXD (Direct mode)
In phase demodulator external input (EXDI0)
External FSYNC input in RX direct mode
INC
PDN_RX
INT5
Reserved
GIO1I: GIO1 pin output signal invert.
[0]:
Non-inverted output.
[1]:
Inverted output.
9.2.17 GIO2 Pin Control Register II (Address: 0x810h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WWS_AC
GIO2 Pin Control II
Reset
W
HBW
0
GIO2S3
0
GIO2S2
1
G
0
GIO2S0
0
GIO2I
0
—
—
8
—
WWS_AC8: See 9.2.8
HBW: IF bandwidth setting.
BWS HBW IF(Hz)
BW
1
1
0
0
1
0
1
0
2000 1200
2000 2400
1000 1200
1000 1200
GIO2S [3:0]: GIO2 pin function se
GIO2S
[0000]
TX state
ARCWTR (Wai
until TX or RX finished)
RX state
[0001]
EOAC (end of
ccess code)
TMEO or TMDEO(TX
modulati
n ena
le)
FSYNC (frame sync)
[0010]
CD (carrier detect)
[0011]
[0100]
[0101]
[0110]
[011
[1000
[1001]
[1010]
[1011]
[1100]
[1101]
[1110]
[1111]
Preamble Detect Output (PMDO)
M
wa
eup signal (TWWS)
Quadr
ture phase demodulator input (DMIQ)
es
ved
TRXD In/Out (Direct mode)
RXD (Direct mode)
TXD (Direct mode)
Quadrature phase demodulator external input (EXDI1)
External FSYNC input in RX direct mode
DEC
PDN_TX
Reserved
Reserved
GIO2I: GIO2 pin output signal invert.
[0]:
Non-inverted output.
[1]:
Inverted output.
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2.4GHz FSK/GFSK SoC
9.2.18 Clock Register (Address: 0x811h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Clock
Reset
R/W
GRC3
1
GRC2
1
GRC1
1
GRC0
1
CSC
0
CGS
1
XS
1
IDREV
0
GRC [3:0]: Clock generation reference counter.
GRC is used to get 2 MHz Clock Generator Reference (F
CGR
) for internal usage.
Clock generation reference = F
CSCK
/ (GRC+1). Maximum divide ratio is 16.
F
CSCK
is A8105
’
s master clock.
IDREV: ID reverse enable.
[0]:
Disable.
[1]:
Enable.
CSC: system clock F
SYCK
divider select.
[0]:
F
CSCK
.
[1]:
F
CSCK
/ 2.
CGS: Clock generator enable.
[0]:
Disable.
[1]:
Enable. CGS shall be set to [1].
XS: Crystal oscillator select.
[0]:
Use external clock.
[1]:
Use external crystal.
Master clock frequency
BWS = 0
BWS = 1
CGS = 0
Crystal frequency
crystal frequency
CGS = 1
32 MHz
64 MH
9.2.19 Data Rate Register (Address: 0x812h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Data Rate
Reset
R/W
SDR7
0
SDR6
0
SDR5
0
SDR4
0
SDR3
0
SDR2
0
SDR1
0
SDR0
0
SDR [7:0]: Data rate division selection.
Data rate = F
CSCK
/ [32*(SDR [7:0]+1)].
9.2.20 PLL Register I (Address
3h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PLL I
R/W
CHN7
0
CHN6
0
CHN5
0
CHN4
0
CHN3
0
CHN2
0
CHN1
0
CHN0
0
Reset
CHN [7:0]: LO channel number select.
9.2.21 PLL
egi
ter II (Address: 0x814h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
DBL
DBL
0
RRC1
RRC1
0
RRC0
RRC0
0
CHR3
CHR3
0
CHR2
CHR2
1
CHR1
CHR1
1
CHR0
CHR0
1
IP8
BIP8
0
P
II
Reset
W
DBL: Crystal frequency doubler selection.
[0]:
Disable. F
XREF
= F
XTAL
[1]:
Enable. F
XREF
=2 * F
XTAL
.
.
RRC [1:0]: RF PLL reference counter setting.
CHR [3:0]: PLL channel step setting.
IP [8:0]: LO frequency integer part value.
IP [8:0] are from address (0x812h) and (0x813h),
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2.4GHz FSK/GFSK SoC
9.2.22 PLL Register III (Address: 0x815h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
R
BIP7
IP7
0
BIP6
IP6
1
BIP5
IP5
0
BIP4
IP4
0
BIP3
IP3
1
BIP2
IP2
0
BIP1
IP1
1
BIP0
IP0
1
PLL III
Reset
IP [8:0]: LO frequency integer part value.
IP [8:0] are from address (0x812h) and (0x813h),
BIP [8:0]: LO base frequency integer part setting.
BIP [8:0] are from address (0x812h) and (0x813h),
9.2.23 PLL Register IV (Address: 0x816h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
B
2
Bit 1
Bit 0
W
R
FP15
FP14
FP13
FP12
FP11
FP10
FP9
FP8
AC8/FP8
0
PLL IV
Reset
–/FP15 AC14/FP14
AC13/FP13 AC12/P12 AC11/
FP1
AC10/FP10 AC9/FP9
0
0
0
0
0
0
FP [15:0]: LO base frequency fractional part setting.
FP [15:0] are from address (0x816h) and (0x817h),
AC [14:0] (Read): Auto Frequency compensation value (if AFC (0
81Ah) =1).
FP [15:0] (Read): LO frequency fractional part setting.
9.2.24 PLL Register V (Address: 0x817h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
R
FP7
AC7/FP7
0
FP
AC6/F
6
0
FP5
AC5/FP5
0
FP4
AC4/FP4
0
FP3
AC3/FP3
0
FP2
AC2/FP2
0
FP1
AC1/FP1
1
FP0
AC0/FP0
1
PLL V
Reset
FP [15:0]: LO base frequency frac
art setting.
FP [15:0] are from address (0x814h) a
0x815h),
AC [14:0] (Read): Auto Frequ
ncy compensation value (if AFC (0x81Ah) =1).
FP [15:0] (Read): LO fr
quency fractional part setting.
9.2.25 TX R
gister I (Address: 0x818h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
GDR
0
TMDE
1
TXDI
0
TME
1
FS
0
FDP2
1
FDP1
1
FDP0
0
Re
et
GDR: Gaussian Filter Over Sampling Rate Select.
[0]:
BT= 1.
[1]:
BT= 0.5
TMDE: TX Modulation Enable for VCO Modulation.
[0]:
Disable.
[1]:
Enable.
TXDI: TX data invert. Recommend TXDI = [0].
[0]:
Non-invert.
[1]:
Invert.
TME: TX modulation enable.
[0]:
Disable.
[1]:
Enable.
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2.4GHz FSK/GFSK SoC
FS: Filter select.
The filter shape is gaussian filter.
[0]:
disable.
[1]:
enable.
FDP [2:0]: Frequency deviation power setting. Refer to control register (15h).
9.2.26 TX Register II (Address: 0x819h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TX II
W
FD7
0
FD6
0
FD5
1
FD4
0
FD3
1
FD2
1
FD1
1
FD0
1
Reset
FD [7:0]: Frequency deviation setting.
FDEV
= F
PFD
/2**16*FD* 2**(FDP-1).
Where F
PFD
= F
XTAL
* (DBL+1) / (RRC [1:0]+1), PLL comparison frequency.
9.2.27 Delay Register I (Address: 0x81Ah)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Delay
Reset
W
DPR2
0
DPR1
0
DPR0
0
TDL1
1
TD
PDL2
0
PDL1
1
PDL0
0
DPR [2:0]: Delay scaling setting.
Recommend DPR = [000].
TDL [1:0]: Delay for TX data out after PDN_TX enable.
Delay= 20 * (TDL [1:0]+1)*(DPR [2:0]+1) + (TX_5DLY [4:0]+1) us.
PDL [2:0]: Delay for TX settling.
Delay= 20 * (PDL [2:0]+1)*(DPR [2:0]+1) us.
9.2.28 Delay Register II (Address: 0x81Bh)
Name
R/W
Bit 7
Bit
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Delay
Reset
W
WSEL2
0
EL
WSEL0
0
AGC_D1
0
AGC_D0
0
RS_DLY2 RS_DLY1 RS_DLY0
0
0
1
WSEL[2:0]: XTAL settling delay se
200us ~ 2.5ms). Recommend WSEL = [010].
[000]:
200us.
[001]:
400us.
[010]:
600us.
[011]:
800us.
[100]:
1ms.
[101]:
1.5ms.
[
10]:
ms.
[111]:
2.5ms.
AGC_D [1:0]: RSSI cal
bration switching time (10us ~ 40us
)
. Recommend AGC_D = [00].
[00]:
10us.
[01]:
20us
[10]:
30us.
[11]:
40us.
RS_DLY [2:0]
RS
I measurement delay (10us ~ 80us
).
Recommend RS_DLY = [001].
[000]:
10us.
[0
1]:
0us.
[010]:
30us.
[011]:
40us.
[100]:
50
.
[101]:
60us.
[110]:
70us.
[111]:
80us.
9.2.29 RX Register (Address: 0x81Ch)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RX
W
MSCRC
0
RXSM1
1
RXSM0
0
AFC
0
RXDI
0
DMG
0
BWS
1
ULS
0
Reset
MSCRC: Mask CRC (CRC Data Filtering Enable).
[0]:
Disable.
[1]:
Enable.
RXSM [1:0]: Reserved for internal usage onl
y
.
S
hall be set to [10].
AFC: Auto Frequency compensation select.
[0]:
Manual compensation.
[1]:
Auto compensation.
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2.4GHz FSK/GFSK SoC
RXDI: RX data output invert. Recommend RXDI = [0].
[0]:
Non-inverted output.
[1]:
Inverted output.
DMG: Reserved for internal usage onl
y
.
S
hall be set to [0].
BWS: IF Bandwidth selection.
HBW: IF bandwidth setting.
BWS HBW IF(Hz)
BW
1
1
0
0
1
0
1
0
2000 1200
2000 2400
1000 1200
1000 1200
ULS: RX Up/Low side band select.
[0]:
Up side band,
[1]:
Low side band.
9.2.30 RX Gain Register I (Address: 0x81Dh)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
B
Bit 2
Bit 1
Bit 0
W
R
AGCE
ADC8
0
MIC
MICR
1
IGC1
IGCR1
1
IGC0
IGCR
MGC1
MGCR1
1
MGC0
MGCR0
1
LGC1
LGCR1
1
LGC0
LGCR0
1
RX Gain I
Reset
AGCE: Auto Front end Gain Control Select.
[0]:
Disable.
[1]:
Enable.
IGC [1:0]: IFA Attenuation Select.
[00]:
0dB.
[01]:
6dB.
[10]:
12dB.
[11]:
18dB.
MGC [1:0]: Mixer Gain Attenuation select.
[00]:
0dB.
[01]:
6dB.
[10]:
12dB.
[11]:
18dB.
LGC [1:0]: LNA Gain Attenuation sel
ct.
[00]:
6dB.
[01]:
12dB.
[10]:
18dB.
[1
B.
9.2.31 RX Gain Register II (Address: 0x81Eh)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
PKIS1
PKIS0
PKT1
PKT0
DCH1
DCH0
RSAGC1
RSAGC0
RX Gain II
Reset
—
0
—
0
—
0
—
1
—
0
—
0
VT1
0
VT0
0
PKIS[1:0]: AG
P
k Detect Current Select. Recommend PKIS[1:0[ = [00].
PKT[1:0]
O Peak Detect Current Select. Recommend PKT [1:0] = [01].
DCH [1:0]: AGC Hold setting.
[00]: Hold by Preamble OK.
[01]:
Hold by SYNC.
[10]:
No Hold.
[11]:
No Hold.
VT[1:0]: AGC comparator output.
RH [7:0]: Reserved for internal usage onl
y
.
RSAGC [1:0]: AGC clock select.
[00]:
IF/4
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2.4GHz FSK/GFSK SoC
[01]:
IF/2
[10]:
IF
[11]:
2*IF
Where IF is 1Mhz for BWS=0, and 2Mhz for BWS=1.
9.2.32 RX Gain Register III (Address: 0x81Fh)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
R
IFPK
RH7
0
VRSEL
RH6
0
MS
RH5
0
MSCL4
RH4
0
MSCL3
RH3
0
MSCL2
RH2
0
MSCL1
RH1
0
MSCL0
RH0
0
RX Gain III
Reset
IFPK: AGC Amplifier Current Select
.
Recommend IFPK = [0].
VRSEL: ADC reading select.
[0]: Normal ADC. [1]: RSSI ADC (with AGC turn on).
MS: AGC Manual scale select.
[0]:
RL-RH(Auto).
[1]:
MSCL(Manual).
MSCL[4:0]: AGC Manual Scale setting.
RH [7:0]: RSSI Calibration High Threshold.
9.2.33 RX Gain Register IV (Address: 0x820h)
Name
R/W
Bit 7
Bit 6
Bit 5
it 4
Bit 3
Bit 2
Bit 1
Bit 0
W
R
MXD
RL7
0
CSS
RL6
0
HPLS
RL5
1
MHC1
RL4
0
MHC0
RL3
1
LHC1
RL2
1
LHC0
RL1
1
XADSP
RL0
0
RX Gain III
Reset
MXD: Reserved for internal usage only. Shall be s
t to [0].
CSS: RX demodulation carrier detect select.
[0]:
Deselect.
[1]:
select.
HPLS: High Power LNA Gain Sele
ommend HPLS = [0].
[0]:
LGC is set to 6dB when in TX Mo
]:
LGC is set to LGM[1:0].
MHC [1:0]: Reserved for inte
nal u
age onl
y
.
S
hall be set to [10].
LHC [1:0]: Reserved for inte
nal usage onl
y
.
S
hall be set to [10].
XADS: ADC inpu
sign
l select.
[0]:
Convert intern
l temperature or RSS signal.
[1]:
Convert external voltage,
RL [7:0]: RSSI Calibration Low Threshold value.
9.2.34 RSSI Threshold Register (Address: 0x821h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
R
RTH7
ADC7
0
RTH6
ADC6
0
RTH5
ADC5
0
RTH4
ADC4
0
RTH3
ADC3
0
RTH2
ADC2
0
RTH1
ADC1
0
RTH0
ADC0
0
RSSI Threshold
Reset
RTH [7:0]: Carrier detect threshold.
ADC [8:0]: ADC output value of temperature, RSSI or external voltage measurement (read only).
ADC [8:0] are located at address 0x81D and 0x821h.
For normal ADC measurement with VRSEL=0 (in 0x81Fh), which include external voltage, Temp and RSSI with AGC off
measurement, ADC [8] is zero. ADC input voltage= 1.2 * ADC [8:0] / 256 V.
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9.2.35 ADC Control Register (Address: 0x822h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADC Control
Reset
W
RSM1
0
RSM0
1
ERSS
0
FSARS
1
SYNCS
0
XADS
0
RSS
1
CDM
1
RSM [1:0]: RSSI margin = RTH
–
RTL. Recommend RSM = [11].
[00]:
5.
[01]:
10.
[10]:
15.
[11]:
20.
ERSS: end enable for RSSI measurement
[0]:
RSSI measurement continues until leave off RX mode.
[1]:
RSSI measurement will end when carrier detected and ID code word received.
FSARS: ADC clock select. Recommend FSARS = [0].
[0]:
2MHz.
[1]:
4MHz.
SYNCS: Sync word detect select.
[1]:
sync word.
[0]:
preamble
XADS: ADC input signal select.
[0]:
Convert internal temperature or RSS signal.
[1]:
Convert external volta
e,
RSS: Temperature/RSSI measurement select.
[0]:
Temperature measurement.
[1]:
RSSI or carrier-detect measuremen
CDM: RSSI measurement mode.
[0]:
Single mode.
[1]:
Continuous mode.
9.2.36 Code Register I (Address: 0x823h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Code I
Reset
W
XDS
0
MCS
0
WHTS
0
FECS
0
CRCS
0
PML2
0
PML1
1
PML0
1
XDS: VCO Modulation Data Samplin
Clock selection.
[0]:
8x over-sampling Clock.
[1]:
X
Clock.
MCS: Manchester Code Ena
le.
[0]:
Disable.
[1]:
Enable.
WHTS: Data whitening (Data Encryption) select.
[0]:
Disable.
[1]:
En
ble.
FECS: FEC sele
.
[0]:
Disable.
[1]:
Enable.
CRCS: CRC sel
ct.
[0]:
Disa
1]:
Enable.
PML [2:0]: Preamble length select. Recommend PML= [11].
[000]:
1 byte.
[001]:
2 bytes.
[010]:
3 bytes.
[011]:
4 bytes.
[100]:
5byts.
[101]
: 6bytes.
[110]:
7bytes.
[111]:
8bytes
9.2.37 Code Register II (Address: 0x824h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Code II
Reset
W
DCL2
1
DCL1
1
DCL0
1
ETH2
0
ETH1
0
ETH0
1
PMD1
1
PMD0
1
DCL [2:0]: Demodulator DC estimation average mode. Refer to DCM (0x82Bh) for details.
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2.4GHz FSK/GFSK SoC
DCL [2]: payload average mode.
[0]:
128 bits average.
[1]:
256 bits average.
DCL [1]: For average and hold mode.
[0]:
32 bits average.
[1]:
64 bits average.
DCL [0]: Preamble detection delay. Count from preamble detected signal. Recommend DCL0 = [1].
[0]:
4 bits for DCL1=0, 8 bits for DCL1=1.
[1]:
8 bits for DCL1=0, 16 bits for DCL1=1.
ETH [2:0]: ID code error tolerance. Recommend ETH = [01].
[000]~[111]:
0~7 bit.
PMD [1:0]: Preamble pattern detection length. Recommend PMD = [10].
[00]:
0bit.
[01]:
4bits.
[10]:
8bits.
[11]:
16bits.
9.2.38 Code Register III (Address: 0x825h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
B
t 2
Bit 1
Bit 0
Code III
Reset
W
IDL
1
WS6
0
WS5
1
WS4
0
WS3
1
WS
0
WS1
1
WS0
0
IDL: ID code length select. Recommend IDL= [1].
[0]:
2 bytes.
[1]:
4 bytes.
WS [6:0]: Data Whitening seed setting (data encryption key).
9.2.39 IF Calibration Register I (Address: 0x826h)
Name
R/W
Bit 7
Bit 6
Bit 5
B
t 4
Bit 3
Bit 2
Bit 1
Bit 0
W
R
RNUM0_2 RNUM0_1 RNUM
MFBS
FBCF
0
MFB3
FB3
0
MFB2
FB2
1
MFB1
FB1
1
MFB0
FB0
0
IF Calibration I
Reset
—
1
—
0
—
0
RNUM0[2:0]: sync word clock recovery ma
ual setting.
MFBS: IF filter calibration value select.
co
mend MFBS = [0].
[0]:
Auto calibration value.
[1]:
Manua
libration value.
MFB [3:0]: IF filter manual calibrat
ue.
FBCF: IF filter auto calibrati
n flag
[0]:
Pass.
[1]:
Fail.
FB [3:0]: IF filter cal
bra
ion value.
MFBS= 0: Auto c
brat
n value (AFB),
MFBS= 1: Manual ca
bration value (MFB).
9.2.40 IF
libration Register II (Address: 0x827h)
Na
e
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
R
PWORS
TRT2
TRT1
TRT0
FCD4
1
MRCKS
FCD3
0
RNUM1_2 RNUM1_1
RNUM1_0
IF Calibration II
Reset
—
0
—
0
—
1
FCD2
0
FCD1
0
FCD0
0
PWORS: TX high power setting.
[0]:
Disable.
[1]:
Enable.
TRT [2:0]: TX Ramp down discharge current select. Recommand value=[000]
MRCKS: Preamble detect and sync detect manual setting. [1]: manual
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2.4GHz FSK/GFSK SoC
RNUM1[2:0]: sync word clock recovery manual setting.
FCD [4:0]: IF filter calibration deviation from goal.
9.2.41 VCO current Calibration Register (Address: 0x828h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
R
—
TWORF
0
PKS
—
VCCS
MVCS
FVCC
0
VCOC3
VCB3
1
VCOC2
VCB2
0
VCOC1
VCB1
0
VCOC0
VCB0
0
VCO current
Calibration
—
0
Reset
0
PKS: VCO Current Calibration Mode Select. Recommend PKS = [0].
VCCS: Reserved for internal usage onl
y
.
S
hall be set [0].
MVCS: VCO current calibration value select. Recommend MVCS = [0].
[0]:
Auto calibration value.
[1]:
Manual calibration value.
VCOC [3:0]: VCO current manual calibration value.
TWORF: TWOR interrupt flag.
FVCC: VCO current auto calibration flag.
[0]:
Pass.
[1]:
Fail.
VCB [3:0]: VCO current calibration value.
MVCS= 0: Auto calibration value (VCB).
MVCS= 1: Manual calibration value (VCOC).
9.2.42 VCO Single band Calibration Register I (Add
s: 0x829h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
R
DCD1
DCD0
DAGS
PDV
—
MVBS
VBCF
0
MVB2
VB2
1
MVB1
VB1
0
MVB0
VB0
0
VCO Single band
Calibration I
—
1
—
1
—
0
Reset
1
DCD [1:0]: VCO Deviation Calibra
a
y
.
R
ecommend DCD = [01].
Delay time = PDL (Delay Register I, 0
h)
×
(DDC + 1 ).
DAGS: DAG Calibration Valu
Sel
ct. Recommend DAGS = [0].
[0]:
Auto calibration value.
[1]:
Manual calibration value.
PDV: Reserved for in
ernal usage only. Shall be set [0].
MVBS: VCO
ank cal
bration value select. Recommend MVBS = [0].
[0]:
Auto calibr
tion
alue.
[1]:
Manual calibration value.
MVB [2:0
CO band manual calibration value.
VBCF: VCO band auto calibration flag.
[0]:
Pass.
[1]:
Fail.
VB [2:0]: VCO bank calibration value.
MVBS= 0: Auto calibration value (AVB).
MVBS= 1: Manual calibration value (MVB).
9.2.43 VCO Single band Calibration Register II (Address: 0x82Ah)
Name R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
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2.4GHz FSK/GFSK SoC
VCO Single band
Calibration II
W
DAMV1
1
DAMV0
0
VTH2
1
VTH1
1
VTH0
1
VTL2
0
VTL1
1
VTL0
1
Reset
DMV [1:0]: Demodulator D/A Voltage Range Select. Recommend DMV = [10].
[00]:
1/32*1.2.
[01]:
1/16*1.2.
[10]:
1/8*1.2.
[11]:
1/4*1.2.
VTH [2:0]: RF AGC upper threshold level setting
[000]:
VDD_A
–
0.6V.
[001]:
VDD_A
–
0.7V.
[010]:
VDD_A
–
0.8V.
[011]:
VDD_A
–
0.9V
[100]:
VDD_A
–
1.0V.
[101]:
VDD_A
–
1.1V.
[110]:
VDD_A
–
1.2V.
[111]:
VDD_A
–
1.3V
VDD_A is on chip analog regulator output voltage
VTL [2:0]: RX AGC lower threshold level setting
[000]:
0.1V.
[001]:
0.2V.
[010]:
0.3V.
[011]:
0.4V.
[100]:
0.5V.
[101]:
0.6V.
[110]:
0.7V.
[111]:
0.8V
9.2.44 Battery detect Register (Address: 0x82Bh)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
R
RGS
RGV1
RGV1
0
RGV0
RGV0
0
PACTL
BDF
0
BVT2
BV
BVT1
BVT1
1
BVT0
BVT0
1
BDS
BDS
0
Battery detect
Reset
—
0
RGS: VDD_D voltage setting in Sleep mode.
[0]:
1.8V.
[1]:
1.6V.
RGV [1:0]: VDD_D and VDD_A voltage setting in non-Sleep
ode
ecommend RGV = [11].
[00]:
1.9V.
[01]: 1
.8V.
[10]:
1.7V.
[11]:
1.6V.
PACTL: Reserved for internal usage only. Shall be set
BVT [2:0]: Battery voltage detect threshold.
[000]: 1
.8V.
[001]: 1
.9V.
[010]:
2.0V.
[011]:
2.1V.
[100]:
2.2V.
[101]:
2.3V.
[110]:
2.4V.
[111]:
2
V.
BDS: Battery detect enable.
[0]:
Disable.
[1]:
Enable. It will be clea
ter battery detection done.
BDF: Battery detection flag.
[0]:
Battery voltage less than t
reshold.
[1]:
Battery voltage greater than threshold.
Refer to chapter 19 for details.
9.2.45 TX test Reg
ster (Address: 0x82Ch)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TX test
Reset
W
IFBC1
0
IFBC0
0
TXCS
0
PAC1
1
PAC0
0
TBG2
1
TBG1
1
TBG0
1
RMP [1:0]
PA ramp up timing scale.
Delay scales 2^(RMP [1:0])
TXCS: TX Current Setting.
PAC [1:0]: PA Current Setting.
TBG [2:0]: TX Buffer Setting.
9.2.46 Rx DEM test Register I (Address: 0x82Dh)
Name R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
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2.4GHz FSK/GFSK SoC
Rx DEM test I
Reset
W
DMT
0
DCM1
1
DCM0
1
MLP1
0
MLP0
0
SLF2
1
SLF1
0
SLF0
0
DM
T
:
R
eserved for internal usage onl
y
.
S
hall be set to [0].
DCM [1:0]: Demodulator DC estimation mode.
[00]:
Fix mode (For testing only). DC level is set by DCV [7:0].
[01]:
Preamble hold mode. DC level is preamble average value.
[10]:
Average and hold mode. DC level is the average value hold about 8 bit data rate later after preamble is detected.
[11]:
Payload average mode (For internal usage). DC level is payload data average.
MLP [1:0]: Reserved for internal usage onl
y
.
S
hall be set to [000].
SLF [2:0]: Reserved for internal usage onl
y
.
S
hall be set to [111].
9.2.47 Rx DEM test Register II (Address: 0x82Eh)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
B
2
Bit 1
Bit 0
Rx DEM test II
Reset
W
DCV7
1
DCV6
0
DCV5
0
DCV4
0
DCV3
0
DCV2
0
DCV1
0
DCV0
0
DCV [7:0]: Demodulator fix mode DC value. Recommend DCV = [0x80].
9.2.48 Charge Pump Current Register (Address: 0x82Fh)
Name
R/W
Bit 7
Bit 6
Bit 5
B
4
Bit 3
Bit 2
Bit 1
Bit 0
Charge Pump Current
Reset
W
CPM3
1
CPM2
1
CPM1
1
PM
1
CPT3
1
CPT2
1
CPT1
1
CPT0
1
CPM [3:0]: Charge Pump Current Setting for VM loop. R
mend CPM = [1111].
Charge pump current = (CPM + 1) / 16 mA.
CPT [3:0]: Charge Pump Current Setting for VT loop. Recommend CPT = [1111].
Charge pump current = (CPT + 1) / 16 mA.
9.2.49 Crystal test Register (Ad
s: 0x830h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Crystal test
Reset
W
PRS
0
QDS
0
QLIM
0
DBD
0
XCC1
0
XCC0
1
XCP1
0
XCP0
1
PRS: Limiter amplifier
isch
rge manual select. Recommend PRS =[0].
QDS: VDD_A Qu
Dis
harge Select.
[0]:
Disable.
:
E
ab
e.
QLIM: q
charge select for IF limiter amp.
[0]:
disab
[1]:
enable (QLIM fall down delay 10us)
DBD: Reserved for internal usage onl
y
.
S
hall be set to [0].
XCC[1:0]: Crystal current setting. Shall be set to [01].
XCP[1:0]: Crystal regulating couple setting. Shall be set to [01].
9.2.50 PLL test Register (Address: 0x831h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PLL test
Reset
W
MDEN
0
PMPE
1
PRIC1
1
PRIC0
0
PRRC1
1
PRRC0
0
SDPW
0
NSDO
0
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2.4GHz FSK/GFSK SoC
MDEN : Use for Manual VCO Calibration. Shall be set to [0].
PMPE: Reserved for internal usage only. Shall be set to [1].
PRIC[1:0]: Reserved for internal usage only. Shall be set to [01].
PRRC[1:0]: Reserved for internal usage only. Shall be set to [01].
SDPW: Reserved for internal usage only. Shall be set to [0].
NSDO: Reserved for internal usage only. Shall be set to [1].
9.2.51 VCO test Register I (Address: 0x832h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VCO test I
Reset
W
DEVGD2
0
DEVGD1
0
DEVGD0
0
TLB1
1
TLB0
1
RLB1
RLB0
1
MGS
0
DEVGD [2:0]: Sigma Delta Modulator Data Delay Setting. Recommend DEVGD = [000].
TLB [1:0]: Reserved for internal usage onl
y
.
S
hall be set to [11].
RLB [1:0]: Reserved for internal usage onl
y
.
S
hall be set to [00].
MGS: IGC Manual setting select.
[0]:
Auto.
[1]:
Manual.
9.2.52 VCO test Register II (Address: 0x833h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VCO test II
Reset
W
CHD3
0
CHD2
1
CHD1
0
CHD0
1
RFT3
0
RFT2
0
RFT1
0
RFT0
0
CHD [3:0]: Channel Frequency Offset for De
i
tion Calibration.
Offset channel number = +/- (CHD + 1).
RFT [3:0]: RF analog pin configur
r testing. Recommend RFT= [0000].
9.2.53 IFAT Register (Add
ess: 0x834h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VCO test II
Reset
W
MPDT5
1
MPDT4
0
MPDT3
0
MPDT2
0
MPDT1
0
MPDT0
0
—
—
LIMC
1
MPDT[5:0]: TX ramp up/down scale select.
LIMC: Reserved for internal usage onl
y
.
S
hall be set to [1].
9.2.54 RF
Test Register I (Address: 0x835h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RFT1
Reset
W
ASMV2
0
ASMV1
0
ASMV0
0
SDMS
1
OLM
0
CPCS
1
CPH
1
CPS
1
AMSV [2:0]: TX Ramp up/Ramp down Timing Select.
[000]:
4us,
[001]:
8us.
[010]:
12us.
[011]:
16us.
[100]:
20us,
[101]:
24us.
[110]:
28us.
[111]:
32us.
SDMS: Reserved for internal usage onl
y
.
S
hall be set to [1].
OLM : Open Loop Modulation Enable. Shall be set to [0].
[0]:
Disable.
[1]:
Enable.
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2.4GHz FSK/GFSK SoC
CPCS: Charge Pump Current Select. Shall be set to [0].
[0]:
Use CPM for TX, CPT for RX.
[1]:
Use CPTX for TX, CPRX for RX.
CPH: Charge Pump High Current. Shall be set to [0].
[0]:
Normal.
[1]:
High.
CPCS: Charge Pump Current Select. Shall be set to [0].
[0]:
Use CPM for TX, CPT for RX.
[1]:
Use CPTX for TX, CPRX for RX.
9.2.55 RFT Test Register II (Address: 0x836h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
R
—
—
—
CRS3
CRSR3
0
CRS2
CRSR2
1
CRS1
CRSR1
0
CRS0
CRSR0
0
SRS2
SR
R2
1
SRS1
SRSR1
0
SRS0
SRSR0
0
RFT2
Reset
CRS [2:0]: RSSI voltage offset fine trim setting.
SRS [2:0]: RSSI voltage curve slope fine time setting.
9.2.56 RFT Test Register III (Address: 0x837h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit
Bit 3
Bit 2
Bit 1
Bit 0
W
R
—
—
0
STMP
STM5
STMR
1
TM4
STMR4
0
STM3
STMR3
0
STM2
STMR2
0
STM1
STMR1
0
STM0
STMR0
0
RFT3
Reset
—
0
STMP: Temp voltage ADC reading select.
[0]:
1 scale / degree C.
[1]:
2 scale/degree C.
STM [5:0]: ADC voltage fine trim setting.
9.2.57 RFT Test Register IV (A
: 0x838h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
R
—
—
—
DVI1
DVI0
FBG4
FBGR4
1
FBG3
FBGR3
0
FBG2
FBGR2
0
FBG1
FBGR1
0
FBG0
FBGR0
0
RFT4
Reset
—
0
—
0
DVI[1:0]: Reserv
d for internal usage
FBG[4:0]: Ba
dga
voltage SPI fine trim setting.
9.2.58 R
est Register V (Address: 0x839h)
Na
e
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
R
FGC1
FGCR1
1
FGC0
FGCR0
1
CTR5
CTRR5
1
CTR4
CTRR4
0
CTR3
CTRR3
0
CTR2
CTRR2
0
CTR1
CTRR1
0
CTR0
CTRR0
0
RFT5
Reset
FGC[1:0]: BPF fine gain control.
CTR [5:0]: ADC voltage SPI fine trim setting.
9.2.59 Channel Index Register (Address: 0x83Ah)
Name R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
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2.4GHz FSK/GFSK SoC
Channel Index
Reset
W
—
—
—
0
CHIDX5
1
CHIDX4
0
CHIDX3
0
CHIDX2
1
CHIDX1
0
CHIDX0
1
CHIDX[5:0]: Whitening seed setting for BLE mode(BLE_ON=1).
9.2.60 CRC Register 1 (Address: 0x83Bh)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CRC1
Reset
W
CRCINIT23 CRCINIT22 CRCINIT21 CRCINIT20 CRCINIT19 CRCINIT18 CRCINIT17 CRCINIT16
0
1
0
1
0
1
0
1
CRCINIT[23:0]: CRC initial value for TX CRC-24bits encoder.
9.2.61 CRC Register 2 (Address: 0x83Ch)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CRC2
Reset
W
CRCINIT15 CRCINIT14 CRCINIT13 CRCINIT12 CRCINIT11 CR
IT1
CRCINIT9 CRCINIT8
0
1
0
1
0
1
0
1
9.2.62 CRC Register 3 (Address: 0x83Dh)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit
Bit 2
Bit 1
Bit 0
CRC3
Reset
W
CRCINIT7 CRCINIT6 CRCINIT5 CRCINI
4 CRC
NIT3 CRCINIT2 CRCINIT1 CRCINIT0
0
1
0
1
0
1
0
1
9.2.63 CRC Register 4 (Address: 0x83Eh)
Name
R/W
Bit 7
Bit 6
Bit
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CRC4
Reset
W
CRCINR23 CRCINR22
RCINR21 CRCINR20 CRCINR19 CRCINR18 CRCINR17 CRCINR16
0
1
0
1
0
1
0
1
CRCINR[23:0]: CRC initial value for RX CRC
24bits decoder.
9.2.64 CRC Register 5 (Address: 0x83Fh)
Name
R/W
Bit 7
it 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CRC5
Reset
W
C
CINR15 CRCINR14 CRCINR13 CRCINR12 CRCINR11 CRCINR10
CRCINR9 CRCINR8
0
1
0
1
0
1
0
1
9.2.65 CRC Regis
er 6 (Address: 0x840h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CRC6
Reset
W
CRCINR7 CRCINIR6 CRCINIR5 CRCINIR4 CRCINIR3 CRCINIR2 CRCINIR1 CRCINIR0
0
1
0
1
0
1
0
1
9.2.66 VCO Single band Calibration Register I (Address: 0x841h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
R
DAGM7
ADAG7
1
DAGM6
ADAG6
0
DAGM5
ADAG5
0
DAGM4
ADAG4
0
DAGM3
ADAG3
0
DAGM2
ADAG2
0
DAGM1
ADAG1
0
DAGM0
ADAG0
0
VCO Single band
Calibration III
Reset
DAGM [7:0]: DAG Manual Setting Value. Recommend DAGM = [0x80].
ADAG [7:0]: Auto DAG Calibration Value.
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2.4GHz FSK/GFSK SoC
9.2.67 VCO deviation Calibration Register I (Address: 0x842h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
R
DEVS3
DEVA7
0
DEVS2
DEVA6
1
DEVS1
DEVA5
1
DEVS0
DEVA4
1
DAMR_M
DEVA3
VMTE_M
DEVA2
VMS_M
DEVA1
MSEL
DEVA0
VCO Deviation I
Reset
0
0
0
0
DEVS [3:0]: Deviation Output Scaling. Recommend DEVS = [0011].
DAMR_M: DAMR Manual Enable. Recommend DAMR_M = [0].
[0]:
Disable.
[1]:
Enable.
VMTE_M: VMT Manual Enable. Recommend VMTE_M = [0].
[0]:
Disable.
[1]:
Enable.
VMS_M: VM Manual Enable. Recommend VMS_M = [0].
[0]:
Disable.
[1]:
Enable.
MSEL: VMS, VMTE and DAMR control select. Recommend MSEL = [0].
[0]:
Auto control.
[1]:
Manual control.
DEVA [7:0]: Deviation Output Value.
MVDS (0x841h)= 0: Auto calibration value ((DEVC / 8
)
×
(DEVS + 1)),
MVDS (0x841h)= 1: Manual calibration value (DEVM [6:0]).
9.2.68 VCO deviation Calibration Register II (Address: 0x843h)
Name
R/W
Bit 7
Bit 6
Bit 5
it 4
Bit 3
Bit 2
Bit 1
Bit 0
W
R
MVDS
ADEV7
0
DEVM6
ADEV6
0
DEVM
ADE
1
DEVM4
DEV4
0
DEVM3
ADEV3
1
DEVM2
ADEV2
0
DEVM1
ADEV1
0
DEVM0
ADEV0
0
VCO Deviation II
Reset
MVDS: VCO Deviation Calibration Select. Recommend MVDS = [0].
[0]:
Auto calibration value.
[1]:
Manual calibra
n value.
DEVM [6:0]: VCO Deviation Manual Calib
atio
Value.
ADEVC [7:0]: VCO Deviation Auto
tion Value.
9.2.69 VCO deviation Cal
bration Register III (Address: 0x844h)
Name
R
W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VCO Deviation III
Reset
W
R
VMG7
1
VMG6
0
VMG5
0
VMG4
0
VMG3
0
VMG2
0
VMG1
0
VMG0
0
VMG [7:0]: V
Ce
ter Value for Deviation Calibration. Recommend VMG [7:0] = [0x80].
9.2.70 A
Control Register (Address: 0x845h)
Na
e
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADC
W
AVSEL1
1
AVSEL0
0
MVSEL1
1
MVSEL0
0
RADC
0
FPS2
0
FPS1
0
FPS0
0
Reset
AVSEL [1:0]: ADC average times (for Carrier / temeperature sensor / external ADC). Recommend AVSEL = [10].
[00]:
No average.
[01]:
Average 2 times.
[10]:
Average 4 times.
[11]:
Average 8 times.
MVSEL [1:0]: ADC average times (for VCO calibration and RSSI ). Recommend MVSEL = [01].
[00]:
Average 8 times.
[01]:
Average 16 times.
[10]:
Average 32 times.
[11]:
Average 64 times.
RADC: ADC read out average mode.
[0]:
1, 2, 4, 8 average mode. The average number is according to the setting of AVSEL in RX Gain Register (IV).
Sep., 2014, Version 0.6 (Preliminary)
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2.4GHz FSK/GFSK SoC
[1]:
8, 16, 32, 64 average mode. The average number is according to the setting of MVSEL in RX Gain Register (IV)
FPS[2:0]
:
Gaussian filter BT setting.
GDR=0.
FPS[2:0]
BT
7
1.4
6
1.3
5
1.2
4
3
2
1
0
1.1 0.75 0.7 0.65 0.6
GDR=1.
FPS[2:0]
BT
7
6
5
4
3
X
2
X
1
X
0
X
0.7 0.65 0.6 0.55
9.2.71 WOT Register (Address: 0x846h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bi
1
Bit 0
WOT
W
—
0
SPSS
0
WMODE
0
WN1
0
WN0
0
Reset
—
—
—
.
SPSS: Mode back select in WOT mode.
[0]:
Standby mode.
[1]:
PLL mode.
WMODE: Wakeup mode select.
[0]:
WOR
[1]:
WOT
WN[1:0]: WOT Wake up times.
9.2.72 Channel Group Register I (Address: 0x847h)
Name
R/W
Bit 7
Bit 6
Bit 5
it 4
Bit 3
Bit 2
Bit 1
Bit 0
CHGL
Reset
R/W
CHGL7
0
CHGL6
0
CHG
1
CHGL4
0
CHGL3
1
CHGL2
0
CHGL1
0
CHGL0
0
CHGL [7:0]: PLL channel group low boundary se
ing.
9.2.73 Channel Group Register II (Addr
s: 0x848h)
Name
R/W
Bit 7
it 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CHGH
Reset
R/W
CHGH
0
HG
6
1
CHGH5
0
CHGH4
1
CHGH3
0
CHGH2
0
CHGH1
0
CHGH0
0
CHGH [7:0]: PLL channel gr
up high boundary setting.
PLL frequency is divided into 3 groups:
Channel
Group1
0 ~ CHGL-1
Group2
Group3
CHGL ~ CHGH-1
CHGH ~ 255
Note: Ea
h group needs its own VCO current, bank and deviation calibration. Use the same calibration value for the frequency
in the sam
roup.
9.2.74 Charge Pump Current Register II (Address: 0x849h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CPC II
Reset
W
CPTX3
0
CPTX2
0
CPTX1
1
CPTX0
0
CPRX3
0
CPRX2
0
CPRX1
1
CPRX0
0
CPTX [3:0]: Charge Pump Current Setting for TX mode. Recommend CPTX = [0010].
Charge pump current = (CPTX + 1) / 16 mA.
CPRX [3:0]: Charge Pump Current Setting for RX mode. Recommend CPRX = [0010].
Charge pump current = (CPRX + 1) / 16 mA.
Sep., 2014, Version 0.6 (Preliminary)
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2.4GHz FSK/GFSK SoC
9.2.75 VCO Modulation Delay Register (Address: 0x84Ah)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VCO Delay
Reset
W
—
0
INTPRC
0
DEVFD2
1
DEVFD1
0
DEVFD0
1
DEVD2
0
DEVD1
0
DEVD0
0
INTPRC: Internal PLL loop filter resistor and capacitor select.
[0]:
disable.
[1]:
enable
DEVFD [2:0]: VCO Modulation Data Delay by 8x over-sampling Clock. Recommend DEVFD = [101].
DEVD [2:0]: VCO Modulation Data Delay by XCPCK Clock. Recommend DEVD = [000].
9.2.76 Internal Capacitance Register (Address: 0x84Bh)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTC
W
VRPL1
0
VRPL0
0
VCOSC5
0
VCOSC4
1
VCOSC3
0
VC
C2
1
VCOSC1
0
VCOSC0
0
Reset
VRPL [1:0]: internal PLL loop filter resistor value select.
[00]:
500 ohm.
[01]:
666 ohm.
[10]:
1 K ohm.
[11]:
2K ohm.
VCOSC[5:0]: Reserved for internal usage
9.2.77 RX Detection Register (Address: 0x84Ch)
Name
R/W
Bit 7
Bit 6
Bit 5
it 4
Bit 3
Bit 2
Bit 1
Bit 0
W
R
PRED
REDN1
PREDN0
PREUP2
PREUP1
PREUP0
DC_SEL RXDCS
DET
DCOUT[7:0]
Reset
0
0
1
0
0
0
1
0
DC_SEL: Initial DC value select when sync word ok.[0]:
DC set by last pattern DC
[1]:
DC set by 0x82Eh DC value.
RXDCS: RX dc average clock setting. Re
om
ed RXDCS=[0]
PREDN[2:0]: Preamble detect low
old setting.
PREUP[2:0]: Preamble dete
t high threshold setting.
DCOUT [7:0]: Read demodulator DC value.
9.2.78 BLE Header Register 0 (Address: 0x84Dh)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
R
TXHDR15 TXHDR14 TXHDR13 TXHDR12 TXHDR11 TXHDR10
TXHDR9
RXHDR15 RXHDR14 RXHDR13 RXHDR12 RXHDR11 RXHDR10
RXHDR9
TXHDR8
RXHDR8
0
HEADER0
Re
0
0
0
0
0
0
0
TXHDR[15:0]: TX header setting for BLE mode.
RXHDR[15:0]: RX header setting for BLE mode.
9.2.79 BLE Header Register 1 (Address: 0x84Eh)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
R
TXHDR7
RXHDR7
0
TXHDR6
RXHDR6
0
TXHDR5
RXHDR5
0
TXHER4
RXHDR4
0
TXHDR3
RXHDR3
0
TXHDR2
RXHDR2
0
TXHDR1
RXHDR1
0
TXHDR0
RXHDR0
0
HEADER1
Reset
Sep., 2014, Version 0.6 (Preliminary)
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2.4GHz FSK/GFSK SoC
9.2.80 ID Register 0 (Address: 0x84Fh)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ID0
W/R
ID31
0
ID30
0
ID29
0
ID28
0
ID27
0
ID26
0
ID25
0
ID24
0
Reset
ID[31:0]: ID Data.
Once this address is accessed, ID Data is input/output in sequence corresponding to Write or Read.
9.2.81 ID Register 1 (Address: 0x850h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ID1
W/R
ID23
0
ID22
0
ID21
0
ID20
0
ID19
0
ID18
0
ID
7
0
ID16
0
Reset
ID[31:0]: ID Data.
Once this address is accessed, ID Data is input/output in sequence corresponding to Write or Read.
9.2.82 ID Register 2 (Address: 0x851h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 2
Bit 1
Bit 0
ID2
W/R
ID15
0
ID14
0
ID13
0
ID12
0
ID
0
ID10
0
ID9
0
ID8
0
Reset
ID[31:0]: ID Data.
Once this address is accessed, ID Data is input/output in se
en
corresponding to Write or Read.
9.2.83 ID Register 3 (Address: 0x852h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ID3
W/R
ID7
0
ID6
0
ID5
0
ID4
0
ID3
0
ID2
0
ID1
0
ID0
0
Reset
ID[31:0]: ID Data.
Once this address is accessed, ID Data i
in
t/output in sequence corresponding to Write or Read.
9.2.84 DID Register 0 (Address
3h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DID0
R
DID31
1
DID30
0
DID29
1
DID28
0
DID27
1
DID26
0
DID25
1
DID24
0
Reset
DID[31:0]: Device ID.
9.2.85 DID
egister 1 (Address: 0x854h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
D
R
DID23
1
DID22
0
DID21
0
DID20
0
DID19
0
DID18
0
DID17
0
DID16
1
Re
et
DID[31:0]: Device ID.
9.2.86 DID Register 2 (Address: 0x855h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DID2
R
DID15
0
DID14
0
DID13
0
DID12
0
DID11
0
DID10
1
DID9
0
DID8
1
Reset
DID[31:0]: Device ID.
Sep., 2014, Version 0.6 (Preliminary)
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2.4GHz FSK/GFSK SoC
9.2.87 DID Register 3 (Address: 0x856h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DID3
R
DID7
1
DID6
0
DID5
1
DID4
0
DID3
0
DID2
0
DID1
0
DID0
1
Reset
DID[31:0]: Device ID.
9.2.88 EXT Register 1 (Address: 0x857h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EXT1
Reset
W/R
—
—
XEC
1
BREV
0
BGS
0
LIMB
0
ADCCS
0
BOD
0
REGR
0
XEC
:
Reserved. Should set to [1]
BREV
:
data byte reversion for TX data in the air
[0]:
normal.
[1]:
reverted.
BGS
:
Reverved should set to [0]
LIMB
:
Reserved. Should set to [0]
ADCCS
:
Reserved. Should set to [0]
BOD
: regulator input low voltage detect selection.
[0]:
disable.
[1]:
enable.
REGR
:
pin7
“
VDD_R
”
driver voltage output enable for 12bit ADC
[0]:
disable.
[1]:
enable. Output voltage is equal to pin8
“
VDD_A
”
9.2.89 EXT Register 2 (Address: 0x858h)
Name
R/W
Bit 7
Bit 6
Bit 5
it 4
Bit 3
Bit 2
Bit 1
Bit 0
EXT2
Reset
W
VTRB3
0
VTRB2
0
VTRB
0
VTRB0
0
VMRB3
0
VMRB2
0
VMRB1
0
VMRB0
0
VTRB[3:0]
:
Reserved. Should set to [0000]
VMRB[3:0]
:
Reserved. Should set to [0000]
9.2.90 EXT Register 3 (Address: 0x859h
Name
R/W
Bit 7
B
t 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EXT3
Reset
W
—
0
VCS
0
VCSW
0
FAS
0
CGC
0
IWA
0
IWC
0
LBG
0
IFAS: Reserved for internal
sage only.
CGC: Clock generation setting. [Fcsck = 32Mhz]: GRC=7, CGC=0.
[Fcsck = 64Mhz]: GRC=3, CGC=1.
IWA: RXFE new IFAMP path
ain
IWC: Reserved for i
ternal usage only. Shall be set to [0].
LBG: Reserved
inte
nal usage only.
VCS
:
Reserv
d.
VCSW
:
Reserved.
9.2.91 ADC Control Register (Address: 0x85Ah)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
R
BUFS
CKS
—
—
—
0
MODE
MODE
0
MVS2
MVS2
0
MVS1
MVS1
0
MVS0
MVS0
0
ADCE
ADCE
0
ADCCTL
Reset
—
0
1
BUFS
:
input buffer select for 12 bit ADC.
[0]:
disable.
[1]:
enable.
CKS: ADC clock selected.
[0]
: 1 MHz
[1]
: 4 MHz
Sep., 2014, Version 0.6 (Preliminary)
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2.4GHz FSK/GFSK SoC
MODE: ADC measurement mode.
[0]:
Single mode.
[1]:
Continuous mode.
MVS [1:0]: ADC average times (for VCO calibration and RSSI ).
[00]:
Average 8 times.
[01]:
Average 16 times.
[10]:
Average 32 times.
[11]:
Average 64 times.
ADCE: ADC measurement enable
9.2.92 ADC Value Register 1 (Address: 0x85Bh)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B
t 0
W
R
ADCIE
—
—
—
MVADC8
—
ADIVL
ADC11
0
ADCYC
ADC10
0
ENAD
ADC9
0
DTMP
ADC8
0
ADCAVG1
Reset
MVADC11 MVADC10
MVADC9
0
— —
ADCIE : 12-bits interrupt enable.
[0]:
disable.
[1]:
enable.
ADIVL: Reserved. Should set to [0]
ADCYC: Reserved. Should set to [0]
ENADC: Enable ADC.
MVADC [11:0]: Moving average ADC output value
ADC [11:0]: ADC output value
MVADC [11:0]: Moving average ADC output value
9.2.93 ADC Value Register 2 (Address: 0x85Ch)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADCAVG2
Reset
R
MVADC7
—
MVADC6
—
MVADC5
—
MVADC4
—
MVADC3
—
MVADC2
—
MVADC1
—
MVADC0
—
MVADC [11:0]: Moving average AD
utput value
9.2.94 ADC Value Register 3 (A
s: 0x85Dh)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADCAVG3
Reset
R
A
C7
—
ADC6
—
ADC5
—
ADC4
—
ADC3
—
ADC2
—
ADC1
—
ADC0
—
ADC [11:0]: ADC
utp
t value
9.2.95 Timer
nte
val Register 1 (Address: 0x85Eh)
N
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W/R
TMR_ITV[15:8]
TMR
TV1
Reset
0
0
0
0
0
0
0
0
TMR_ITV[15:0]
: Timer interval setting.
Timer interval can be set to be:
TMRCKS[1:0] = 00: 0.15625 ms ~ 10.24 s
TMRCKS[1:0] = 01: 0.3125 ms ~ 20.48 s
TMRCKS[1:0] = 10: 0.625 ms ~ 40.96 s
TMRCKS[1:0] = 11: 1.25 ms ~ 81.92 s
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2.4GHz FSK/GFSK SoC
9.2.96 Timer Interval Register 2 (Address: 0x85Fh)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W/R
TMR_ITV[7:0]
TMRITV2
Reset
0
0
0
0
0
0
0
0
TMR_ITV[15:0]
: Timer interval setting.
Timer interval can be set to be:
TMRCKS[1:0] = 00: 0.15625 ms ~ 10.24 s
TMRCKS[1:0] = 01: 0.3125 ms ~ 20.48 s
TMRCKS[1:0] = 10: 0.625 ms ~ 40.96 s
TMRCKS[1:0] = 11: 1.25 ms ~ 81.92 s
9.2.97 Timer Wake On Radio Register 0 (Address: 0x860h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W/R
—
TMRWOR0
Reset
0
0
0
0
0
0
0
0
9.2.98 Timer Wake On Radio Register 1 (Address: 0x861h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit
Bit 2
Bit 1
Bit 0
W/R
TMRWORS
—
0
—
0
TMR_O
S4 TMR_OFS3 TMR_OFS2 TMR_OFS1 TMR_OFS0
TMRWOR1
Reset
0
0
0
0
0
TMRWORS:
Timer WOR / WOT selection.
[0]:
WOR
[1]:
WOT
TMR_OFS[4:0]:
Interrupt offset for 16-bits Timer.
9.2.99 Timer Control Register (Address
0x862h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
R
TMRON
TMRIE
MRIE
0
TMRIF
TMRIF
0
TMRCOR TMRWOR
TMRCKS[1:0]
TMRCKS[1:0]
TMR_CE
TMR_CE
0
TMRCTL
Reset
—
0
—
—
0
0
0
0
TMRON:
Turn on TMR.
TMRIE
: Timer Interrupt Enable.
[0]: Disable.
[1]: Enable.
TMRIF
: Timer Int
rupt
lag. (Write “1” to clear)
TMRCOR
: Timer
LK re-correct when sync.
[0]:
disable.
[1]:
enable
TMRWO
er WOR function enable.
[0]: Disabl
[1]: Enable.
TMRCKS[1:0]: Select Timer Source Clock
[00]: 6.4 kHz
[01]: 3.2 kHz
[10]: 1.6 kHz
[11]: 0.8 kHz
TMR_CE
: Start Timer counting.
[0]: Stop.
[1]: Start.
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2.4GHz FSK/GFSK SoC
9.2.100 Power Control Register 0 (Address: 0x863h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
CBG2
0
CBG1
0
CBG0
0
PDNS
1
STS
0
ENDL2
0
ENDL1
0
ENDL0
0
PWRCTL0
Reset
CBG[2:0]: Reserved for internal usage.
PDNS: Power manager to turn on REGOD Recommend PDNS = [0]
STS: Reserved for internal usage onl
y
.
S
hall be set to [0].
ENDL[2:0]: Reserved for internal usage only
9.2.101 Power Control Register 1 (Address: 0x864h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
B
t 1
Bit 0
W
EBOD
1
ENAV
0
QDSA
1
ENDV
1
QDSD
0
CEL
0
SVRE
0
CELA
0
PWRCTL1
Reset
EBOD: Reserved for internal usage.
ENAV: REGOA and REGOS connection.
QDSA: quick discharge select for REGOA.
ENDV: REGOA is connected to REGOD.
QDSD: quick discharge select for REGOD.
CEL: Digital voltage select in standby mode. Recommend CEL = [0].
SVREF: Reserved for internal usage. Recommend SVREF = [0].
CELA: Reserved for internal usage.
PM mode: Low power operation select.
MCU STOP
PM1(idle)
ENAV=1, QDSA=0, ENDV=1, QDSD=0
PM2(sleep)
ENAV=0, QDSA=1, ENDV=1, QDSD
PM3(deep sleep)
ENAV=0, QDSA=1, ENDV=0, QDSD=
9.2.102 Power Control Register 2 (Address:
x865h)
Name
R/W
Bit 7
Bit
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
RTCPUNIE
—
—
RCR1
0
RCR0
0
RGC1
0
RGC0
1
RCHC
0
PWRCTL2
Reset
0
—
—
RTCPUNIE: Reserved for internal
Shall be set to [0].
RCR[1:0]: Reserved for internal usag
.
RGC[1:0]: Low power band-
ap current select. Recommend RGC = [01]
RCHC: Reserved for internal
sage.
9.2.103 Power Contr
l Re
ister 3 (Address: 0x866h)
Name
R
W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
MR7
0
MR6
0
MR5
0
MR4
0
MR3
0
MR2
0
MR1
0
MR0
0
PWRCT
3
Reset
MR[7:0]:
served for internal usage.
9.2.104 Power Control Register 4 (Address: 0x867h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
MS7
0
MS6
0
MS5
0
MS4
0
MS3
0
MS2
0
MS1
0
MS0
0
PWRCTL4
Reset
MS[7:0]: Reserved for internal usage.
9.2.105 DC_SHIFT(Address: 0x868h)
Name R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
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2.4GHz FSK/GFSK SoC
dc_shift[7:0]
W/R
DCSFT
Reset
0
1
0
1
0
1
0
0
dc_shift [7:0]: DC average by ID initial dc value shift setting. (NOTE): DC_SHIFT[7] is signed bit.
9.2.106 TX_5DLY(Address: 0x869h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
HDRSW
0
EARTS
EACKS
TX_5DLY[4:0]
TX5DY
Reset
0
0
0
0
0
0
0
HDRSW: switch header length
[1]: 6 bits
[0]: 5 bits
EARTS:
Auto resend
( EARTS=1
TX)
EACKS:
Auto ack
( EACKS=1
RX)
TX_5DLY [4:0]: TX data output delay timing after PDN_TX enable.
9.2.107 ACKRT (Address: 0x87Ch)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit
Bit 2
Bit 1
Bit 0
W
L
OUT[5:0]
ACKRT
Reset
—
0
—
0
0
1
0
0
0
1
LL_TIME_OUT[5:0]:
RX timeout register,
Timeout = 20us x (1+LL_TIM
_OUT)
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2.4GHz FSK/GFSK SoC
10.SOC Architectural Overview
A8105 microcontroller is instruction set compatible with the industry standard 8051. Besides FSK/GFSK RF transceiver, A8105
integrates many features, three 8/16bit counters/timers, watchdog timer, RTC, UART, SPI interface, I
2
C interface, 2 channels
PWM, 8 channels ADC and battery detector, The interrupt controller is extended to support 6 interrupt sources; watchdog timer,
RTC, SPI, I
2
C, ADC and RF. A8105 includes TTAG (2-wire) debug circuitry that provides full time, real-time, in-circuit
debugging.
10.1 Pipeline 8051 CPU
A8105 microcontroller has pipelined RSIC architecture 10 times faster compared to standard 8051 archite
e. The pipeline
8051 is fully compatible with the MCS-51
TM
instruction set. User can use standard 8051 assemblers and co
pilers to develop
software. The pipelined architecture 8051 has greatly increases its instruction throughput over the standa
d 8051 architecture.
A8105 has a total of 110 instructions. The table below shows the total number of instructions that re
uire each execution time.
For more detail information of instruction, please refer Table 10.1.
Clock to Execute
1
2
3
4
5
8
6
1
Number of instructions
24
38
29
11
10.2 Memory Organization
The memory organization of A8105 is similar to the standard 8051. The memory organization is shown as figure 10.1
Program /Data
memory (FLASH)
External Data
address sp
ce
Internal Data Space
0x3FFF
0xFF
2KBytes
Data Storage
(In-System
Special
Function
programmable in 512
bytes sector)
Upper 128 RAM
(Indirect Adressing
Only)
0x3800
0x37FF
Registers
(Direct addressing only
0A7F
0x0900
0x80
0x7F
RF FIFO
RF Register
0x0800
0x07FF
Direct and Indirect
Addressing
Low 128
Bytes RAM
(Direct and Indirect
Addressing )
XRAM 2KBytes
(accessable using
MOVX instruction)
0x30
0x2F
Bit Addressable
0x20
General Purpose
Registers
0x1F
0x00
0
0x00
0x0000
Figure 10.1 Memory Organization
10.2.1 Program memory
The standard 8051 core has 64KB program memory space. A8105 implement 16KB flash. The last 2KB program memory
space (0x 3800 ~ 0x3FFF) supports IAP (In-Application Programming) function. The each block size in this area is 128Bytes.
User has 16 blocks in 2KB program memory space to storage data. Program memory is normally assumed to be read-only.
However, A8105 can write to program memory by IAP function call. Please reference Application note to write program memory
for more detail.
10.2.2 Data memory
The A8105 includes 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128
bytes of data memory are used for general purpose registers and scratch pad memory. Either direct or indirect addressing may
be used to access the lower 128 bytes of data memory. Locations 0x00 through 0x1F are addressable as four banks of general
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2.4GHz FSK/GFSK SoC
purpose registers, each bank consisting of eight byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may
either be addressed as bytes or as 128 bit locations accessible with the direct addressing mode. The upper 128 bytes of data
memory are accessible only by indirect addressing. This region occupies the same address space as the Special Function
Registers (SFR) but is physically separate from the SFR space. The addressing mode used by an instruction when accessing
locations above 0x7F determines whether the CPU accesses the upper 128 bytes of data memory space or the SFRs.
Instructions that use direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the
upper 128 bytes of data memory. Figure 10.1 illustrates the data memory organization of the A8105.
10.2.3 General Purpose Registers
The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of general
purpose
registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only one of these banks m
y be enabled
at a time. Two bits in the program status word, RS0 (PSW.3) and RS1 (PSW.4), select the active register
(see description
of the PSW in SFR Definition 9.1). This allows fast context switching when entering subroutines and interru
service routines.
Indirect addressing modes use registers R0 and R1 as index registers.
10.2.4 Bit Addressable Locations
In addition to direct access to data memory organized as bytes, the sixteen data memory locatio
s at 0x20 through 0x2F are
also accessible as 128 individually addressable bits. Each bit has a bit address from 0x00 t
0x7F. Bit 0 of the byte at 0x20 has
bit address 0x00 while bit7 of the byte at 0x20 has bit address 0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access
is distinguished from a full byte access by the type of instruction used (bit source or d
s
ination operands as opposed to a byte
source or destination). The MCS-
51™ ass
embly language allows an alternate n
on f
r bit addressing of the form XX.B
where XX is the byte address and B is the bit position within the byte. For exa
e instruction:
MOV C, 22.3h ;moves the Boolean value at 0x13 (bit 3 of the byte at locatio
0x
to the Carry flag.
10.2.5 Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitu
e th
special function registers (SFRs). The SFRs provide
control and data exchange with the CIP-51’s resources and perip
eral
The CIP-51 duplicates the SFRs found in a typical 8051
implementation as well as implementing additional SFRs used to configure and access the sub-systems unique to the MCU.
This allows the addition of new functionality while retaining
tibi
ity with the MCS-
51™ instruction set. Table 9.2 lists the
SFRs implemented in the CIP-51 System Controller.
The SFR registers are accessed anytime the direct addressin
mode is used to access memory locations from 0x80 to 0xFF.
SFRs with addresses ending in 0x0 or 0x8 (e.g. P0,
CON, SCON0, IE, etc.) are bit-addressable as well as byte-addressable.
All other SFRs are byte-addressable only. Unoccupie
addresses in the SFR space are reserved for future use. Accessing
these areas will have an indeterminate effect
d should be avoided.
10.2.6 Stack
A8105 has 8-bit stack point called SP
81) located in the internal RAM space. It is incremented before data is stored during
PUSH and CALL execution and dec
d after data is popped during POP, RET and RETI execution. In the other words it
always points to the last valid stack b
he SP is accessed as any other SFRS.
Addre
s/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
81h
R/W
SP
Reset
0
0
0
0
0
1
1
1
Stack pointer register
10.2.7 Data Pointer Register
A8105 ar
plemented dual data pointer registers, auto increment and auto decrement to speed up data block copying.
DPTR0 an
DPTR1 are located at four SFR addresses. Active DPTR register is selected by SEL bit (0x86.0). If SEL = 0 the
DPTR0 is s
lected otherwise DPTR1.
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
82h
DPL0
R/W
Reset
0
0
0
0
0
0
0
0
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
83h
DPH0
R/W
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2.4GHz FSK/GFSK SoC
Reset
0
0
0
0
0
0
0
0
Data Pointer Register DPTR0
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
84h
DPL1
R/W
Reset
0
0
0
0
0
0
0
0
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
85h
DPH1
R/W
Reset
0
0
0
0
0
0
0
0
Data Pointer 1 Register DPTR1
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bi
1 Bit
0
86h
DPS
Reset
R/W ID1
0
ID0 TSL
AU1 AU0
–
SEL
0
0
0
0
0
0
Data Pointers Select Regist
r
ID[1:0]
‐
Increment/decrement function select. See table below.
TSL
‐
Toggle select enable. When set, this bit allows the following D
TR
elated instruction to toggle the SEL bit following
execution of the instruction:
MOVC A, @A+DPTR
INC DPTR
MOVX @DPTR, A
MOVX A, @DPTR
MOV DPTR, #data16
When TSL=0, DPTR related instructions do not affect
tate of SEL bit.
AU
‐
When set to ‘1’ performs automatic in
rem
nt
0)/ decrement(1) of selected DPTR according to IDx bits, after each MOVX
@DPTR, MOVC @DPTR instructions
SEL
‐
Select active data pointer
–
se
e below
‐ ‐
Unimplemented bit. Read as 0
Table DPTR0, DPTR1 operations
Selected d
ta pointer register in used in the following instructions:
MOV
@DPTR,A
MOVX A,@DPTR
MOVC A,A+DPTR
JMP @A+DPTR
INC DPTR
MOV DPTR,#data16
10.2.8 RF Registers and RF FIFO
RF registers are RF radio control registers and located in 0x0800 ~ 0x08ff. Please refer the section 9.2 and the related function
setting in the datasheet. A8105 has 384 Bytes FIFO located from 0x0900 to 0x0A7F. There are 128 bytes FIFO from 0x0900 ~
0x097F for data transmitting. There are 128 bytes FIFO from 0x0980 ~ 0x09FF for data receiving.
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10.3 Instruction set
A8105 use a high performance, pipeline 8051 core and it is filly compatible with the standard MCS-51
TM
instruction set.
Standard 8051 development tools can used to develop software for A8105. All A8105 instruction sets are the binary and
functional equivalent of the MCS-51
TM
. However, instruct timing is different with the standard 8051. All instruction timings are
specified in the terms of clock cycles as shown in the table 10.1
Mnemonic
Description
Code
0x11
‐
0xF1
0x24
Bytes Cycles
ACALL addr11
ADD A,#data
ADD A,@Ri
ADD A,direct
ADD A,Rn
ADDC A,#data
ADDC A,@Ri
ADDC A,direct
ADDC A,Rn
AJMP addr11
ANL C,/bit
ANL A,#data
ANL A,@Ri
ANL A,direct
ANL A,Rn
ANL C,bit
Absolute subroutine call
2
2
2
1
2
1
2
1
2
2
2
1
2
1
2
3
2
3
3
3
3
1
2
1
1
2
1
1
2
1
1
1
4
2
2
2
1
2
2
2
1
3
2
2
2
2
1
2
3
3
5
4
5
4
1
3
1
1
3
1
3
3
1
3
2
Add immediate data to accumulator
Add indirect RAM to
accumulator
Add direct byte
to accumulator
Add register to accumulator
0x26
‐
0x27
0x25
0x28
‐
0x
F
0x
4
Add immediate data to A with
carry flag
Add indirect RAM to A with carry flag
Add direct byte to A with carry flag
Add register to accumulator with carry fla
Absolute jump
0
36
‐
0x37
x35
0x38
‐
0x3F
0x01
‐
0xE1
0xB0
AND complement of direct bit to
arry
AND immediate data to accum
ator
AND indirect RAM to
tor
AND direct byte to accum
tor
AND register to
ccumu
ator
0x54
0x56
‐
0x57
0x55
0x58
‐
0x5F
0x82
AND direc
it to carry flag
ANL direct,#data
ANL direct,A
CJNE @Ri,#data
CJNE A,#datare
CJNE A,d
ectre
CJNE R
,#da
ar
CLR A
AND i
med
ate data to direct byte
ccumulator to direct byte
0x53
0x52
C
e immediate to ind. and jump if not equal
0xB6
‐
0xB7
ompare immediate to A and jump if not equal
Compare direct byte to A and jump if not equal
Compare immediate to reg.
and jump if not equal
Clear accumulator
0xB4
0xB5
0xB8
‐
0xBF
0xE4
CLR
t
Clear direct bit
0xC2
CLR C
Clear carry flag
0xC3
CPL A
Complement accumulator
0xF4
CPL bit
Complement direct bit
0xB2
CPL C
Complement carry flag
0xB3
DA A
Decimal adjust accumulator
Decrement indirect RAM
Decrement accumulator
0xD4
DEC @Ri
0x16
‐
0x17
0x14
DEC A
DEC direct
DEC Rn
Decrement direct byte
0x15
Decrement register
0x18
‐
0x1F
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2.4GHz FSK/GFSK SoC
DIV A,B
Divide A by B
0x84
0xD5
1
3
2
1
1
2
1
1
3
2
1
3
2
2
2
3
3
1
2
2
1
2
2
2
1
2
3
2
2
2
3
3
2
1
2
1
1
6
5
4
3
1
3
2
5
5
3
5
5
3
4
4
4
4
2
3
2
2
3
2
2
1
2
3
3
2
2
3
3
2
1
3
5
4
DJNZ direct,rel
DJNZ Rn,rel
INC @Ri
Decrement direct byte and jump if not zero
Decrement register and jump if not zero
Increment indirect RAM
0xD8
‐
0xDF
0x06
‐
0x07
0x04
INC A
Increment accumulator
INC direct
Increment directbyte
0x05
INC Rn
Increment register
0x08
‐
0x0F
0xA3
INC DPTR
Increment data pointer
JB bit,rel
Jump if direct bit is set
0x20
JBC bit,directre
JC rel
Jump if direct bit is set and clear bit
Jump if carry flag is set
0x10
0
0
JMP@A+DPTR
JNB bit,rel
Jump indirect relative to the DPTR
Jumpifdirectbitisnotset
0x73
0
30
JNC
Jump if carry flag is not set
Jump if accumulator is not zero
Jump if accumulator is zero
Long subroutine
call
0x50
JNZ rel
0x70
JZ rel
0x60
LCALL addr16
LJMP addr16
MOV A,@Ri
MOV bit,C
MOV @Ri,#data
MOV @Ri,A
MOV @Ri,direct
MOV A,#data
MOV A,direct
MOV A,Rn
MOV C,bit
MO
direc
,#data
OV direct,@Ri
MOV direct,A
MOV direct,Rn
MOV direct1,direct2
0x12
Long jump
0x02
Move indirect RAM to
ator
Move carry flag
o dire
bit
Move imm
diate data to indirect RAM
Move
cumula
or to indirect RAM
M
dire
t byte to indirect RAM
mmediate data to accumulator
Move direct byte to accumulator
Move register to accumulator
Move direct bit to carry flag
Move immediate data to direct byte
Move indirect RAM to direct byte
Move accumulator to direct byte
Move register to direct byte
Move direct byte to direct byte
0xE6
‐
0xE7
0x92
0x76
‐
0x77
0xF6
‐
0xF7
0xA6
‐
0xA7
0x74
0xE5
0xE8
‐
0xEF
0xA2
0x75
0x86
‐
0x87
0xF5
0x88
‐
0x8F
0x85
MOV DPTR,#data16
Load 16
‐
bit constant in
to active DPTR
0x90
MOV Rn,#data
MOV Rn,A
Move immediate data to register
Move accumulator to register
Move direct byte to register
0x78
‐
0x7F
0xF8
‐
0xFF
0xA8
‐
0xAF
0x93
MOV Rn,direct
MOVC A,@A+DPTR
Move code byte relative to DPTR to accumulator
MOVC A,@A+PC
Move code byte relative to PC to accumulator
0x83
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2.4GHz FSK/GFSK SoC
MOVX @DPTR,A
MOVX @Ri,A
MOVX A,@DPTR
MOVX A,@Ri
MUL A,B
Move A to external
SRAM (16
‐
bitaddress)
Move A to external RAM
(8
‐
bitaddress)
Move external RAM (16
‐
bitaddress) to A
Move external RAM (8
‐
bitaddress) to A
Multiply A and B
0xF0
0xF2
‐
0xF3
0xE0
1
1
1
1
1
1
2
2
1
1
2
2
3
2
2
1
1
1
1
1
1
1
2
2
1
2
2
1
1
1
2
1
1
3
2
1
2
1
2
1
2
2
1
3
2
2
1
2
2
3
2
3
4
4
1
1
1
1
1
3
3
2
2
2
1
1
3
3
2
3
3
2
2
2
0xE2
‐
0xE3
0xA4
NOP
No operation
0x00
ORL direct,A
ORL A,#data
ORL A,@Ri
ORL A,direct
ORL A,Rn
ORL C,/bit
ORL C,bit
OR accumulator to direct byte
0x42
OR immediate data to accumulator
OR indirect RAM to accumulator
OR direct byte to accumulator
0x44
0x46
‐
0x47
0x45
OR register to accumulator
0x4
x4F
0xA0
OR complement of direct bit to carry
OR direct bit to carry flag
0
72
ORL direct,#data
POP direct
PUSH direct
RET
OR immediate data to direct byte
Pop direct byte from internal
ram stac
Push direct byte on
to internal
ram stac
Return from subroutine
0x43
0xD0
0xC0
0x22
RETI
Return from interrupt
0x32
RL A
Rotate accumulator left
0x23
RLC A
Rotate accumulat
r left
rough carry
Rotate acc
mulator right
0x33
RR A
0x03
RRC A
Rotate
ccu
ul
tor right through carry
S
rry
lag
0x13
SETB C
0xD3
SETB bit
ct bit
0xD2
SJMP rel
Short jump (relative address)
0x80
SUBB A,@Ri
SUBB A,d
ect
SU
A,#
ata
UB
A,Rn
SWAP A
Subtract indirect RAM from A with borrow
Subtract direct byte from A with borrow
Subtract immediate data from A with borrow
Subtract register from A with borrow
Swap nibbles within the accumulator
Exchange indirect RAM with accumulator
Exchange direct byte with accumulator
Exchange register with accumulator
Exchange low
‐
order nibble indirect RAM with A
ExclusiveOR immediate data to direct byte
ExclusiveOR immediate data to accumulator
ExclusiveOR indirect RAM to accumulator
ExclusiveOR direct byte to accumulator
0x96
‐
0x97
0x95
0x94
0x98
‐
0x9F
0xC4
XCH A,@Ri
XCH A,direct
XCH A,Rn
XCHD A,@Ri
XRL direct,#data
XRL A,#data
XRL A,@Ri
XRL A,direct
0xC6
‐
0xC7
0xC5
0xC8
‐
0xCF
0xD6
‐
0xD7
0x63
0x64
0x66
‐
0x67
0x65
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XRL A,Rn
ExclusiveOR register to accumulator
0x68
‐
0x6F
1
2
1
3
XRL direct,A
ExclusiveOR accumulator to direct byte
Table 10.1 Instruction set sorted by alphabet
0x62
10.4 Interrupt handler
This section describes 8051 external interrupts and their functionality. For peripheral related interrupts, please refer to an
appropriate peripheral section. The external interrupts symbol is shown in figure above. And the pins functionality is described in
the following table. All pins are one directional. There are no three-state output pins and internal signals.
Name
ACTIVE
TYPE DESCRIPTION
int0(P3.2) low/falling Input External
interrupt 0 line
int1(P3.3) low/falling Input External
interrupt 1 line
int2(P0.7)
int3*(P1.2)
int4*(P1.3)
RFINT
low
low
low
failing
failing
Input External
interrupt 2 line
Input External
interrupt 3 line
Input External
interrupt 4 lin
KEYINT
Table 10.2
External interrupts pins desc
Note1
：
Number of external interrupt sources depends on core configuratio
. It
be adjusted upon request. The int0 & int1
sources are always available. Please check your configuration.
Note2
：
*pin functionality depends on compare / capture unit.
10.4.1 FUNCTIONALITY
All 8051 IP cores have implemented two levels interrupt pri
ty c
trol. Each external interrupt can be in high or low level
priority group by setting or clearing a bit in the IP(0xB8), EIP
xF8
, and DEVICR(0xCF) registers. External interrupt pins are
activated at low level or by a falling edge. Interrupt reques
mpled each system clock at the rising edge of CLK.
Interrupt flag
Function
Active level/edge
Flag resets
Vector
1
Natural priority
IE0
TF0
IE1
TF1
TI & RI
TF2
Reserved
INT2F
INT3F
INT4F
RFINT
KEYINT
WDIF
I2CMIF
I2CSI
PIIF
Device pin INT0
Low/falling
Hardware
Hardware
Hardware
Hardware
Software
Software
Software
Hardware
Hardware
Hardware
Software
Software
Software
Software
Software
0x03
0x0B
0x13
0x1B
0x23
0x2B
0x33
0x3B
0x43
0x4B
0x53
0x5B
0x63
0x6B
0x73
1
2
3
4
5
6
7
8
Internal, Timer 0
Device pin INT1
Internal, Timer 1
Interrupt, UART
Interrupt, Ti
Reserved
Devic
pin INT2
Devic
pin I
T3
Device
in INT4
nterrupt, RFINT
I
terr
pt, KeyINT
nternal, Watchdog
Internal, I2C MASTER MODULE
Internal, DI2CS/
Internal, SPI
–
Low/falling
–
–
–
–
Low
Low
Low
-Falling
9
10
11
12
13
14
15
-Falling
–
–
–
rved
R
served
Reserved
Reserved
–
–
Hardware
Hardware
0x7B
0x83
16
17
Table10.3
8051 interrupts summary
1- This
is a default location when IRQ_INTERVAL = 8, in other case is equal to (IRQ_INTERVAL* n ) + 3, when n = (natural Priority – 1)
Each interrupt vector can be individually enabled or disabled by setting or clearing a corresponding bit in the IE(0xA8),
EIE(0xE8), DEVICR(0xCF). The IE contains global interrupt system disable(0) / enable(1) bit called EA.
IE register
(0xA8)
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
A8h
IE
R/W EA
–
ET2 ES0 ET1 EX1 ET0 EX0
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Reset
0
0
0
0
0
0
0
0
EA
：
Enable global interrupts
EX0
：
Enable INT0 interrupts
ET0
：
Enable Timer 0 interrupts
EX1
：
Enable INT1 interrupts
ET1
：
Enable Timer 1 interrupts
ES
：
Enable UART interrupts
ET2
：
Enable Timer 2 interrupts
All of bits that generate interrupts can be set or cleared by software, with the same result as if
had been set or
cleared by hardware. That is, interrupts can be generated or pending interrupts can be cancelled by so
twar
The exceptions of
this rule are the request flags IE0 and lE1. If the external interrupts 0 or 1 are programmed to be le
el ac
vat
d, IE0 and lE1 are
controlled by the external source via pin INT0 and INT1, respectively. Thus, writing a one to these bits will not set the request
flag IE0 and/or lE1. The same exception is related to INT2F, INT3F, INT4F, RFINTF, and KEYINTF
–
external interrupts number
2, 3, 4, 5, 6.
IP register
(0xB8)
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bi
Bit
Bit 1
Bit 0
B8h
IP
Reset
R/W
–
–
PT2
0
PS
0
P
X1 PT0 PX0
0
0
0
0
0
PX0
：
INT0 priority level control (at 1-high-level)
PT0
：
Timer 0 priority level control (at 1-high-level)
PX1
：
INT1 priority level control (at 1-high-level)
PT1
：
Timer 1 priority level control (at 1-high-level)
PS
：
UART priority level control (at 1-high-level)
PT2
：
Timer 2 priority level control (at 1-high-level)
TCON register
(0x88)
Address/N
/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
88h
TCON
R
set
R/W TF1 TR1 TF0 TR0 IE1
IT1
0
IE0
0
IT0
0
0
0
0
0
0
IT0
：
INT0 level (at 0) /
dge (
t 1) sensitivity
IT1
：
INT1 level (at 0)
edge (at 1) sensitivity
IE0
：
INT0 interru
ag
Cleared
y h
rdware when processor branches to interrupt routine
IE1
：
INT1 interrupt flag
Cle
by hardware when processor branches to interrupt routine
TF0
：
Tim
0 interrupt (overflow) flag
Cleared by hardware when processor branches to interrupt routine
TF1
：
Timer 1 interrupt (overflow) flag
Cleared by hardware when processor branches to interrupt routine
SCON register
(0x98)
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
98h
SCON
Reset
R/W SM0 SM1 SM2 REN TB8
RB8
0
TI
0
RI
0
0
0
0
0
0
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RI
：
UART receiver interrupt flag
TI
：
UART transmitter interrupt flag
EIE register
(0xE8)
Address/Name R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
E8h
EIE
Reset
EI2CS
ESPI
0
R/W
EI2CM EWDI EKEYINT ERFINT EINT4 EINT3 EINT2
0
0
0
0
0
0
0
EINT2
：
Enable INT2 interrupts
EINT3
：
Enable INT3
EINT4
：
Enable INT4
ERFINT
：
Enable RF INT
EKEYINT
：
Enable KEYINT
EWDI
：
Enable Watchdog interrupts
EI2CM
：
Enable I2C MASTER MODULE interrupts
EI2CS
：
Enable DI2CS interrupts
ESPI
：
Enable SPI MODULE interrupts
EIP register
(0xF8)
Address/Name R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit
Bit 2
Bit 1
Bit 0
F8h
EIP
Reset
PI2CS
PSPI
0
R/W
PI2CM PWDI PKE
INT PRFINT PINT4 PINT3 PINT2
0
0
0
0
0
0
0
PINT2
：
INT2 priority level control (at 1-high-level)
PINT3
：
INT3/Compare 0 priority level control (at 1-high-lev
PINT4
：
INT4/Compare 1 priority level control (at 1-high-le
PRFINT
：
RFINT priority level control (at 1-high-level
PKEYINT
：
KEYINT priority level control (at 1-high-l
vel)
PWDI
：
Watchdog priority level control (at 1-high-level)
PI2CM
：
I2C MASTER MODULE priority level
ntrol (at 1-high-level)
PI2CS
：
I2C MODULE priority level contro
at 1
high-level)
PSPI
：
SPI MODULE priority level control (at 1-high-level)
EIF register
(0x91)
Address/
ame R/W Bit
7 Bit
6 Bit
5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
91h
EIF
eset
I2CSF
SPIF
0
R/W
I2CMF
0
–
KEYINTF RFINTF INT4F
INT3F INT2F
0
0
0
0
0
0
INT2F
：
INT2 int
upt
lag
Should
e cleared by external hardware when processor branches to interrupt routine. This bit is a copy of INT2 pin
updated every CLK
eriod. It cannot be set by software.
INT3F*
：
T3/Compare 0 interrupt flag
Sho
be cleared by external hardware when processor branches to interrupt routine. t cannot be set by software.
INT4F*
：
INT4/Compare 1 interrupt flag
Should be cleared by external hardware when processor branches to interrupt routine.
It cannot be set by software.
RFINTF
：
RFINT interrupt flag
Must be cleared by software writing 0x08 when controlled by RFINT.
KEYINTF
：
KEYINT interrupt flag
Must be cleared by software writing 0x10 when controlled by KEYINT.
I2CMIF
：
I2C MASTER MODULE interrupt flag
. It must be cleared by software writing 0x40. It cannot be set by software
I2CSIF
：
I2C MODULE interrupt flag
SPIIF
：
SPI MODULE interrupt flag
Software should determine the source of interrupt by checking both modules
’
interrupt related bits. It must be cleared by
software writing 0x80. It cannot be set by software.
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10.5 Reset source
Reset circuitry allows A8105 to be easily placed in a predefined defau
t condition. LVD, Reset, POR, and Watchdog signal will
reset 8153 when they happen.
Power o
Reset
REGI
Internal
Reset
RESETN
eset circuit
w voltage
detecot
REGI
Watchdog timer
Figure 10.2 Reset source
RSFLAG: Reset Fl
g(0xBA):
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2
Bit 1
Bit 0
BAh
RSFLAG
R
–
–
–
–
–
LVDF RESETNF PORF
Reset
0
0
0
0
0
0
0
1
Write any data to RSFLAG to clear all bits.
PORF
(power-on reset flag)
= 1: Occurred Power-on Reset
= 0: No Power-on Reset
RESETNF
(resetn flag)
= 1: Occurred ResetN reset
= 0: No ResetN resetno resetn reset
LVD
(Low voltage detect) flag
= 1: Occurred Low Voltage Reset
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= 0: No Low Voltage reset
Please refer the figure 10.3 and 10.4 for the timing diagram for stable power o
t signal and internal behavior of CPU.
XOUT
REGI
RST1
T
VIH
RESETN
2046 Crystal Clock Cycles
R
T1
T
: According to RESETN’s RC delay (standard module is about 50ms)
Figure 10.3 Timing Diagram for stable power to the release of RESETN
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CPU clock
RESETN
RST2
T
VIH
2046 Crystal Clock Cycles
startup
T
CPU OP Code Fetch
CPU Sta
Running
CPU Stop Running
RST2
T
: 2 Crystal Clock Cycles (min)
: 2046 Crystal Clock Cycles + RESETN’s RC delay (standard mod
le is about 50ms)
startup
T
Figure 10.4 Timing Diagram for
ESETN control sequence
10.6 Clock source
A8105 has three clock source, crystal osc
lla
or (pin 13,14/ Xi, XO), RTC crystal (pin 1,2/ P3.6, P3.7/ RTC_I, RTC_O) and
internal RC oscillator. In the MCU part (digi
l p
ipherals ), user choices the suitable clock source by power consumptions and
performance. In the RF part, the cloc
rce only comes from XO..
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RF
Clock
Generator
XO
0
1
CLKRUN
RTC
IRC
1
0
/1
/2
LK
MCU
Core
CLKCTRL
CLKSEL =7
RTCS
/4
CLKPMM
/8
CLKSEL
/16
/32
/64
PMM STOP
WOR/TWOR
timer
CLK
L = 0 ~6
Figure 10
ole chip clock
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11. I/O Ports
A8105 has two type of digitla I/O Pins. One is 24 pins and the other is 28 pins. In 24pins, there are separated to 3 Ports (Port0,
Port1 and Port3) and each of the Port pin can be defined as general-purpose I/O (GPIO) or peripheral I/O signals connected to
the timers, UART, I2C and SPI functions. In 28pins, there are extra 4pins of Port2 and they are Port2.0 ~ Port2.3. Thus, each
pin can also be used to wake A8105 up from sleep mode. User can select each pin function by setting register. Each port has
itself port register like P0 (0x80), P1 (0x90), P2(0xA0) and P3 (0xB0) that are both byte addressable and bit addressable. When
reading, the logic levels of the Port
’
s input pins are returned. Each port has three registers to setting Pull-up (PUN),
Output-enable (OE) and Wake-up enable (WUN). As shown the bellow block diagram, Fig. 11.1. Unused I/O pins should have a
defined level and not be left floating. One way to do this is to leave the pin unconnected and configure the pin as a
general-purpose I/O input with pull-up resistor.
PUN
DO
P
OE
DI
KEYINT
WUN
Figure
1.1 Ports
I/O block diagram
OE
0
0
P
N
P
1
HZ
DO
DI
1
INH
DO
1
X
1
Tab
1 OE and PUN setting and Output(P) and Input(DI)
WUN
0
1
KEYINT
Enable
Disable
Table 11.2 WUN setting and KEYINT source
11.1 FUNCTIONALITY
It h
hree 8-bit full bi-directional ports, P0, P1 and P3. Each port bit can be individually accessed by bit addressable
instruction
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
80h
R/W
P0
Reset
0
0
0
0
0
0
0
0
Port 0 register
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
90h
R/W
P1
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Reset
0
0
0
0
0
0
0
0
Port 1 register
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
A0h
R/W
P2
Reset
0
0
0
0
0
0
0
0
Port 2 register
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
B0h
R/W
P3
Reset
0
0
0
0
0
0
0
0
Port 3 register
Read and write accesses to the I/O port are performed via their corresponding SFRs P0(0x80), P1(0x90), and P3(0xB0).
Some port
‐
reading instructi
ons read the data register and others read the port’s pin
The “Read
‐
Modify
‐
Write” instructions are
directed to the data registers and are shown below. All the other instructions used to re
d a port e
xclusively read the port’s pin.
Instruction
ANL
Function description
Logic AND
ORL
Logic OR
XRL
JBC
CPL
Logic eXclus
ve OR
Jump if b
t is s
and clear
Complement bit
INC, DEC
DJNZ
Inc
, decrement byte
De
t and jump if not zero
MOV Px.y, C
Move carry bit to y of port x
CLR Px.y
SETB Px.y
Table1
Cle
r bit y of port x
Set bit y of port x
Read-modify-write instructions
According the Table 11.1, all Port pins can be co
figured as Output, Input with the pull-up resistor (around
100
Kohm) or Input.
Please refer the following truth table
w every function setting. When OE=1, this pin is configured as Output. Otherwise OE
=0, this pin is configured as Input. U
set PUN =1 or 0 depending on application. When OE =0, PUN=0 is recommended
for saving power.
All Port pins can wake A8105 up w
en WUEN=0 and configured GPIO. All Port pins
’
WUN signals connect one OR gate to
KEYINT
. It means pin wake up function needs
KEYINT
ISR to take care this interrupt event.
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
D1h
P0OE
R/W
Reset
0
0
0
0
0
0
0
0
Port 0 Output Enable Register
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
D2h
P0PUN
R/W
Reset
0
0
0
0
0
0
0
0
Port 0 Pull Up Register
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
D3h
P0WUN
R/W
Reset
1
1
1
1
1
1
1
1
Port 0 Wake Up Enable Register
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2.4GHz FSK/GFSK SoC
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
D9h
P1OE
R/W
Reset
0
0
0
0
0
0
0
0
Port 1 Output Enable Register
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
DAh
P1PUN
R/W
Reset
0
0
0
0
0
0
0
0
Port 1 Pull Up Register
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
DBh
P1WUN
R/W
Reset
1
1
1
1
1
1
1
1
Port 1 Wake Up Enable Register
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bi
it 2
Bit 1
Bit 0
A1h
P2OE
R/W
Reset
0
0
0
0
0
0
0
0
Port 2 Output E
able
egister
Address/Name R/W Bit
7 Bi
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
A2h
P2PUN
R/W
Reset
0
0
0
0
0
0
0
0
Port 2 Pull Up Register
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
A3h
P2WUN
/W
Reset
1
1
1
1
1
1
1
1
Port 2 Wake Up Enable Register
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
E1h
P3OE
R/W
Reset
0
0
0
0
0
0
0
0
Port 3 Output Enable Register
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
E2h
P3PUN
R/W
Reset
0
0
0
0
0
0
0
0
Port 3Pull Up Register
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
E3h
P3WUN
R/W
Reset
1
1
1
1
1
1
1
1
Port 3 Wake Up Enable Register
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IOSEL Register
(0xBB)
Address/Name R/W Bit
7 Bit
6 Bit
5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BBh
IOSEL
Reset
R/W
–
RADCIOS[1:0]
RTCIOS BBIOS
–
I2CIOS URT0IOS
0
0
0
0
0
0
0
0
RADCIOS1 (RC-ADC1 I/O select)
[0]: Disable RC-ADC1 analog input.
[1]: P1.0, P1.1, P1.2, P1.3 are selected for RC-ADC0 analog input pin.
RADCIOS0 (RC-ADC0 I/O select)
[0]: Disable RC-ADC0 analog input.
[1]: P0.0, P0.1, P0.2, P0.3 are selected for RC-ADC0 analog input pin.
RTCIOS (Real-time clock I/O select)
[1]: The pad is for RTC clock
[0]: The pad is normal I/O
BBIOS (Base band I/O select)
[1]: P0.7, P1.2, P1.3 are selected for
RF GPIO1,GPIO2,CKO function pin
[0]: P0.7, P1.2, P1.3 are normal I/O
I2CIOS (I2C I/O select)
[1]: The pad is selected for I2C (open drain I/O)
[0]: The pad is normal I/O
UARTIOS (UART0 I/O select)
[1]: Port 3.0 and Port3.1 are selected for UART0 mode0 (open drain I/O)
[0]: Port 3.0 and Port3.1 are normal I/O
ADCCH Register
(0xBC)
Address/Name R/W
Bit 7
Bit
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BCh
ADCCH
Reset
R/W
—
0
—
0
—
0
— ADCCH3
ADCCH2 ADCCH1 ADCCH0
0
0
0
0
0
ADCCH[3:1] (ADC I/O select)
[000]: Select P3.2 as ADC analog in
[001]: Select P3.3 as ADC analog inp
[010]: Select P3.4 as ADC an
log input.
[011]: Select P3.5 as ADC ana
og in
ut.
[100]: Select P1.6 as ADC analog input.
[101]: Select P1.7 as ADC ana
og input.
[110]: Select P3.0 as
DC analog input.
[111]: Select P3.1
s ADC analog input.
ADCCCH0
[1]: Enable AD
an
og input
[0]: Disa
ADC
nalog input
11.2 Key interrupt
User can use P0, P1 or P3 port as key input and meanwhile these key are clicked to event a key interrupt to wake up A8105 or
enter key process flow. It is a helpful use to design a remote controller and low power consumption with power saving mode
setting. The KEY INT vector is located on 0x5B. User can put an interrupt service routine in 0x5B.
The KEY interrupts can wake up A8105 back to normal mode in PM1 and PM2. In PM3, Port 3.2~Port 3.5 and RESETN PIN will
reset A8105 and A8105 need to initial all needed peripherals and take care key interrupt event.
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p0wun[0]
p0[0]
p0wun[7]
p0[7]
p1wun[0]
p1[0]
KEYINT
p1wun[7]
p1[7]
p3wun[0]
p3[0]
p3wun[7]
p3[7]
Figur
11.2 Key
interrupt block diagram
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12 Timer0,1 and Timer2
A8105 contains three 16-bit timer/counters, Timer 0, Timer 1 and Timer 2. Timer 0 and Timer 1 in the
“
timer mode
“
, timer
registers are incremented every 4/12/CLK periods depends on CKCON (0x8E) setting, when appropriate timer is enabled. In
the
“
counter mode
”
the timer registers are incremented every falling transition on theirs corresponding input pins: T0 or T1. The
input pins are sampled every CLK period.
The Timer 2 is one of the most powerful peripheral units of the core. It can be used for all kinds of digital signal generation
and event capturing like pulse generation, pulse width modulation, pulse width measuring etc.
12.1 Timer 0 & 1 PINS DESCRIPTION
The pins functionality is described in the following table. All pins are one directional.
PIN
ACTIVE TYPE DESCRIPTION
T0(P3.4)
GATE0(P3.2) High
T1(P3.5)
GATE1(P3.3) High
Falling
Input
Input
Input
Input
Timer 0 clock line
Timer 0 clock line gate control
Timer 1 clock line
Falling
Timer 1clock line gate cont
ol
Table12.1 Timer 0, 1 pins description
12.2 Timer 0 & 1 FUNCTIONALITY
12.2.1 OVERVIEW
Timer 0 and Timer 1 are fully compatible with the standard 8051 timers
Each timer consists of two 8-bit registers TH0
(0x8C), TL0 (0x8A), TH1 (0x8D), TL1 (0x8B). Timers 0, 1 work in the same four modes. The modes are described below.
M1 M0 Mode Function
description
0
0
1
1
0
1
0
1
0
1
2
3
THx operates as 8-bit timer/counter w
de by 32 prescaler served by lower 5-bit of TLx.
16-bit timer/counter. THx and TLx are c
ed.
TLx operates as 8-bit timer/coun
er with 8-bit auto-reload by THx.
TL0 is configured as 8-bit time
/coun
er controlled by the standard Timer 0 bits. TH0 is an 8-bit timer
controlled by the Timer 1 controls bits. Timer 1 holds its count.
Table12.2 Timer 0 and 1 modes
12.2.2 Timer 0 & 1 Registers
TMOD register
(0x89)
Address/Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
89h
TMOD
R/W GATE1
CT
M1
M0 GATE0 CT
M1
M0
Timer 1 control bits
Timer 0 control bits
eset
0
0
0
0
0
0
0
0
GATE
：
Gating c
trol
=1, Timer x
n
bled while GATEx pin is high and TRx control bit is set.
=0, Tim
x e
abled while TRx control bit is set.
CT
：
Counter or
mer select bit
=1,
nter mode, Timer x clock from Tx pin.
=0,
mer mode, internally clocked.
M[1
：
0]
：
Mode select bits
TCON register
(0x88)
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
88h
TCON
Reset
R/W TF1 TR1 TF0 TR0 IE1
IT1
0
IE0
0
IT0
0
0
0
0
0
0
TR0
：
Timer 0 run control bit
=1, enabled.
=0, disabled.
TR1
：
Timer 1 run control bit
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=1, enabled.
=0, disabled.
TF0
：
Timer 0 interrupt (overflow) flag.
Cleared by hardware when processor branches to interrupt routine.
TF1
：
Timer 1 interrupt (overflow) flag.
Cleared by hardware when processor branches to interrupt routine.
CKCON register (0x8E)
Address/Name R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2 Bit 1 Bit 0
8Eh
CKCON
R/W WD1
WD0 T2M T1M T0M
MD2 MD1 MD0
Reset
0
0
0
0
0
0
0
0
T2M
：
This bit controls the division of the system clock that drives Timer 2.
=1, Timer 2 uses a divided-by-4 of the system clock frequency.
=0, Timer 2 uses a divided-by-12 of the system clock frequency.
T1M
：
This bit controls the division of the system clock that drives Timer 1.
=1, Timer 1 uses a divided-by-4 of the system clock frequency.
=0, Timer 1 uses a divided-by-12 of the system clock frequency.
T0M
：
This bit controls the division of the system clock that drives Timer 0.
=1, Timer 0 uses a divided-by-4 of the system clock frequency.
=0, Timer 0 uses a divided-by-12 of the system clock frequency.
IE register (0xA8)
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
A8h
IE
Reset
R/W EA
0
2
0
ES
0
ET1 EX1 ET0 EX0
0
0
0
0
0
EA
：
Enable global interrupts.
ET0
：
Enable Timer 0 interrupts.
ET1
：
Enable Timer 1 interrupts.
IP register (0xB8)
Address/Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
B8h
IP
Rese
–
–
PT2
0
PS
0
PT1
0
PX1
0
PT0
0
PX0
0
0
0
PT0
：
Timer 0 priority le
el control (at 1-high level)
PT1
：
Timer 1 priority le
el co
rol (at 1-high level)
Timer 0
1 re
ated bits that generate interrupts can be set or cleared by software, with the same result as if they had been
set or cleared by ha
dware. That is, interrupts can be generated or pending interrupts can be cancelled by software.
Interrupt flag
Function
Active level/edge
Flag resets
Vector Natural
priority
TF0
TF1
Internal, Timer 0
Internal, Timer 1
–
–
Hardware
Hardware
0x0B
0x1B
2
4
Table12.3
Timer 0, 1 interrupts
12.2.3 Timer 0
–
Mode 0
In this mode, the Timer 0 register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s. Timer 0
interrupt flag TF0 is set. The counted input is enabled to the Timer 0 when TCON.4 = 1 and either TMOD.3 = 1 or GATE0 = 1.
(Setting TMOD.3 = 1 allows the Timer 0 to be controlled by external input GATE0, to facilitate pulse width measurement). The
13-bit register consists of all 8-bit of TH0 and lower 5 bits of TL0.The upper 3 bits of TL0 are indeterminate and should be
ignored.
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Figure12.1 Timer/Counter
0, Mode 0
：
13-Bit Timer/Counter
12.2.4 Timer 0
–
Mode 1
Mode 1 is the same as Mode 0, except that the timer register is running with al
16 bits. Mode 1 is shown in figure below.
Figure
.2 Timer/Counter
0, Mode 1
：
16-Bit Timer/Counter
12.2.5 Timer 0
–
Mode 2
Mode 2 configures the timer reg
as an 8-bit counter (TL0) with automatic reloads, as shown in figure below. Overflow
from TL0 not only sets TF0, b
t also reloads TL0 with the contents of TH0, which is loaded by software. The reload leaves TH0
unchanged.
Figure12.3 Timer/Counter
0, Mode 2
：
8-Bit Timer/Counter with Auto-Reload
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12.2.6 Timer 0
–
Mode 3
Timer 0 in Mode 3 establishes TL0 and TH0 as two separate counters. The logic for Mode 3 on Timer 0 is shown in
figure below. TL0 uses the Timer 0 control bits
：
C/T, GATE, TR0, GATE0 and TF0. TH0 is locked into a timer function and use
the TR1 and TF1 flag from Timer1 and controls Timer1 interrupt. Mode 3 is provided for applications requiring an extra 8-bit
timer/counter. When Timer 0 is in Mode 3, Timer 1 can be turned off by switching it into its own Mode 3, or can still be used by
the serial channel as a baud rate generator, or in any application where interrupt from Timer 1 is not required.
Figure12.4 Timer/Counter
0, Mode 3
：
Two 8-Bit Timers/Counters
12.2.7 Timer 1
–
Mode 0
In this Mode, the Timer1 register is
onfi
ured as a 13-bit register. As the count rolls over from all 1s to all 0s, Timer1
interrupt flag TF1 is set. The counted input i
en
bled to the Timer1 when TCON.6 = 1 and either TMOD.6 = 0 or GATE1 = 1.
(Setting TMOD.7 = 1 allows the Tim
e controlled by external input GATE1, to facilitate pulse width measurements). The
13
‐
bit register consists of all 8 bits o
nd the lower 5 bits of TL1. The upper 3 bits of TL1 are indeterminate and should be
ignored.
Figure12.5 Timer/Counter 1, Mode 0
：
13-Bit Timers/Counters
12.2.8 Timer 1
–
Mode 1
Mode 1 is the same as Mode 0, except that timer register is running with all 16 bits. Mode 1 is shown in figure below.
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Figure12.6 Timer/Counter
1, Mode 0
：
16-Bit Timers/Counter
12.2.9 Timer 1
–
Mode 2
Mode 2 configures the
timer register as an 8-bit counter (TL1) with automatic re
oads, as shown in figure below.
Overflow from TL1 not only sets TF1, but also reloads TL1 with the contents of TH
which is loaded by software. The reload
leaves TH1 unchanged.
Figure12
er/Counter 1, Mode 2
：
8-Bit Timer/Counter with Auto-Reload
12.2.10 Timer 1
–
Mode 3
Timer 1 in Mode 3 is he
d coun
ing. The effect is the same as setting TR1=0.
12.3 Timer2 PINS DESCRIPTION
The Timer 2 pins functionality is described in the following table. All pins are one directional.
PIN
ACTIVE TYPE
DESCRIPTION
t2
(P1.0)
falling
INPUT Timer
2 clock line
t2ex
(P1.1)
high
INPUT Timer
2 control
Table12.4 Compare/Capture pins description
12.4 Timer2 FUNCTIONALITY
12.4.1 OVERVIEW
Timer 2 is fully compatible with the standard 8052 Timer 2. It is up counter. Totally five SFRs control the Timer 2 operation:
TH2/TL2(0xCD/0xCC) counter registers, RCAP2H/RCAP2L (0xCB/0xCA) capture registers and T2CON(0xC8) control register.
Timer 2 works in the three modes selected by T2CON bits as shown in table below.
RCLK, CPRL2 TR2 Function
description
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TCLK
0
0
1
1
1
16-bit auto-reload mode. The Timer 2 overflow sets TF2 bit and the TH2,TL2
registers reloaded 16-bit value from RCAP2H, RCAP2L.
16-bit capture mode. The Timer 2 overflow sets TF2 bit. When the EXEN2 =
1, the TH2, TL2 register values are stored into RCAP2H, RCAP2Lwhile
falling edge is detected on T2EX pin.
0
1
X
X
1
0
Baud rate generator for the UART0 interface. It auto-reloads its counter with
RCAP2H, RCAP2Lvalues each overflows.
Timer 2 is off
X
Table12.5
Timer 2 modes
12.4.2 Timer 2 Registers
T2CON register
(0xC8)
Address/Name R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TF2 EXF2
RCLK TCLK
EXEN2 TR2
CT2 CPRL2
C8h
R/W
APOL
Reset
0
0
0
0
0
0
0
0
EXF2
：
Falling edge indicator on T2EX pin when EXEN = 1. Must be cleared by soft
are.
RCLK
：
Receiver clock enable
=1, UART0 receiver is clocked by Timer 2 overflow pulses
=0, UART0 receiver is clocked by Timer 2 overflow pulses
TCLK
：
Transmit clock enable
=1, UART0 transmitter is clocked by Timer 2 overflow pulses
=0, UART0 transmitter is clocked by Timer 2 overflow pulses
EXEN2
：
Enable T2EX pin functionality.
=1, Allows capture or reload as a result of T2EX pin falling e
ge.
=0, ignore T2EX events
TR2
：
Start / Stop Timer 2
=1, start
=0, stop
CT2
：
Timer / counter select
=1, external event counter. Clock sourc
s T2 pin.
=0, timer 2 internally clocked
CPRL2
：
Capture / Reload select
=1, T2EX pin falling edge caus
pture to occur when EXEN2 = 1
=0, automatic reload occurs o
2 overflow or falling edge T2EX pin when EXEN2 = 1. When RCLK or TCLK is set
this bit is ignored and automati
d on Timer 2 overflow is forced.
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Figure12.8 Timer
2 block
iagram in timer mode
CKCON register (0x8E)
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
8Eh
R/W
D1 WD0 T2M
T1M T0M MD2 MD1 MD0
CKCON
Reset
0
0
0
0
0
0
0
0
T2M
：
This bit controls the division o
stem clock that drives Timer 2. This bit has no effect when the
timer is in baud
rate generator mode.
=1, Timer 2 uses a divid
-by-4 of the system clock frequency.
=0, Timer 2 uses a divid
-by-1
of the system clock frequency.
Timer 2 interrupt re
ated b
s are shown below. An interrupt can be turned on/off by IE (0xA8) register, and set into high/low
priority group by IP r
gist
r.
IE register (0xA8
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
A8h
IE
Reset
R/W EA
0
–
ET2
0
ES
0
ET1 EX1 ET0 EX0
0
0
0
0
0
EA
：
Enable global interrupts.
ET2
：
Enable Timer 2 interrupts.
IP register (0xB8)
Address/Name R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
B8h
IP
Reset
R/W
–
–
PT2
0
PS
0
PT1
0
PX1
0
PT0
0
PX0
0
0
0
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PT2
：
Timer 2 priority level control (at 1-high level)
T2CON register
(0xC8)
Address/Name R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
C8h
T2CON
Reset
R/W
TF2 EXF2
RCLK TCLK
EXEN2 TR2
CT2 CPRL2
0
0
0
0
0
0
0
0
TF2
：
Timer 2 interrupt (overflow) flag. It must be cleared by software.
The flag will not be set when either RCLK or TCLK is set.
All Timer 2 related bits generate interrupts can be set or cleared by software, with the same result as if they had been set or
cleared by hardware. That is, interrupts can be generated or pending interrupts can be cancell
d by software.
Interrupt flag
Function
TF2 Internal,
Timer2
Active level / edge
Flag resets
Vec
tural priority
–
Software
Timer2 interrupt
0x2B
6
Table12.6
Interrupt is also generated at falling edge
of T2EX pin, while EXEN2 bit is s
his i
errupt doesn’t set TF2 flag, but EXF2
only and also uses 0x2B vector. Please see picture below. Timer2 internal lo
igured as baud
‐
rate generator is shwon
below.
Figure12.9 Timer
2 block diagram as UART0 baud rate generator
Please note that SMODbit is ignored by UART when clocked by Timer2. The RLCK/TCLK frequency is equal to
：
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13. UART
UART is full duplex, meaning it can transmit and receive concurrently. It is receive double
‐
buffered, meaning it can
commence reception of a second byte before a previously received byte has been read from the receive register. Writing to
SBUF loads the transmit register, and reading SBUF reads a physically separate receive register. The serial port can operate in
4 modes: one synchronous and three asynchronous modes. Mode 2 and 3 has a special feature for multiprocessor
communications. This feature is enabled by setting SM2 bit in SCON register. The master processor first sends out an address
byte, which identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in
a data byte. With SM2 = 1, no slave will be interrupted by a data byte. An address byte will interrupt all slaves. The addressed
slave will clear its SM2 bit and prepare to receive the data bytes that will be coming. The slaves that were not
eing addressed
leave their SM2 set and ignoring the incoming data.
13.1 UART PINS DESCRIPTION
The UART pins functionality is described in the following table. All pins are one directional
There are no three
‐
state
output pins and internal signals.
PIN
Rxd_0
(P3.0)
Txd_0
(P3.1)
ACTIVE TYPE
–
–
DESCRIPTION
Input / Output
Serial r
iver
_
/ O_0
Output Seria
itter line 0
Table13.1 UART
pins descri
tion
13.2 FUNCTIONALITY
The UART has the same functionality as a standard
1 UART. The UART related registers are: SBUF(0x99), SCON
(0x98), PCON(0x87), IE(0xA8) and IP(0xB8). The UART
ffer (SBUF) consists of two separate registers: transmit and
receive registers. A data writes into the SBUF sets this da
ART output register and starts a transmission. A data reads
from SBUF, reads data from the UART receive regis
er.
SBUF register
(0x99)
Address/Name R/
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
99h
SBUF
/W
Reset
0
0
0
0
0
0
0
0
SBUF[7:0]
：
UART buffer
SCON register
0x98)
Ad
ress/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
98h
SCON
R/W SM00
SM01 SM02
REN
TB8
0
RB8
0
TI
0
RI
0
Reset
0
0
0
0
SM2
：
Enable a multiprocessor communication feature
SM [1:0]
：
Sets baud rate
SM0 SM1 Mode Description
Baud Rate
0
0
1
1
0
1
0
1
0
1
2
3
Shift register
F
CLK
/12
8-bit UART
9-bit UART
9-bit UART
Variable
F
CLK
/32 or F
CLK
/64
Variable
Timer 2 cannot be used as baud rate generator when Compare Capture unit is present in the system. The UART baud
rates are presented in the table below.
Mode
Mode 0
Baud Rate
FCLK/12
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Mode 1, 3
Timer 1 overflow rate
–
T1
ov
SMOD= 0
SMOD= 1
T1
ov
/32
T1
ov
/16
Timer 2 overflow rate
–
T2
ov
SMOD= x
SMOD= 0
SMOD= 1
T2
ov
/16
F
CLK
/64
F
CLK
/32
Mode 2
The SMOD bit is located in PCON register.
REN
：
If set, enable serial reception. Cleared by software to disable reception.
TB8
：
The 9
th
transmitted data bit in Modes 2 and 3. Set or cleared by the MCU, depending on the function it p
rfo
ms (parity
check, multiprocessor communication etc.)
RB8
：
In Modes 2 and 3 it is the 9
th
data bit received. In Mode 1, if SM2 is 0, RB8 is the stop bit. In M
de 0
is bit is not used.
PCON register
(0x87)
Address/Name
87h
R/W
Bit 7
SMOD
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
–
–
PWE
0
–
SW
STOP CKSE
PCON
Reset
0
0
0
0
0
0
SMOD
：
UART double baud rate bit when clocked by Timer 1 only.
UART interrupt related bits are shown below. An interrupt can be turned on / o
f by IE register, and set into high / low priority
group by IP register.
IE register
(0xA8)
Address/Name R/W Bit
7 Bit
it 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
A8h
IE
Reset
R/W EA
0
–
2
0
ES
0
ET1 EX1 ET0 EX0
0
0
0
0
0
ES
：
RI & TI interrupt enable flag
IP register
(0xB8)
Address/Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
B8h
IP
Rese
–
–
PT2
0
PS
0
PT1
0
PX1
0
PT0
0
PX0
0
0
0
PS
：
RI & TI interrupt p
ority flag
SCON register
(0x98)
A
dress/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
98h
SCON
Reset
R/W
SM0
0
SM1
0
SM2 REN
TB8
0
RB8
0
TI
0
RI
0
0
0
TI
：
Transmit interrupt flag, set by hardware after completion of a serial transfer. It must be cleared by software.
RI
：
Receive interrupt flag, set by hardware after completion of a serial reception. It must be cleared by software.
All of bits that generate interrupts can be set or cleared by software, with the same result as if they had been set or cleared by
hardware. That is, interrupts can be generated or pending interrupts can be cancelled by software.
Interrupt flag
Function
Active level / edge
Flag resets
Vector Natural
priority
TI & RI
Internal, UART
Table13.3
–
Software
UART interrupt
0x23
5
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13.3 OPERATING MODES
13.3.1 UART MODE 0, SYNCHRONOUS
Pin RXD0I serves as input and RXD0O as output. TXD0 output is a shift clock. The baud rate is fixed at 1/12 of the CLK
clock frequency. Eight bits are transmitted with LSB first. Reception is initialized by setting the flags in SCON as follows: RI=0
and REN=1.
Figure13.3 UART
transmission mode 0 timing diagram
13.3.2 UART MODE 1, 8-BIT UART, VARIABLE BAUD RATE, TIMER CLOCK SOURCE
Pin RXD0I serves as input, and TXD0 serves as serial output. 10 bits are transmitte
: a start bit (always 0), 8 data bits
(LSB first), and a stop bit (always 1). On receive, a start bit synchronizes the transmission, 8
ata bits are available by reading
SBUF, and stop bit sets the flag RB8 in the SFR SCON. The baud rate is variable an
depends from Timer 1 or Timer 2 mode.
To enable Timer 2 clocking set the TCLK, RCLK bits located in T2CON (0xC8
gist
r. SMOD bit is ignored when UART is
clocked by Timer2.
Figure13.4 UART
transmission mode 1 timing diagram
13.3.3 UART MODE 2, 9
‐
BIT UART, FIXED BAUD RATE
This mode is similar to Mode 1 with two
ferences. The baud rate is fixed at 1/32 or 1/64 of CLK clock frequency, and 11
bits are transmitted or received: a start bit (0), 8 da
a bits (LSB first), a programmable 9
th
bit, and a stop bit (1). The 9
th
bit can be
used to control the parity of the UART inter
ce
t transmission, bit TB8 in SCON is output as the 9
th
bit, and at receive, the 9
th
bit affects RB8 in SCON.
Figure13.5 UART
transmission mode 2 timing diagram
13.3.4
ART MODE 3, 9
‐
BIT UART, VARIABLE BAUD RATE, TIMER CLOCK SOURCE
The
ly difference between Mode 2 and Mode 3 is that the baud rate is a variable in Mode 3. When REN=1 data
receiving is enabled. The baud rate is variable and depends from Timer 1 or Timer 2 mode. To enable Timer 2 clocking set the
TCLK, RCLK bits located in T2CON (0xC8) register. SMOD bit is ignored when UART is clocked by Timer2.
Figure13.6 UART
transmission mode 3 timing diagram
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14. IIC interface
A8105
’
s I
2
C peripheral provides two-wire interface between the device and I
2
C -compatible device by the two-wire I
2
C serial bus.
The I
2
C peripheral supports the following functions.
Conforms to v2.1 of the I
2
C specification (published by Philips Semiconductor)
Master transmitter / receiver
Slave transmitter / receiver
Flexible transmission speed modes: Standard (up to 100 Kb/s) and Fast (up to 400Kb/s)
Multi-master systems supported
Supports 7-bit addressing modes on the I
2
C bus
Interrupt generation
Allows operation from a wide range of input clock frequencies (build-in 8-bit timer)
PIN 23 and PIN 24 are I2C Interface in A8105. The alternate function is Port 0.5 and Port 0.6. Use
ca
set BBSEL (BBH)
to set up the PIN function. Please refer the Chapter 11 for more detail information.
PIN
SCL
(P0.5)
SDA
(P0.6)
TYPE
INPUT /OUTPUT
INPUT/ OUTPUT
DESCRIPTION
I
2
C clock input /output
I
2
C data input /outp
t
Table14.1
I2C interface pins description
14.1 Master mode I
2
C
The I
2
C master mode provides an interface between a microprocessor a
d a
I
2
C bus. It can be programmed to operate
with arbitration and clock synchronization to allow it to operate in multi
‐
aster systems. Master mode I
2
C supports transmission
speeds up to 400Kb/s.
14.1.1 I
2
C REGISTERS
There are six registers used to interface to the host: th
ol, Status, Slave Address, Transmitted Data, Received Data
and Timer Period Register.
Regi
ter
ave address
–
I2CMSA
Control
–
I2CMCR
Address
0xF4
0xF5
Tr
smitted data I2CBUF
Timer period – I2CMTP
Table14.3
0xF6
0xF7
I
2
C Registers for writing
Register
Slave address
–
I2CMSA
Status
–
I2CMSR
Address
0xF4
0xF5
Received data – I2CBUF
0xF6
Timer period – I2CMTP
0xF7
Table14.4
I
2
C Master m
de Timer Period Register
I
2
C Registers for reading
To g
rate wide range of SCL frequencies the core have built
‐
in 8
‐
bit timer. Programming sequence must be done at
least once
ter system reset. After reset, register have 0x01 value by default.
SCL_PERIOD = 2 x (1+TIMER_PRD) x (SCL_LP + SCL_HP) x CLK_PRD
For example
：
– CLK_PRD = 62.5ns (CLK_FRQ = 16MHz)
；
– TIMER_PRD =3
；
– SCL_LP = 6
；
(fixed)
– SCL_HP = 4; (fixed)
SCL_PERIOD = 2 x (1 + 3) x (6 + 4 ) x 62.5ns = 5000ns = 5us
SCL_FREQUENCY = 1 / 5us = 200 KHz
SCL_PRD
– SCL line period (I2C clock line)
TIMER PRD
-Timer period register value (range 1 to 255)
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CLK_PRD
– System clock period (1/f
clk
)
I2CMTP
(0xE7)
Address/Name R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
E7h
I2CMTP
Reset
R/W
0
0
P.6
0
P.5
0
P.4
0
P.3
0
P.2
0
P.1
0
P.0
1
I
2
C CONTROL AND STATUS REGISTERS
The Control Register consists of eight bits: the RUN, START, STOP, ACK, HS, ADDR, SLRST and R
TB bit.
e RSTB bit
performs reset of whole I
2
C controller and behaves identically as external reset provided by RST pin. U
this bit software
application can reinitialize I
2
C mater module when some problem is encountered on I
2
C bus. In cas
wh
n I
2
C Slave device
blocks I
2
C bus, then SLRST bit should be set along with RUN bit (just after issuing the RSTB
SLR
T bit causes that I
2
C
master module generates 9 SCK clocks (no START is generated) to recover Slave device to known state and issues at the end
STOP. This bit is automatically cleared by I2C MASTER MODULE
, thus, it is always read as ‘0’. The BUSY bit should be
checked to know when this transmission is ended.
The START bit will cause the generation of the START, or REPEATED START conditi
n. The STOP bit determines if the
cycle will stop at the end of the data cycle, or continue on to a burst. To generate a si
gle send cycle, the Slave Address register
is written with the des
ired address, the R/S bit is set to ‘0’, and Control Register
wri
ten with HS=0, ACK=x, STOP=1,
START=1, RUN=1 (binary xxx0x111 x
‐
mean 0 or 1) to perform the operation
top
When the operation is completed (or
aborted due an error), the interrupt is generated. The data may be read from
ved Data Register. When I2C MASTER
MODULE core operates in Master receiver mode the ACK bit must be set
orm
y to logic 1. This cause the I2C MASTER
MODULE bus controller to send acknowledge automatically after each byte.
his bit must be reset when the I2C MASTER
MODULE bus controller requires no further data to be sent from slave tr
smitter.
The ADDR bit along with RUN bit cause the generation of the S
AR
condition and transmission of Slave Address. Next
STOP can end transmission, or REPEATED START generates
e
ART and ADDRRESS sequence once again. In both
cases STOP can ends transmission. See I
2
C MASTER MODULE ACK Polling chapter for details.
I2CMCR
(0xF5)
Address/Name R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ACK STOP
START RUN
F5h
R/W
STB SLRST ADDR
HS
I2CMCR
Reset
0
0
0
0
0
0
0
0
RSTB SLRST ADDR HS R/
K STOP START RUN OPERATION
0
0
0
0
0
0
1
1
START condition followed by SEND (Master remains
in Transmitter mode)
0
0
0
0
0
–
1
1
1
START condition followed by SEND and STOP
condition
0
0
0
0
1
0
0
1
1
START condition followed by RECEIVE operation
with
negative Acknowledge
(Master remains in
Receiver mode)
0
0
0
0
0
0
1
1
0
1
1
0
1
1
1
1
START condition followed by RECEIVE and STOP
condition
START condition followed by RECEIVE (Master
remains in Receiver mode)
forbidden sequence
Master Code sending and switching to High
‐
speed
mode
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
0
1
1
1
0
0
1
0
0
–
0
–
0
–
0
–
0
–
0
–
1
I2CM module software reset
Reset slaves connected to I2C bus by generating 9
SCK clocks followed by STOP
0
0
1
0
0
0
0
0
1
START condition followed by Slave Address
Table14.5
Control bits combinations permitted in IDLE state *
RSTB SLRST ADDR HS R/S ACK STOP START RUN OPERATION
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0
0
0
0
–
–
0
0
1
SEND operation (Master remains in Transmitter
mode)
0
0
0
0
0
0
0
0
0
0
0
0
–
–
0
–
–
–
1
1
0
0
0
1
0
1
1
STOP condition
SEND followed by STOP condition
Repeated S
T
ART condition followed by SEND
(Master remains in Transmitter mode)
Repeated S
T
ART condition followed by SEND and
STOP condition
Repeated S
T
ART condition followed by RECEIVE
operation with
negative Acknow
edge
(Master
remains in Receiver mode)
0
0
0
0
0
0
0
0
0
1
–
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
1
1
1
1
Repeated S
T
ART condition fol
d by SEND and
STOP condition
Repeated S
T
ART con
ition f
lowed by RECEIVE
(Master remains in Receiver mode)
forbidden sequence
I2CM module so
are
eset
Repeated S
T
ART condition followed by Slave
Address
0
1
0
0
0
0
0
0
1
0
–
0
1
–
0
1
–
–
1
–
0
1
–
1
1
–
1
Table14.6
Control bits combinations permitted in M
er Tr
nsmitter mode
RSTB SLRST ADDR HS R/S ACK STOP START RUN OP
RA
ON
RECE
VE operation with
negative Acknowledge
(Master remains in Receiver mode)
STOP condition**
RECEIVE followed by STOP condition
RECEIVE operation (Master remains in Receiver
mode)
0
0
0
0
–
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
–
–
–
–
0
1
1
1
0
0
0
0
0
1
1
forbidden sequence
0
0
0
0
0
0
0
0
–
1
1
0
1
0
0
1
1
1
Repeated S
T
ART condition followed by RECEIVE
operation with
negative Acknowledge
(Master
remains in Receiver mode)
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
–
1
1
0
0
0
1
0
0
1
–
1
1
1
1
–
1
1
1
1
–
Repeated S
T
ART condition followed by RECEIVE
and STOP condition
Repeated S
T
ART condition followed by RECEIVE
(Master remains in Receiver mode)
Repeated S
T
ART condition followed by SEND
(Master remains in Transmitter mode)
Repeated S
T
ART condition followed by SEND and
STOP condition
–
–
–
I2CM module software reset
Table14.7
Control bits combinations permitted in Master Receiver mode
The status Registe
is consisted of six bits
：
the BUSY bit, the ERROR bit, the ADDR_ACK bit, the DATA_ACK bit, the
ARB_LO
it, and the IDLE bit.
I2CMSR
(0xF5)
Address/Name R/W
Bit 7
Bit 6
BUS_
BUSY
0
Bit 5
IDLE
1
Bit 4
ARB_
LOST
0
Bit 3
DATA_
ACK
0
Bit 2
ADDR_
ACK
0
Bit 1
ERROR
0
Bit 0
BUSY
0
F5h
I2CMSR
R/W
–
Reset
0x20
0
IDLE
：
This bit indicates that I2C BUS controller is in the IDLE state
。
BUSY
：
This bit indicates that I2C BUS controller receiving, or transmitting data on the bus, and other bits of Status register are
no valid;
BUS_BUSY
：
This bit indicates that the Bus is Busy, and access is not possible. This bit is set / reset by START and STOP
conditions;
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ERROR
：
This bit indicates that due the last operation an error occurred: slave address wasn
’
t acknowledged,
transmitted
data wasn
’
t acknowledged, or I2C Bus controller lost the arbitration;
ADDR_ACK
：
This bit indicates that due the last operation slave address wasn
’
t acknowledged;
ARB_LOST
：
This bit indicates that due the last operation I2C Bus controller lost the arbitration;
SLAVE ADDRESS REGISTER
The Slave address Register consists of eight bits
：
Seven address bits (A6-A0), and Receive/ not send bit R/S. The R/S bit
determines if the next operation will be a Receive (high), or Send (low).
I2CMSA
(0xF4)
Address/Name R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
F4h
I2CMCA
Reset
R/W
A.6
0
A.5
0
A.4
0
A.3
0
A.2
0
A.1
0
A.0
0
R/
0
I
2
C Buffer
–
RECEIVER AND TRANSMITTER REGISTERS
I2C module has two separated 1 byte buffer in receiver and transmitter and these are lo
ated in the same address (0xF6).
The Transmitted Data Register consists of eight data bits which will be sent on the bus due the next Send, or Burst Send
operation. The first send bit is D.7 (MSB).
I2CBUF
(0xF6)
Address/Name R/W
Bit 7
Bit 6
Bit 5
B
t 4
Bit 3
Bit 2
Bit 1
Bit 0
F6h
I2CBUF
Reset
R/W
D.7
0
D.6
0
D.5
0
D.4
D.3
0
D.2
0
D.1
0
D.P
0
The Receiver Data Register consists of eight data bits w
ve been received on the bus due the last receive, or Burst
Receive operation.
I2CBUF
(0xF6)
Address/Name R/W
i
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
F6h
I2CBUF
Reset
R/W
7
0
D.6
0
D.5
0
D.4
0
D.3
0
D.2
0
D.1
0
D.P
0
14.2.4 I2C MASTER MOD
LE AVAILABLE SPEED MODES
Default transmission parameter
constant values are shown in sections below. SCL clock frequency can be changed by
modification of timer per
od values as show in the table below.
I2C MASTER MODULE STANDARD MODE
Typical confi
ratio
values for Standard speed mode
：
The followi
g t
le gives an example parameters for standard I2C speed mode.
System clock
TIMER_PERIOD Transmission
speed
4 MHz
6 MHz
10 MHz
16 MHz
20 MHz
1 (01h)
2 (02h)
4 (04h)
7 (07h)
9 (09h)
100kb/s
100kb/s
100kb/s
100kb/s
100kb/s
Table14.8
I2C MASTER MODULE Timer period values for standard speed mode
I2C MASTER MODULE FAST MODE
Typical configuration values for Fast speed mode
：
The following table gives example parameters for Fast I2C speed mode.
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System clock
TIMER_PERIOD Transmission
speed
10 MHz
16 MHz
20 MHz
1 (01h)
1 (01h)
2 (02h)
250 Kb/s
400 Kb/s
333 Kb/s
Table14.8 I2C
MASTER MODULE Timer period values for Fast speed mode
14.2.5 I2C MASTER MODULE AVAILABLE COMMAND SEQUENCES
I2C MASTER MODULE SINGLE SEND
IDLE
Write Slave Address
to
I2CSA
register
Write Data to
I2CBUF
register
This sequence may be omitte
in single-Master sys
s
Read
I2CCR
register
NO
Bus Busy=“0”
YES
Write ,,—0-111”to
I2CCR
register
Read
I2CCR
reg
ster
NO
Bus
usy
“0”
YES
YES
NO
Error =“0”
IDLE
Error service
IDLE
Figure14.4 I2C
MASTER MODULE Single SEND flowchart
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I2C MASTER MODULE SINGLE RECEIVE
IDLE
Write Slave Address
to
I2CSA
register
This sequence may be omitted
in single-Master systems
Read
I2CCR
register
NO
Bus Busy=“0”
YES
Write ,,—00111”to
I2CCR
register
Read
I2CCR
register
NO
Bus Busy=“0”
YES
YES
Error =“0”
Read Data from
I2CBUF
register
Error service
IDLE
ID
Figure14.5 Single
RECEIVE flowchart
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I2C MASTER MODULE BURST SEND
IDLE
Write Slave Address
to
I2CSA
register
Write Data to
I2CBUF
register
This sequence may be omitted
in single-Master systems
Read
I2CCR
register
NO
Bus Busy=“0”
YES
Write ,,—0-011”to
I2CCR
register
Read
I2CCR
register
NO
Bus Busy=“0”
YES
NO
Error =“0”
YES
NO
Arb_Lost =‘1’
Write Da
a to
I2CBUF
re
ister
Write ,,—0-100”to
I2CCR
register
YES
NO
YES
I
dex = n
Error service
IDLE
Error service
IDLE
Write ,,–
I2CCR
Write ,,—0-101”to
I2CCR
register
Read
I2CCR
register
NO
Bus Busy=“0”
YES
YES
NO
Error =“0”
IDLE
Error service
IDLE
Figure14.6 I2C
MASTER MODULE Sending n bytes flowchart
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I2C MASTER MODULE BURST RECEIVE
IDLE
This sequence may be omitted
in single-Master systems
Write Slave Address
to
I2CSA
register
Read
I2CCR
register
NO
Bus Busy=“0”
YES
Write ,,—01011”to
I2CCR
register
Read
I2CCR
register
NO
Bus Busy=“0”
YES
NO
Error =“0”
YES
NO
Arb_Lost =‘1’
Read Data f
m
I2CBUF
re
ister
Write ,,—0-100”to
I2CCR
register
YES
NO
YES
Error service
IDLE
Error service
IDLE
Ind
x = m-1
Write ,,—01
I2CCR
r
Write ,,—00101”to
I2CCR
register
Read
I2CCR
register
NO
Bus Busy=“0”
YES
YES
Read Data from
NO
Error =“0”
Error service
IDLE
I2CBUF
register
IDLE
Figure14.7 I2C
MASTER MODULE Receiving m bytes flowchart
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I2C MASTER MODULE BURST RECEIVE AFTER BURST SEND
Figure14.8 I2C
MASTER MODULE
ending n bytes then Repeated Start and Receiving m bytes flowchart
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I2C MASTER MODULE BURST SEND AFTER BURST RECEIVE
Figure14.9 I2C
MAST
ODULE Receiving m bytes then Repeated Start and Sending n bytes flowchart
igure14.10 I2C
MASTER MODULE Single RECEIVE with 10-bit addressing flowchart
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I2C MASTER MODULE ACK POLLING
IDLE
Write Slave Address
to
I2CSA
register
Read
I2CCR
register
NO
BUS BUSY= ‘0’
YES
Write ,,00100001″ to
I2CCR
register
Read
I2CCR
register
NO
BUSY= ‘0’
YES
NO
A
R_ACK=‘0’
YE
Burst S
op
Write ,,00100011″ to
I2CCR
register
Read
I2CCR
register
NO
BUSY= ‘0’
YES
YES
NO
ADDR_ACK=‘0’
Burst Send or Stop
Figure14.11 I2C
MASTER MODULE ACK Polling flowchart
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14.3 I2C MASTER MODULE INTERRUPT GENER
A
TION
I2C MASTER MODULE interrupt flag is automatically asserted when I2C transfer (send or receive a byte) is completed or
transfer error has occurred. I2CMIF flag has to be cleared by software.
Interrupt flag
Function
I2CMIF Internal,
I2C MASTER MODULE
Table14.11 I2C
MASTER MODULE interrupt summary
Active level/edge
Flag resets
Vector Natural
priority
–
Software 0x6B
14
I2C MASTER MODULE related interrupt bits have been summarized below. The IE (0xA8) contains global i
terrupt system
disable (0) / enable (1) bit called EA.
EIE (0xE8)
Address/Name R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
E8h
EIE
Reset
EI2CS
ESPI
0
R/W
EI2CM EWDI EKEYINT ERFINT EINT4 EINT3 EINT2
0
0
0
0
0
0
0
EI2CM
：
Enable I2C MASTER MODULE interrupts
EIP (0xF8)
Address/Name R/W
Bit 7
Bit 6
Bit 5
Bi
4
Bi
3 Bit
2 Bit
1 Bit
0
F8h
EIP
Reset
PI2CS
PSPI
0
R/W
PI2CM PWDI PK
YIN
PRFINT PINT4 PINT3 PINT2
0
0
0
0
0
0
0
PI2CM
：
I2C MASTER MODULE priority level control (at 1
vel)
EIF
(0x91)
Address/Name R/W
B
7 Bit
6 Bit
5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
91h
EIF
Reset
I2CSF
SP
0
R/W
I2CMF
0
–
KEYINTF RFINTF INT4F
INT3F INT2F
0
0
0
0
0
0
I2CMIF
：
I2C MASTER MODULE inte
flag
It must be cleared by so
tware writing logic
‘
1
’
. Writing
‘
0
’
does not change its content.
14.5 Slave mode I
2
C
The I
2
C modu
e
rovides an interface between a microprocessor and I
2
C bus. It can works as a slave receiver or transmitter
depending on
ork
ng mode determined by microprocessor/microcontroller. The core incorporates all features required by I
2
C
specification. Th
I
2
C module supports all the transmission modes: Standard and Fast.
14.5.1 I2
MODULE INTERNAL REGISTERS
There
re five registers used to interface to the target device
：
The Own Address, Control, Status, Transmitted Data and
Received Data registers.
Register
Own address
–
I2CSOA
Control
–
I2CSCR
Address
0xF1
0xF2
Transmitted data
–
I2CSBUF 0xF3
Table14.12 I2C
MODULE Registers for writing
Register
Own address
–
I2CSOA
Control
–
I2CSSR
Address
0xF1
0xF2
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Received data
–
I2CSBUF 0xF3
Table14.13 I2C
MODULE Registers for reading
I2CSOA
–
OWN ADDRESS REGISTER
The Own Address Register consists of seven address bits which identify I
2
C module core on I
2
C Bus. This register can be
read and written at the address 0xF1.
I2CSOA (0xF1)
Address/Name R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
F1h
I2CSOA
Reset
R/W
–
A.6
0
A.5
0
A.4
0
A.3
0
A.2
0
A.1
0
A0
0
0
I2CSCR
–
CONTROL AND STATUS REGISTERS
The Control Register consists of the bits
：
The RSTB and DA bit. The RSTB bit performs rese
of whole I
2
C controller and
behaves identically as external reset provided by RST pin. Using this bit software application can rei
itialize I
2
C module when
some problem is encountered on I
2
C bus. The DA bit enables (
‘
1
’
) and disable (
‘
0
’
) the I
2
C mod
le device operation. DA is set
immediately to
‘
1
’
when MCU write DA=1. This register can be only written at address 0xF
Reading this address puts status
register on data bus
–
see below.
I2CSCR
(0xF2)
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4
Bit
Bit 2
Bit 1
Bit 0
F2h
I2CSCR
R/W RSTB DA
–
–
R
CFINCLR SENDFINCLR
–
–
Reset
0
0
0
0
0
0
0
0
DA
：
Device Active
–
enable or disable the I
2
C module device oper
tion;
RSTB
：
Reset of whole I
2
C controller by writing
‘
1
’
to this b
haves identically as RST pin
RECFINCLR
：
Writing
‘
1
’
to this bit clears RECFIN bit from
C MODULE status register.
SENDFINCLR
：
Writing
‘
1
’
to this bit clears SENDFIN bit from the I2C MODULE status register.
The Status Register consists of five bits:
he DA, BUSACTIVE, RECFIN, SENDFIN bit, RREQ bit, TREQ bit. The receive
finished RECFIN bit indicates that Master I
C controller has finished transmitting of data during single or burst receive
operations. It also causes generation of
ter
upt on IRQ pin. The send finished SENDFIN bit indicates that Master I2C
controller has finished receiving of data durin
single or burst send operations. It also causes generation of interrupt on IRQ pin.
The Receive Request RREQ bit in
that I
2
C module device has received data byte from I2C master. I
2
C module host
device (usually MCU) should read o
byte from the Received Data register I2CSBUF. The Transmit Request TREQ bit
indicates that I2C MODULE d
vice is addressed as Slave Transmitter and I
2
C module host device (usually MCU) should write
one data byte into the Transm
ted D
ta register I2CSBUF. The
BUSACTIVE ‘1’ signalizes that any transmission (send, receive
or own address detection) is in progress. BUSACTIVE is cleared (‘0’) automatically by
I
2
C module in case when there is no any
transmission. This is re
d only bit.
The DA bit should be p
lled (read) when MCU wrote DA=0. The DA bit is not immediately cleared when any I2C
transmission (sen
, receive or own address detection) is in progress. When current transmission has completed then this bit is
cleared to ‘0’ and
C module become inactive.
I2CSSR
(0xF2)
Address/Name R/W Bit
7 Bit
6 Bit
5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
F2h
I2CSSR
Reset
R/W
DA
0
–
BUSACTIVE RECFIN SENDFIN TREQ RREQ
0
0
0
0
0
0
0
DA
：
Device Active
–
enable (
‘
1
’
) or disable (
‘
0
’
) the I2C MODULE device operation;
BUSACTIVE
：
Bus ACTIVE
– ‘
1
’
signalizes that any transmission: send, receive or own address detection
is in progress;
RREQ
：
Indicates that I
2
C module device has received data byte from I
2
C master;
It is automatically cleared by read of I2CSBUF.
TREQ
：
Indicates that I
2
C module device is addressed as transmitter and requires data byte from host device;
It is automatically cleared by write data I2CSBUF.
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RECFIN
：
Indicates that Master I2C controller has ended transmit operation. It means that no more RREQ
will be set during
this single or burst I
2
C module receive operation. It is cleared by writing
‘
1
’
to the
RECFINCLR bit in the I
2
C module control
register.
SENDFIN
：
Indicates that Master I2C controller has ended receive operation. It means that no more
TREQ will be set during
this single or burst I
2
C module send operation. It is cleared by writing
‘
1
’
to the SENDFINCLR bit in the I2C control register.
NOTE
：
All bits are active at HIGH level (
‘
1
’
).
I2CSBUF
–
RECEIVER AND TRANSMITTER REGISTERS
The Transmitter Data Register consists of eight Data bits which will be sent on the bus due the next Send operation. The
first send bit is the D.7(MSB).
I2CSBUF (0xF3)
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
F3h
I2CSBUF
Reset
R/W
D.7
0
D.6
0
D.5
0
D.4
0
D.3
0
D.2
0
D.
0
D.
0
The Receiver Data Register consists of eight data bits which have been receive
on
e bus due the last Receive
operation.
I2CSBUF (0xF3)
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4
Bit 2
Bit 1
Bit 0
F3h
I2CSBUF
Reset
R/W
D.7
0
D.6
0
D.5
0
D.4
D.3
0
D.2
0
D.1
0
D.0
0
14.7
A
VAILABLE I2C MODULE TRANSMISSIO
DES
This chapter describes all available transmission modes
he I
2
C module core. Default I2C own address for all presented
waveforms is 0x39 (
“
0111001
”
).
14.7.1 I
2
C module SINGLE RECEIVE
The figure below shows a set of sequenc
during Single data Receive by I2C MODULE. Single receive sequences
：
Start condition
I
2
C module is addressed by I2C Ma
er as receiver
Address is acknowledged
2
C module
Data is received by I
2
C
Data is acknowledged by
odule
Stop condition
14.7.2 I
2
C module SINGLE SEND
The figure below shows a
et of sequences during Single data Send by I2C MODULE. Single send sequences
：
Start cond
tion
I
2
C m
ule i
addressed by I2C Master as transmitter
A
dres
is acknowledged by I
2
C module
Data is
ansmitted by I
2
C module
Data is not acknowledged by I2C Master
top condition
14.7.3 I
2
C module BURST RECEIVE
The figure below shows a set of sequences during Burst data Receive by I
2
C module. Burst receive sequences
：
Start condition
I
2
C module is addressed by I2C Master as receiver
Address is acknowledged by I
2
C module
(1)Data is received by I
2
C module
(2)Data is acknowledged by I
2
C module
STOP condition
Sequences (1) and (2) are repeated until Stop condition occurs.
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14.7.4 I
2
C module BURST SEND
The figure below shows a set of sequences during Burst Data Send by I
2
C module. Burst send sequences
：
Start condition
I
2
C module is addressed by I2C Master as transmitter
Address is acknowledged by I
2
C module
(1)Data is transmitted by I
2
C module
(2)Data is acknowledged by I2C Master
(3)Last data is not acknowledged by I2C Master
Stop condition
Sequences (1) and (2) are repeated until last transmitted data is not acknowledged (3) by I2C Master.
14.7.5 AVAILABLE I
2
C module COMMAND SEQUENCES FLOWCHART
IDLE
software rese
Write own Address to
I2CSOA
register
Write ,,1——-“ to
I2CSCR
register
Write ,,01——“ to
I2CSCR
register
Read
I2CSCR
register
YES
RR
1’
Read data from
I2CSBUF
register
NO
YES
TREQ = ‘1’
write data
to
NO
I2CSBUF
register
YES
SENDFIN = ‘1’
(Burst) Send is done
Clear SENDFIN bit
NO
YES
RECFIN = ‘1’
(Burst) Receive is
done
NO
Clear RECFIN bit
Figure14.20 Available
I2C MODULE command sequences flowchart
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14.8 I2C MODULE INTERRUPT GENER
A
TION
I2C MODULE interrupt flag is automatically asserted when I2C transfer (send or receive a byte) is completed or transfer
error has occurred. I2CSIF flag has to be cleared by software.
Interrupt flag
Function
I2CSIF Internal,
DI2CS
Table14.16
Active level/edge
Flag resets
Vector Natural
priority
Software 0x73
15
I2C MODULE interrupt summary
–
I2C MODULE related interrupt bits have been summarized below. The IE (0xA8) contains global interrupt
ystem disable (0)
/ enable (1) bit called EA.
EIE (0xE8)
Address/Name R/W Bit
7 Bit
6 Bit
5
Bit 4
Bit 3
Bit 2
Bi
1 Bi
0
E8h
EIE
Reset
EI2CS
ESPI
0
R/W
EI2CM EWDI EKEYINT
ERFINT EINT4
EINT3 EINT2
0
0
0
0
0
0
EI2CS
：
Enable I2C MODULE interrupts
EIP (0xF8)
Address/Name R/W Bit
7 Bit
6 Bit
5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
F8h
EIP
PI2CS
PSPI
R/W
PI2CM PWDI PKEY
NT PRFINT PINT4
PINT3 PINT2
Reset
0
0
0
0
0
0
0
0
PI2CS
：
I2C MODULE priority level control (at 1-high-le
EIF (0x91)
Address/Name R/W B
t 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
91h
EIF
I2CS
SP
F
R/W
I2CMF
–
KEYINTF RFINTF
INT4F INT3F INT2F
Reset
0
0
0
0
0
0
0
0
I2CSIF
：
I2C MODULE interr
pt flag
Software should determ
ne th
source of interrupt by check both modules
’
interrupt related bits. It must be cleared by
software writing 0x80. It cannot be set by software.
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15. SPI interface
The SPI is a fully configurable SPI master/slave device, which allows user to configure polarity and phase of serial clock
signal SCK.
The SPI allows the microcontroller to communicate with serial peripheral devices. It is also capable of inter-processor
communications in a multi
‐
master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on
the two independent serial data lines. SPI data are simultaneously transmitted and received.
The SPI is a technology independent design that can be implemented in a variety of process technologies.
The SPI system is flexible enough to interface directly with numerous standard product periphera
s from several
manufacturers. The system can be configured as a master or a slave device. Data rates as high as System clock d
v
ded by four
(CLK/4). Clock control logic allows a selection of clock polarity and a choice of two fundamentally different
king protocols to
accommodate most available synchronous serial peripheral devices. When the SPI is configured as a mas
r, software selects
one of four different bit rates for the serial clock.
The SPI automatically drive selected by SSCR (Slave Select Control Register) slave select o
tputs (SS7O
–
SS0O), and
address SPI slave device to exchange serially shifted data.
Error
‐
detection logic is included to support inter-processor communications. A write
collis
n detector indicates when an
attempt is made to write data to the serial shift register while a transfer is in progress. A m
ltiple
‐
master mode
‐
fault detector
automatically disables SPI output drivers if more than one SPI devices simultaneous
attempts to be become bus master.
15.1 KEY FE
A
T
URES
All features listed
elow
re included in the current version of SPI core.
SPI Master
F
l du
le
synchronous serial data transfer
Ma
ter
peration
Multi-master system supported
p to 8 SPI slaves can be addressed
System error detection
Interrupt generation
Supports speeds up to 1/4 up to system clock
Bit rates generated 1/4, 1/8, 1/32, 1/64, 1/128, 1/512 of system clock
Four transfer formats supported
Simple interface allows easy connection to microcontrollers
SPI Slave
Full duplex synchronous serial data transfer
Slave operation
System error detection
Interrupt generation
Supports speeds up to 1/4 of system clock
Simple interface allows easy connection to microcontrollers
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Four transfer formats supported
Fully synthesizable, static synchronous design with no internal tri-states
15.2 SPI PINS DESCRIPTION
PIN
TYPE
ACTIVE
DESCRIPTION
Scki_Scko
(P0.0)
INPUT / OUTPUT
–
SPI clock input / output
MISO
(P0.1)
SIMO
(P0.2)
SSO
(P0.3)
INPUT / OUTPUT
INPUT / OUTPUT
OUTPUT
–
–
Master serial data input / Slave serial data output
Slave serial data input / Master serial data output
Slave select output
low
Table15.1
SPI pins description
15.3 SPI HARDWARE DESCRIPTION
15.3.1 BLOCK DIAGRAM
When an SPI transfer occurs, an 8
‐
bit character is shifted out on data pin while a different 8
bit character is simultaneously
shifted in a second data pin. Another way to view this transfer is that an 8
‐
bit shift register i
the master and another 8
‐
bit shift
register in the slave are connected as a circular 16
‐
bit shift register. When a trans
er occurs, this distributed shift register is
shifted eight bit positions; thus, the characters in the master and slave are effectively e
cha
ged.
The central element in the SPI system is the block containing the shift r
an
the read data buffer. The system is
single buffered in the transmit direction and double buffered in the receive dire
his fact means new data for transmission
cannot be written to the shifter until the previous transaction is complete; howev
received data is transferred into a parallel
read data buffer so the shifter is free to accept a second serial character. As long as the first character is read out of the read
data buffer before the next serial character is ready to be transferred, no
verrun condition will occur.
Figure 15.2
SPI Block Diagram
The eight pins are associated with the SPI: the SS, clock pins SCKI, SCKO and SCKEN, master pins MI and MO and slave
pins SOEN, SI and SO.
The SS input pin in a master mode is used to detect mode
‐
fault errors. A low on this pin indicates that some other device in
a multi
‐
master system has become a master and trying to select the SPI MODULE as a slave. The SS input pin in a slave mode
is used to enable transfer.
The SCKI pin is used when the SPI is configured as a slave. The input clock from a master synchronizes data transfer
between a master and the slave devices. The slave device ignore the SCKI signal unless the SS (slave select) pin is active low.
The SCKO and SCKEN pins are used as the SPI clock signal reference in a master mode. When the master initiates a
transfer eight clock cycles is automatically generated on the SCKO pin.
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When the SPI is configured as a slave the SI pin is the slave input data line, and the SO is the slave output data line.
When the SPI is configured as a master, the MI pin is the master input data line, and the MO is the master output data line.
15.3.2 INTERNAL REGISTERS
SPI Control Register
The control register may be read or written at any time, is used to configure the SPI System.
SPCR
(0xEC)
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
ECh
R/W SPIE SPE
SPR2 MSTR CPOL CPHA SPR1 SPR0
EIE
Reset
0
0
0
0
0
1
0
0
SPIE
：
SPI interrupt enable
= 0, interrupts are disabled, polling mode is used
= 1, interrupts are enabled
SPE
：
SPI system enable
= 0, system is off
= 1, system is on
MSTR
：
Master/Slave mode select
= 0, slave
= 1, master
CPOL
：
Clock polarity select
= 0, high level; SCK idle low
= 1, low level; SCK idle high
CPHA
：
Clock phase.
. Select one of two different transfer formats
SPR[2:0]
：
SPI clock rate select bits.
See the table below
SPR2 SPR1 SPR0 System
clock divided by
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4
8
16
32
64
128
256
Slave Select Control Register
The control register may
e read or written at any time. It is used to configure which slave select output should be driven
while SPI master transfer. C
nten
s of SSCR register is automatically assigned on SS7O
‐
SS0O pins when SPI master
transmission starts.
SSCR
(0xEF)
Addr
ss/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
EFh
SSCR
Reset
R/W
SS7
1
SS6
1
SS5
1
SS4
1
SS3
1
SS2
1
SS1
1
SS0
1
SS7
–
SS
= 0, P
n SSxO assigned while Master Transfer
= 1, Pin SSxO is forced to logic 1
SPSR
SPI Status Register
(0xED)
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
EDh R/W
SPIF WCOL
MODF SSCEN
–
–
–
–
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EIE
Reset
0
0
0
0
0
1
0
0
SPIF
：
SPI interrupt request. The flag is automatically set to one at the end of an SPI transfer.
WCOL
：
Write collision error status flag. The flag is automatically set if the SPDR is written while a transfer
is in process.
MODF
：
SPI mode-fault error status flag
This flag is set if SS pin goes to active low while the SPI is configured as a master (MSTR = 1)
SSCEN
：
= 1, auto SS assertions enabled
= 0, auto SS assertions disabled
–
SSO always shows contents of SSCR
SPI status register (SPSR) contains flags indicating the completion of transfer or occurrence of system
rrors. All flags are
set automatically when the corresponding event occur and cleared by software sequence. SPIF and WCO
are automatically
cleared by reading SPSR followed by an access of the SPDR. MODF flag is cleared by reading SPSR wit
MODF set followed
by a write to SPCR.
The SSCSEN bit is a enable bit of automatic Slave Select Outputs assertion. When SSCEN is set (‘1’) then during master
transmission the SSXO lines are automatically loaded with contents of SSCR register befor
each
yte transfer, and deasserted
when byte is transferred. When SSCEN bit is cleared the SSXO lines always shows contents of the SSCR register, regardless
of the transmission is in progress or SPI MODULE is in IDLE state.
Receiver and Transmitter Registers
The Transmitted Data Register consists of eight data bits, which will be
on the bus due the next Send operation.
The first send bit is the D.7 (MSB).
SPDR (0xEE)
Address/Name R/W Bit
7 Bit
6 Bit
5 Bi
4 Bit
3 Bit
2 Bit
1 Bit
0
EEh
SPDR
R/W
D.7
0
D.6
0
D
4
0
D.3
0
D.2
1
D.1
0
D.0
0
Reset
The Received Data Register consists of eight data b
s, which were received on the bus due the last Receive operation.
SPDR (0xEE)
Address/Name R/W
it 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EEh
SPDR
R/W
D.7
0
D.6
0
D.5
0
D.4
0
D.3
0
D.2
1
D.1
0
D.0
0
Reset
15.4 MASTER OPER
A
TIONS
When the SP
MO
ULE core is configured as a SPI master, the transfer is initiated by write to the SPDR register. When the
new byte is writte
to the SPDR register, SPI MODULE begins transfer on the nearest BAUD timer overflow. The serial clock
SCK is gene
ed
y the SPI MODULE. In master mode the SPI MODULE activates the SCKEN to enable the SCK output
driver.
The
MODULE in master mode can select one of the eight SPI slave devices, through the SSxO lines. The SSxO lines
–
Slave Sel
output lines are loaded with contents of the SSCR register (0x03). The SSCEN bit from the SPSR register select
between au
omatic SSxO lines control and software control. When set the automatic Slave Select outputs assertion is enabled.
With SSCEN bit set in master mode the SSXO lines are automatically loaded with contents of SSCR register before each byte
transfer, and deasserted when byte is transferred. When SSCEN bit is cleared the SSXO lines are controlled by the software,
and always shows contents of the SSCR register, regardless of the transmission is in progress or the SPI MODULE is in IDLE
state.
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Figure15.3 Automatic
slave select lines assertion
Figure15.4 Sof
ontrolled SSxO lines
15.4.1 MASTER MODE ERRORS
In master mode two system errors can be dete
ted b
the SPI MODULE. The first type of error arises in multiple
‐
master
system when more than one SPI device simultaneousl
tries to be a master. This error is called a Mode Fault. The second error
type, a Write Collision, indicates that MCU trie
to write the SPDR register while transfer was in progress.
MODE FAULT ERROR
Mode fault error occurs when the
MODULE is configured as a master and some other SPI master device will select this
device as if it were a slave. If a Mod
Error occur
：
The MSTR bit is forced to
to reconfigure the SPI MODULE as a slave.
The SPE bit is for
ed to zero to disable the SPI MODULE system
The MODF status
ag is set and an interrupt request is generated
The MODF flag is cleared by r
ading SPSR with MODF set followed by a write to SPCR
Figure15.5
Mode Fault Error generation
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WRITE-COLLISION ERROR
A write collision occurs if the SPI MODULE data register is written while a transfer is in progress. The transfer continues
undisturbed, and the write data that caused the error is not written to the shifter. The Write Collision is indicated by the WCOL
flag in SPSR (3) register.
The WCOL flag is set automatically by hardware, when the WCOL error condition occurs. To clear the WCOL bit, user
should execute the following sequence:
Read contents of the SPSR register
Perform access to the SPDR register ( read or write )
Figure15.6 Write
Collision Error in SPI
ast
de
15.5 SL
A
V
E OPER
A
T
IONS
When configured as SPI Slave the SPI MODULE transfer is
tiat
by external SPI master module by assertion of the SPI
MODULE Slave Select input, and generation of the SCK serial cloc
.
Before transfer starts, the SPI master has to assert
ve Select line to determine which SPI slave will be used to
exchange data. The SS is asserted (cleared = 0), the clo
al connected to the SXCK line will cause the SPI MODULE
slave to shift into receiver shift register contents of th
MOSI line, and drives the MISO line with contents of the Transmitter Shift
register. When all eight bits are shifted in/out the SP
MOD
LE generates the Interrupt request by setting the IRQ output.
In SPI MODULE slave mode only one transfer err
r is possible
–
Write Collision Error.
15.5.1 SLAVE MODE ERRORS
In slave mode, only the Write Collisio
Error can be detected by the SPI MODULE.
The Write Collision Error occurs when t
e S
DR register write is performed while the SPI MODULE transfer is in progress.
In SLAVE mode when the CPHA
ared, the write collision error may occur as long as the SS Slave Select line is driven
low, even if all bits are already trans
This is because there is not clearly specified the transfer beginning, and SS driven
low after full byte transfer may indicat
inning of the next byte transfer.
WRITE-COLLISION ER
OR
A write collision oc
urs if the SPI MODULE data register is written while a transfer is in progress. The transfer continues
undisturbed, and the wr
e dat
that caused the error is not written to the shifter. The Write Collision is indicated by the
W
C
OL
flag in SPSR (3) regis
er.
The WCOL f
is
et automatically by hardware, when the WCOL error condition occurs. To clear the WCLO bit, user
should execu
the fol
owing sequence:
Re
d c
ntents of the SPSR register
Perfo
m access to the SPDR register ( read or write )
Figure15.7 Write
Collision Error
–
SPI Slave mode
–
SPDR write during transfer
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Figure below shows the WCOL generation, in case that the CPHA is cleared. As it is shown the WCOL generation is cause
by any S{DR register write with SS line cleared. It is done even if the SPI master didn’t generate the serial clock SCK. This
is
because there is not clearly specified the transfer beginning, and SS driven low after full byte transfer may indicate beginning of
the next byte transfer.
Figure15.8 WCOL
Error-SPI Slave mode-SPDR write when CPHA = 0 and SS = 0
15.6 CLOCK CONTROL LOGIC
15.6.1 SPI CLOCK PHASE AND POLARITY CONTROLS
Software can select any of four combinations of serial clock (SCK) pha
e and polarity using two bits in the SPI control
register (SPCR). The clock polarity is specified by the CPOL control bit
which selects an active high or active low clock and has
no significant effect on the transfer format. The clock phase (CP
A) c
ntrol bit selects one of two fundamentally different
transfer formats. The clock phase and polarity should be identical f
the master SPI device and the communicating slave
device. In some cases, the phase and polarity are changed betw
en transfers to allow a master device to communicate with
peripheral slaves having different requirements. The flexibi
the SPI system on the SPI MODULE allows direct interface to
almost any existing synchronous serial peripheral.
15.6.2 SPI MODULE TRANSFER FORMATS
During an SPI transfer, data is simultaneously
ransmitted (shifted out serially) and received (shifted in serially). A serial
clock line synchronizes shifting and sampling of the in
orm
tion on the two serial data lines. A slave select line allows individual
selection of a slave SPI device; slave device
that are not selected do not interfere with SPI bus activities. On a master SPI
device, the slave select line can optionally be u
ed to indicate a multiple
‐
master bus contention.
15.6.3 CPHA EQUALS ZERO TRANS
ER FORMAT
Figure below shows a timing dia
of an SPI transfer where CPHA is 0. Two waveforms are shown for SCK: one for
CPOL equals 0 and another for CPO
s 1. The diagram may be interpreted as a master or slave timing diagram since the
SCK, master in/slave out (MISO), and
er out/slave in (MOSI) pins are directly connected between the master and the slave.
The MISO signal is the output
rom the slave, and the MOSI signal is the output from the master. The SS line is the slave select
input to the slave; the SS pin o
the
aster is not shown but is assumed to be inactive. The SS pin of the master must be high.
This timing diagram functionally depicts how a transfer takes place; it should not be used as a replacement for data
‐
sheet
parametric information.
Figure15.9 CPHA
Equals Zero SPI Transfer Format
When CPHA = 0, the SS line must be disserted and reasserted between each successive serial byte. Also, if the slave
writes data to the SPI data register (SPDR) while SS is active low, a write
‐
collision error results. When CPHA = 1, the SS line
may remain active low between successive transfers (can be tied low at all times). This format is sometimes preferred in
systems having a
single fixed master and a single slave driving the MISO data line.
15.6.4 CPHA EQUALS ONE TRANSFER FORMAT
Figure below is a timing diagram of an SPI transfer where CPHA = 1. Two waveforms are shown for SCK: one for CPOL =
0 and another for CPOL = 1. The diagram may be interpreted as a master or slave timing diagram since the SCK, MISO, and
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MOSI pins are directly connected between the master and the slave. The MISO signal is the output from the slave, and the
MOSI signal is the output from the master. The SS line is the slave select input to the slave; the SS pin of the master is not
shown but is assumed to be inactive. The SS pin of the master must be high or must be reconfigured as a general
‐
purpose
output not affecting the SPI.
Figure15.10 CPHA
Equals One SPI Transfer Format
15.7 SPI D
A
TA TRANSFER
15.7.1 TRANSFER BEGINNING PERIOD ( INITIATION DELAY )
All SPI transfers are started and controlled by a master SPI device. As a
he SPI MODULE considers a transfer to
begin with the first SCK edge or the falling edge of SS, depending on the CPH
at selected. When CPHA = 0, the falling
edge of SS indicates the beginning of a transfer. When CPHA = 1, the first edg
on
he SCK indicates the start of the transfer. In
either CPHA format, a transfer can be aborted by taking the SS line hi
h, which causes the SPI slave logic and bit counters to
be reset. The SCK rate selected has no effect on slave operations s
nce
e clock from the master is controlling transfers.
When the SPI is configured as a master, transfers are started by a software write to the SPDR.
15.7.2 TRANSFER ENDING PERIOD
An SPI transfer is technically complete when the SPI
set, but, depending on the configuration of the SPI system,
there may be additional tasks. Because the SPI bit rate do
not affect timing of the ending period, only the fastest rate is
considered in discussions of the ending period. Wh
n the SPI is configured as a master, SPIF is set at the end of the eighth
SCK cycle. When CPHA equals 1, SCK is inactive fo
the l
st half of the eighth SCK cycle.
When the SPI is operating as a slave, the
nding period is different because the SCK line can be asynchronous to the MCU
clocks of the slave and because the slave doe
not have access to as much information about SCK cycles as the master. For
example, when CPHA = 1, where the last
CK edge occurs in the middle of the eighth SCK cycle, the slave has no way of
knowing when the end of the last SCK
ycle is. For these reasons, the slave considers the transfer complete after the last bit of
serial data has been sampled, which
ponds to the middle of the eighth SCK cycle.
The SPIF flag is set at the end o
sfer, but the slave is not permitted to write new data to the SPDR while the SS line is
still low.
15.8 TIMING DIAGRAM
15.8.1 MASTER TRANSMISSION
Figure15.11 Master
mode timing diagram
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15.8.2 SLAVE TRANSMISSION
At a beginning of transfer in Slave mode, the data on serial output (MISO) appears on first rising edge after falling edge on
Slave Select (SS) line. Next bits of serial data are driving into MISO line on first rising edge of CLK after SKC active edge (in this
case rising edge of SCK).
Figure15.12 Slave
mode timing diagram
15.9 SPI MODULE INTERRUPT GENER
A
TION
When interrupt is enabled (SPIE bit in SPCR=1), SPI interrupt flag is aut
ma
y asserted when SPI transfer is completed
or transfer error has occurred. SPIIF flag has to be cleared by software.
Figure15.13 Interrupt
generation
Interrupt flag
SPIIF
Function
Internal, SP
Active level/edge
–
Flag resets
Software
Vector
0x73
Natural priority
15
Table15.2
SPI interrupt summary
SPI related interrupt bits have been summarized below. The IE (0xA8) contains global interrupt system disable (0) / enable (1)
bit called EA.
EIE (0xE8)
ddress/Name R/W Bit
7 Bit
6 Bit
5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EI2CS
ESPI
E8h
EIE
R/W
EI2CM EWDI EKEYINT
ERFINT EINT4
EINT3 EINT2
Reset
ESPI
：
Enable SPI Interrupts
EIP (0xF8)
0
0
0
0
0
0
0
0
Address/Name R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PI2CS
PSPI
F8h
EIP
R/W
PI2CM PWDI PKEYINT
PRFINT PINT4
PINT3 PINT2
Reset
0
0
0
0
0
0
0
0
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PSPI
：
SPI priority level control (at 1-high-level)
EIF (0x91)
Address/Name R/W Bit
7 Bit
6 Bit
5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
91h
EIF
I2CSF
SPIF
R/W
I2CMF
–
KEYINTF RFINTF
INT4F INT3F INT2F
Reset
0
0
0
0
0
0
0
0
SPIIF
：
SPI interrupt flag
It must be cleared by software
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16. PWM
A8105 has two channels Pulse width modulator (PWM) output. Every channel PWM has an 8-bit counter with comparator,
a control register (PWMxCON) and two setting registers (PWMxH and PWMxL). User can select clock source by setting
PWMxCON. Enable PWM output and function by setting PWMxEN = 1; otherwise disable PWM output and function by setting
PWMxEN =0. When user set PWMxEN=0, it output LOW single and reload the PWMxL to itself. When the counter is enabled
and matches the content of PWMxH, its output is asserted HIGH; when the counter is overflow, its output is asserted LOW and
reload PWMxL to itself. The pulse frequency and the duty cycle for 8-bit PWM is given by the below equation
Pulse frequency = System clock / 2
pwxclk+1
/ (255-PWMxL)
Duty cycle = (255-PWMxH) / 255-PWMxL)
Noted: PWMxH must be larger then PWMxL. Otherwise, PWM output always is LOW.
16.1 PWM FUNCTIONALITY
PWMxL
/2
PWM counter
/4
CLK
/8
PWxCL
PWM Output
8-bit comparator
/16
/32
PWMxH
PWMxCON
Figure16.1 PWM
Block Digram
The PWM
ins functionality is described in the following table. All pins are one directional.
PIN
ACTIVE TYPE
DESCRIPTION
PWM0
(P1.6)
PWM1
(P1.7)
OUTPUT PWM
0 output
OUTPUT PWM
1 output
PWM PIN define
Table16.1
16.1.1 PWM Registers
PWM0/1 is new design from AMICCOM. They can output pulse width modulation. User adjusts to duty cycle by setting
PWMxH. PWM counter is up counter. PWM counter is not access directly by MCU. User can set or reset PWM counter by
setting PWMxCON. When PWMxEN =1, PWM counter start to count. When PWMxEN=0, PWM counter stop counting and
reload PWMxL to itself. PWxCLK is clock divider. It divide system clock to 2,4,8,16 ,32
and 64 by setting PWxCLK.
Bit Bit Bit Bit
Address/Name R/W
Bit 7
6
5
4
3
Bit 2
Bit 1
Bit 0
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A9h
PWM0CON
Reset
R/W PWM0EN
–
–
–
– PW0CLK2
PW0CLK1 PW0CLK0
0
0
0
0
0
0
0
0
PWM0CON: PWM channel 0 control register
PWM0EN: PWM Channel 0 Enable,
[0]
: Disable.
[1]
: Enable.
PWM0CLK[2:0]: PWM Channel 0 Clock select
[000]
: MCU Clock /2
[001]
: MCU Clock / 4
[010]:
MCU Clock / 8
[011]
: MCU Clock / 16
[100]
: MCU Clock / 32
[101]
: MCU Clock / 64
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
AAh
PWM0H
R/W
Reset
0
0
0
0
0
0
0
PWM0H: PWM channel 0 output HIGH
er
Address/Name R/W Bit
7 Bit
6 Bit
5
it 4
Bi
3 Bit
2 Bit
1 Bit
0
ABh
PWM0L
R/W
Reset
0
0
0
0
0
0
PWM0L: PWM chann
equency setting register
Bit B
Bit Bit
Address/Name R/W
Bit 7
6
5
4
3
Bit 2
Bit 1
Bit 0
B0h
PWM1CON
R/W PWM1EN
–
–
–
– PW1CLK2
PW1CLK1 PW1CLK0
Reset
0
0
0
0
0
0
0
0
PWM1
ON: PWM channel 1 control register
PWM1EN: PWM Channel 1 Enable,
[0]
: Disable.
[1]
: Enable.
PWM1CLK[2:0]: PWM Chan
el 1 Clock select
[000]
: MCU Clock / 2
[001]
: MCU Clock / 4
[010]:
MCU Clock / 8
[011]
: MCU Clock / 1
[100]
: MCU Clock
32
[101]
: MCU C
ock
64
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
B1h
PWM1H
R/W
Reset
0
0
0
0
0
0
0
0
PWM1H: PWM channel 1 output HIGH register
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
B2h
PWM1L
R/W
Reset
0
0
0
0
0
0
0
0
PWM1L: PWM channel 1 frequency setting register
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17. Watchdog Timer
A8105 has a special timer, called Watchdog Timer. It is a useful programmable clock counter that serves as a time-base
generator, an event timer or system supervisor. User can use be a very long timer with disabled reset function.
17.1 Watchdog timer overview
As can be seen in the figure below, the watchdog timer is driven by the main system clock that is supplied to a series of dividers.
The divider output is selectable and determines interval between timeouts. When the timeout is reached, an interrupt flag will
cause an interrupt to occur if its individual enable bit is set and the global interrupt enable is set. The reset and interrupt are
discrete functions that may be acknowledged or ignored, together or separately for various applications.
Figure 17.1 Wat
Timer architecture
17.2 Watchdog interrupt
WATCHDOG interrupt related bits are shown below.
n int
rrupt can be turned on/off by EIE register, and set into high/low
priority group by EIP register. The IE contains
lobal interrupt system disable (0) / enable (1) bit called EA.
IE register (0xA8)
Address/Na
R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
A8h
IE
Reset
R/W EA
0
–
ET2
0
ES
0
ET1 EX1 ET0 EX0
0
0
0
0
0
EA
：
Enable global interrupts.
EIE (0xE8)
Address/Name R/W Bit
7 Bit
6 Bit
5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
E8h
EIE
Reset
EI2CS
ESPI
0
R/W
EI2CM EWDI EKEYINT ERFINT EINT4 EINT3 EINT2
0
0
0
0
0
0
0
EWDI
：
En
ble Watchdog interrupts
EIP (0xF8)
Address/Name R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
F8h
EIP
Reset
PI2CS
PSPI
0
R/W
PI2CM PWDI PKEYINT
PRFINT PINT4 PINT3 PINT2
0
0
0
0
0
0
0
PWDI
：
Enable Watchdog priority level control (at 1-high-level)
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
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D8h
WDCON
Reset
R/W
–
–
–
–
WDIF WTRF EWT
RWT
0
0
0
0
0
0
0
0
WDIF
：
Watchdog Interrupt Flag.
WDIF in conjunction with the Enable Watchdog Interrupt bit (EXIE.5), and EWT, indicates if
watchdog timer event has occurred and what action should be taken. This bit must be cleared by software before exiting the
interrupt service routine, or another interrupt is generated. Setting WDIF in software will generate a watchdog interrupt if
enabled. Timed access registers procedure can be used to modify this bit.
All of bits that generate interrupts can be set or cleared by software, with the same result as if they had been set or cleared by
hardware. That is, interrupts can be generated or pending interrupts can be cancelled by software. The
Watc
dog interrupt
vector is located in 0x63. User can put interrupt service routine to take care watchdog interrupt event.
17.3 Watchdog Timer reset
The Watchdog Timer Reset function works as follows. After initializing the correct timeout inter
al, sof
ware first restarts the
Watchdog using RWT and then enables the reset mode by setting the Enable Watchdog Timer Reset (WDCON.1) bit. At any
time prior to reaching its user selected terminal value, software can set the Reset Watchdog
imer (WDCON.0) bit. If RWT is
set before the timeout is reached, the timer will start over. If the timeout is reached witho
RW
being set, the Watchdog will
reset the MCU. Hardware will automatically clear RWT after software sets it. When the reset
ccurs, the Watchdog Timer Reset
Flag (WDCON.2) will automatically be set to indicate the cause of the reset, howeve
software must clear this bit manually.
17.4 SIMPLE TIMER
The Watchdog Timer is a free running timer. When used as a simple timer with
he reset (EWT=0) and interrupt functions
disabled (EWDI=0), the timer will continue to set the Watchdog Interrupt flag eac
ime the timer completes the selected timer
interval as programmed by WD[1:0]. Restarting the timer using the RW
bit, allows software to use the timer in a polled timeout
mode. The WDIF bit is cleared by software or any reset. The Watchdo
nterrupt is also available for applications that do not
need a true Watchdog Reset but simply a very long timer. The interru
t is
nabled using the Enable Watchdog Timer Interrupt
(EIE.4) bit. When the timeout occurs, the Watchdog Timer will s
the
DIF bit (WDCON.3), and an interrupt will occur if the
global interrupt enable (EA) is set.
A potential Watchdog
set is executed 512 clocks after setting of WDIF flag
. The
Watchdog Interrupt Flag indicates the source of the interr
software must clear WDIF flag. Proper use of the Watchdog
Interrupt with the Watchdog Reset allows interrupt software
vey the system for errant conditions.
17.5 SYSTEM MONITOR
When using the Watchdog Timer as a system monitor, the Watchdog Reset function should be used. If the Interrupt function
were used, the purpose of the watchdog woul
e defeated. For example, assume the system is executing errant code prior to
the Watchdog Interrupt. The interrupt wou
tempo
arily force the system back into control by vectoring the MCU to the interrupt
service routine. Restarting the Watchdog an
ex
ng by an RETI or RET, would return the processor to the lost position prior to
the interrupt. By using the Watchdog
function, the processor is restarted from the beginning of the program, and therefore
placed into a known state.
17.6 WATCHDOG RELAT
D REGISTERS
The watchdog timer has severa
SFR bits that contribute to its operation. It can be enabled to function as either a reset source,
interrupt source, softwa
e polled timer or any combination of the three. Both the reset and interrupt have status flags. The
watchdog also has a bit
hat restarts the timer. A summary table showing the bit locations is below. A description follows.
t n
me
EWDI
PWDI
WD[1:0]
RWT
EWT
WTRF
WDIF
Register
EIE
EIP
CKCON
WDCON
Bit position
EIE.5
EIP.5
CKCON.7-6
WDCON.0
WDCON.1
WDCON.2
WDCON.3
Description
Enable Watchdog Timer Interrupt
Priority of Watchdog Timer Interrupt
Watchdog Interval
Reset Watchdog Timer
Enable Watchdog Timer Reset
Watchdog Timer Reset flag
Watchdog Interrupt flag
A Watchdog timeout reset will not disable the Watchdog Timer, but restarts the timer. In general, software should set the
Watchdog to whichever state is desired, just to be certain of its state. Control bits that support Watchdog operation are
described in next subchapters.
17.6.1. WATCHDOG CONTROL
Watchdog control bits are described below. Please note that access (write) to this register has to be performed using Timed
access registers procedure.
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Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
D8h
WDCON
Reset
R/W
–
–
–
–
WDIF WTRF EWT
RWT
0
0
0
0
0
0
0
0
WDIF
：
Watchdog Interrupt Flag.
WDIF in conjunction with the Enable Watchdog Interrupt bit (EXIE.5), and EWT, indicates if
watchdog
mer event has
occurred and what action should be taken. This bit must be cleared by software before exiting the interr
pt servi
e routine, or
another interrupt is generated. Setting WDIF in software will generate a watchdog interrupt if enabled. Ti
ccess registers
procedure can be used to modify this bit.
WTRF
：
Watchdog Timer Reset Flag
.
When set by hardware, indicates that a watchdog timer reset has occurred. Set by software d
not generate a watchdog timer
reset. It is cleared by RESET pin, but otherwise must be cleared by software. The watchdo
ime
has no effect on this bit, when
EWT bit is cleared.
EWT
：
Enable Watchdog Timer Reset.
The reset of microcontroller by watchdog timer is controlled by this bit. This bit
effect on the ability of the watchdog timer
to generate a watchdog interrupt. Timed Access procedure must be used to mo
s bit.
0: watchdog timer timeou
t doesn’t reset microcontroller
1: watchdog timer timeout resets microcontroller
RWT
：
Reset Watchdog Timer.
Setting RWT resets the watchdog timer count. Timed Access pro
dur
must be used to set this bit before the watchdog timer
expires, or a watchdog timer reset and/or interrupt will be ge
ted if enabled.
17.6.2 CLOCK CONTROL
The Watchdog timeout selection is made using bits WD[1:0] as shown in the figure.
CKCON register (0x8E)
Address/Name R/
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2 Bit 1 Bit 0
8Eh
R/W WD1
WD0 T2M T1M T0M
MD2 MD1 MD0
CKCON
Re
0
0
0
0
0
0
0
0
Clock control register CKCON(0x8E)
ns WD[1:0] bits select Watchdog timer timeout period. The Watchdog is clocked
directly from CLK pin, and CK
E directly affects its timeout period. It is increased 256 times slower when the core is enabled
CKSE. This allows the watchd
g per
od to remain synchronized with device operation. Number of clocks needed for timeout
does not depend on CKSE, and is constant as shown in table below. The Watchdog has four timeout selections based on the
input CLK clock frequency as
hown in the figure. The selections are a pre-selected number of clocks. Therefore, the
actual timeout interva
is dependent on the CLK frequency.
WD[1:0]
00
Watchdog interval
Number of clocks
131072
2
17
2
20
2
23
2
26
01
10
11
1048576
8388608
67108864
Note that the periods shown above are for the interrupt events. The Reset, when enabled, is generated 512 clocks later
regardless of whether the interrupt is used. Therefore, the actual Watchdog timeout period is the number shown above plus 512
clocks (always CLK pin).
17.7 TIMED ACCESS REGISTERS
Timed Access registers have built in mechanism preventing them from accidental writes. TA is located at 0xEB SFR address.
To do a correct write to such register the following sequence has to be applied:
CLR
EA ;disable interrupt system
MOV
TA, #0xAA
MOV
TA, #0x55
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; Any direct addressing instruction writing timed access register.
SETB
EA ;Enable interrupt system
The time elapsed between first, second, and third operation does not matter (any number of Program Wait Sates is allowed).
The only correct sequence is required. Any third instruction causes protection mechanism to be turned on. This means that time
protected register is opened for write only for single instruction. Reading from such register is never protected. WDCON (D8h) is
Timed Access register.
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18. ADC (Analog to Digital Converter)
A8105 has two built-in ADCs. One is 8-bits ADC do RSSI measurement as well as carrier detection function. The 8-bit ADC
converting time is 20 x ADC clock periods. The other is 8-channel 12-bits SAR ADC.
18.1 8-bits ADC
Bit
Mode
XADS
0
RSS
1
Standby
None
RX
RSSI / Carrier detect
T
a
ble 17.1 Setting of ADC function
Relative Control Register
Mode Control Register (Address: 0802h)
Bit
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bi
Bit 2
Bit 1
Bit 0
R
W
ARSSI
ARSSI
0
AIF
AIF
0
CD
DFCD
0
W
WWS
FMT
FMT
0
FMS
FMS
0
ADCM
ADCM
0
Name
Reset
ADC Register (Address: 0821h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
W
ADC7
RTH7
1
ADC6
RTH6
0
ADC
RTH
0
ADC4
RTH4
1
ADC3
RTH3
0
ADC2
RTH2
0
ADC1
RTH1
0
ADC0
RTH0
1
RSSI Threshold
Reset
ADC Control Register (Address: 0822h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADC Control
Reset
W
RSM1
0
RSM0
1
ERSS
0
FSARS
1
—
—
XADS
0
RSS
1
CDM
1
18.1.1 RSSI Measuremen
A8105 supports 8-bits
igital RSSI to detect RF signal strength. RSSI value is stored in ADC [7:0] (1Dh). Fig 17.1 shows a
typical plot of RSSI r
adi
g as a function of input power. This curve is base on the current gain setting of A8105 reference code.
A8105 automatic
ly a
erages 8-times ADC conversion a RSSI measurement until A8105 exits RX mode. Therefore, each
RSSI measuring time is ( 8 x 20 x F
ADC
). Be aware RSSI accuracy is about ± 6dBm.
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25
℃
_U-8_RSSI with AGC (1M) L2H
350
300
250
200
150
100
50
RSSI AGC
normal AGC
AGC Fix
0
-110
-100
-90
-80
-70
-60
-50
-40
0
-10
0
10
Input Power (dBm)
Figure 18.1 Typical RSSI c
aracteri
ic.
Auto RSSI measurement for TX Power:
1.
2.
3.
4.
5.
6.
Set wanted F
RXLO
Set RSS= 1 (822h), FSARS= 1 (822h, 4MHz ADC cloc
Enable ARSSI= 1 (802h).
Send RX Strobe command.
In RX mode, 8-times average a RSSI measurement periodically.
Exit RX mode, user can read digital RSSI valu
from ADC [8:0] (1Dh) for TX power.
In step 6, if A8105 is set in direct mode, MCU
all let A8105 exit RX mode within 40 us to prevent RSSI inaccuracy.
Strobe CMD
(SCS,SCK,SDIO)
RX-Stro
RX Mode
MCU Read ADC[7:0]
R
Ready Time
RF-IN
Received Packet
Read 8-bits RSSI value
GIO1 Pin – WTR
(GPIO1S[3:0]=00
)
GIO2 Pin
YNC
(GPIO2S[3:0]
001)
T0
T1
T2
T4
T3
T0-T1: Settling
Time
T2-T3: Receiving
Packet
T3
: Exit
RX mode automatically in FIFO mode
T3-T4: MCU
read RSSI value @ ADC [7:0]
Figure 18.2 RSSI Measurement of TX Power.
Auto RSSI measurement for Background Power:
1.
2.
3.
4.
Set wanted F
RXLO
Set RSS= 1 (822h), FSARS= 0 (822h, 4MHz ADC clock).
Enable ARSSI= 1 (802h).
Send RX Strobe command.
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5.
6.
7.
MCU delays min. 140us.
Read digital RSSI value from ADC [8:0] (in 0x81DH and 0x821h) to get background power.
Send other Strobe command to let A8105 exit RX mode.
Strobe CMD
(SCS,SCK,SDIO)
RX-Strobe
MCU Read ADC[7:0]
No Packet
RFI Pin
Min. 140 us
GIO1 Pin – WTR
(GPIO1S[3:0]=0000)
MCU reads 8-bits RSSI value that
is refresh every 40 u
GIO2 Pin – FSYNC
(GPIO2S[3:0]=0001)
T0
T1
T0-T1: MCU
Delay Loop from PLL to RX mode for RSSI measurmen
T1
: Auto
RSSI Measurment is done by 8-times average.
MCU can read RSSI value from ADC [7:0]
Figure 18.3 RSSI Measurement of B
ckground Power.
18.1.2 Carrier Detect
Base on RSSI measurement, user can extend its application
do carrier detect (CD). In Carrier Detect mode, RSSI is refresh
every 5 us without 8-times average. If RSSI level is below
d level (RTH), CD is output high to GIO1 or GIO2 pin to
inform MCU that current channel is busy.
Below is a reference procedure:
1.
2.
Set CDTH (0821h) for absolute RSSI th
hold level (ex. RTH = 80d).
Set GIO2S = [0010] (080Eh) for Car
r D
te
t to GIO2 pin.
(2-1) Set
wanted F
RXLO
(2-2) Set
RSM= [11] (0822h,
0 and hysteresis =6, or CDM =1 and hysteresis =12).
(2-3) Enable
ARSSI= 1 (802h
(2-4) Send
RX Strobe command
(2-5) MCU
enables a
mer delay (min. 100 us).
MCU checks GIO2 pin.
(3-1) If
ADC
≧
CDTH, GIO2 = 0.
(3-2) If
ADC
≦
C
TH-CDM, GIO2 = 1.
(3-3) If ADC loca
es in hysteresis zone, GIO2 = previous state.
Exit RX mo
e.
3.
4.
18.2 12-b
s SAR ADC
A8105 includes a 12-bit successive approximation A/D converter which enables channel selection from 8 channels. The
A/D converter has two operating modes: single mode and continuous mode. The 12-bits A/D converter can be used to perform
the analog input of the specified channel or temperature sensor. Fig 18.5 shows a typical plot of temperature reading for 12-bit
ADC.
Bit
Mode
DTMP BUFS
0
1
0
1
Analog Input
Temperature Sensor
T
a
ble 18.2 Setting of 12-bit ADC function
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The conversion time in single mode can be determined as follows:
1
1
t
conv
32
4
MHz CKS
[
1
:
0
]
t
conv
SARE
A/D converter
operation
Waiting for conversion
A/D conversion
Waiting
conversio
Co
ersio
Result
ADC output
OKADB
Figure 18.4 Single Mode for A/D Conversion.
Measurement for Analog Input:
1. Set
ADCCH (0xBCh) for selecting ADC channel.
2. Set
ENADC (0x85Bh) to enable the SAR ADC.
3. Set
MODE (0x85Ah) to select single mode or continuous mode.
4. Enable
ADCE = 1 (0x85Ah)
Measurement for Temperature:
1. Set
ENADC (0x85Bh) to enable the SAR ADC.
2. Set
BUFS = 1 (0x85Ah)
3. Set
DTMP = 1 (0x85B) to enable the temperat
re sensor for 12-bit ADC.
4. Set
MODE (0x85Ah) to select single mode or contin
ous mode.
5. Enable
ADCE = 1 (0x85Ah)
Temperature 12bit ADC value
2100
2000
1900
1800
1700
1600
1500
1400
1300
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
Temperature (
℃
)
Figure 18.5 Typical 12-bit ADC temperature sensor characteristic curve.
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19. Battery Detect
A8105 has a built-in battery detector to check supply voltage (REGI pin). The detecting range is 1.8V ~ 2.5V in 8 levels.
Relative Control Register
Battery detect Register (Address: 082Bh)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
R
RGS
RGV1
RGV1
0
RGV0
RGV0
0
PACTL
BDF
0
BVT2
BVT2
0
BVT1
BVT1
1
BVT0
BVT0
1
BDS
DS
0
Battery detect
Reset
—
0
BVT[1:0]: Battery detection threshold.
[000]: 1
.8V.
[001]: 1
.9V.
[010]:
2.0V.
[011]:
2.1V.
[100]:
2.2V.
[101]:
2.3V.
[110]:
2.4V.
[111]:
2.5V.
When REGI < Threshold, BDF= low.
When REGI > Threshold, BDF= high.
Below is the procedure to detect low voltage input (ex. below 2.1V):
1.
2.
3.
4.
Set A8105 in standby or PLL mode.
Set BVT[2:0] (082Bh) = [011] and enable BDS (082Bh) = 1.
After 5 us, BDE is auto clear.
MCU reads BDF (082Bh).
If REGI pin > 2.1
V
,
BDF = 1 (battery high). Else, BDF = 0 (battery low).
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20 Power Management
The power consumption of A8105 comes from two parts. One is RF part and the other is digital part (includes MCU core
and peripherals). In the RF part, the idle mode use the minimum power and the TX or RX mode use the maximum power
consumptions. Use changes RF status by setting the strobe control,register(0800h). For more detail information, please refer
chapter 21.1. In this chapter only introduces digital parts. Low power operation is enabled through different power modes setting.
A8105 has various operating mode are referred as normal mode, PM1, PM2, and PM3 (power manager mode 3). Table 20.1
shows the impact of different power modes on systems operation. There are two registers to setting power manager. One is
power control register (PCON, 0x87h) and the other is power control extend register (PCONE, 0xB9h).
In normal mode, user selects different clock be MCU core clock.in CLKSEL[2:0] (PCONE, 0xB9h) then ena
le CKSE
(PCON, 0x87h). User adjusts MCU clocks depends on the required power consumption. CLKSEL[2:0] = 0
110b, the MCU
core clock is the clock sources divide 2 ~ 64. User could adjust the MCU speed to trade-off between t
e pe
ormance and the
power consumption.
BEWARE, please choice CLKSEL firstly then enable CKSE to avoid glitch. Please refer the
reference code or contact AMICCOM
’
s FAE for more details.
User can enable STOP to freeze MCU core clock and all digital peripherals also stop. MCU can
e waked up by hardware
reset, KEY wake up, KEYINT or sleep timer (WOR /TWOR). User set sleep timer, WOR or TWOR before enter STOP mode. In
this condition, it is called PM1. In PM1, all digital circuitry is stop and RF circuitry is active by WOR
Note: Please don
’
t enable STOP and CKSE at the same time.
PCON (087h) Power control
Address/Name R/W Bit
7
Bit 6
Bit 5
Bit 4
Bit 2
Bit 1
Bit 0
87h
R/W SMOD
PCON
–
–
PWE
–
SWB STOP
CKSE
Reset
SWB (Switchback enable)
0
0
0
0
0
0
0
[1]: Enable
[0]: Disable
STOP (Stop mode)
[1]: Enable
[0]: Disable
CKSE (Clock select enable )
[1]: Enable clock select
[0]: Disable clock select
PCONE(0xB9h) Power control exte
Address/Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
B9h
PCON
R/W
–
–
QD REGAE
PM2F CLKSEL2 CLKSEL1 CLKSEL0
Reset
0
0
0
0
0
0
0
0
QD (Quick discharge ) : Reserved for internal usage
REGAE(RegA En
le) : Reserved for internal usage
PM2F (Powe
Mode 2 flag) : Reserved for internal usage
CLKSEL[2:0] (Cloc
Select), Select clock source when enable clock select.
[000]: Cl
source div 64 as MCU clock
[001]: Clo
source div 2 as MCU clock
[010]: Cloc
source div 4 as MCU clock
[011]: Clock source div 8 as MCU clock
[100]: Clock source div 16 as MCU clock
[101]: Clock source div 32 as MCU clock
[110]: Clock source div 64 as MCU clock
[111]: Select RTC as CPU clock when CKSE=0; RTC div 2 as CPU clock when CKSE=1
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MCU speed
16MHz
RAM
ON
Back to Normal
X
LVR
X
RF
X
Normal
CKSE=0
Normal
CKSE=1
(Low speed)
Idle
16MHz
ON
8/4/2/1 MHz
IRC/RTC
ON
ON
ON
ON
X
X
X
X
H/W reset /
KEYINT
/ Sleep timer
H/W reset / wakeup key
/ Sleep timer
(PM1)
Sleep
(PM2)
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
FF
X
Deep Sleep
(PM3)
256K OFF
H/W reset / wakeup key
2K ON
/ Sleep timer
Table 20.1 Power manager
OFF
X: don
’
t care, it can turn on or off by user setting
Note: PM mode setting refer to chapter 9.2.101
RF
Clock
Generator
XO
0
CL
RUN
RTC
1
1
IRC
0
0
1
2
/64
/2
CLK
MCU
Core
CLKCTRL
CLKSEL =7
RTCS
/4
CLKPMM
3
4
/8
CLKSEL
/16
/32
/64
/2
5
6
7
CKSE STOP
WOR/TWOR
timer
CLKSEL = 0 ~ 7
Figure 20.1 Whole chip clock sources
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21 A8105 RF
A8105 integrate 2.4 Ghz GFSK transceiver and use Strobe control register (0800h) to control RF state. There are 6 Strobe
commands to control internal state machine for RF operations. These modes include Sleep mode, Idle mode, Standby mode,
PLL mode, RX mode and TX mode. There are 64Bytes FIFO for data transmitting, receiving. Sleep timer is used for WOR
(Wake On Rx) and time-slotted mode operation.
21.1 Mode Control Register 1 (Address: 0x801h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
STRB7
1
STRB6
0
STRB5
1
STRB4
0
STRB3
0
STRB2
0
STRB1
0
STRB0
0
MODEC1
Reset
Use strobe command control RF state.
STRB[7:0]: Strobe command register.
0x80:
Sleep mode.
0x90:
Idle mode.
0xA0:
Standby mode.
0xB0:
PLL mode.
0xC0:
TX mode.
0xD0:
RX mode.
Mode Register (Address: 0x800h)
Name
R/W
Bit 7
Bit 6
Bit 5
Bi
4
Bit 3
Bit 2
Bit 1
Bit 0
W
R
RESETN
FWPRN
FECF
—
FRPR
CRCF
—
C12RN
CER
BFCRN
PLLER
—
Mode
Reset
–
XER
—
TRSR
—
TRER
—
—
—
In A8105, user can read the RF state from mod
register
CER: RF chip enable status.
[0]:
RF chip is disabled.
[1]:
RF chip
ble
.
XER: Internal crystal oscillator en
tatus.
[0]:
Crystal oscillator is disabled.
[1]:
al oscillator is enabled.
PLLE: PLL enabled status.
[0]:
PLL is disabled.
[1]:
PLL i
enab
ed.
TRER: TRX state enab
ed status.
[0]:
TRX is disabled.
[1]
TRX
s enabled.
TRSR: TRX Status R
gister.
[0]:
RX state.
[1]:
X sta
e.
In A8105, user
ont
l RF mode as well as read/write ram. By DPTR access and MOVX instruction, user change RF mode and
know RF
atus.
21.1.1 Str
be Command – Sleep Mode
Refer to Strobe Control Register, user can write 0x80 to Strobe Control Register directly to set RF into Sleep mode.
21.1.2 Strobe Command – Idle Mode
Refer to Strobe Control Register, user can write 0x90 to Strobe Control Register directly to set RF into Idle mode.
21.1.3 Strobe Command – Standby Mode
Refer to Strobe Control Register, user can write 0xA0 to Strobe Control Register directly to set RF into Standby mode.
21.1.4 Strobe Command – PLL Mode
Refer to Strobe Control Register, user can write 0xB0 to Strobe Control Register directly to set RF into PLL mode.
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21.1.5 Strobe Command – RX Mode
Refer to Strobe Control Register, user can write 0xC0 to Strobe Control Register directly to set RF into RX mode.
21.1.6 Strobe Command – TX Mode
Refer to Strobe Control Register, user can write 0xD0 to Strobe Control Register directly to set RF into TX mode.
21.2 RF Reset Command
In addition to power on reset (POR), A8105 could issue software reset (80h) to RF by setting Mode Register (0800h). A8105
generates an internal signal
“
RESETN
”
to initial RF circuit. After reset command, RF state is in standby mode a
d re-calibration
is necessary.
21.3 FIFO Accessing Command
Before TX delivery, user only needs to write wanted data into TX FIFO (0x900 ~ 0x93F) in advance. Similarly, user can read RX
FIFO (0x900 ~ 0x93F) once payload data is received. It is easy to delivery data to air. Below is
he procedure of writing TX
FIFO.
Step1: Send
(n+1) bytes TX data in sequence by Data Byte 0, 1, 2 to n.
Step2: Send
TX Strobe command for transmitting.
There are similar steps to read RX FIFO.
Step1: Send
RX Strobe command for receiving data.
Step2: Read
RX data from RX FIFO in sequence by Data Byte 0, 1, 2 to n.
A8105 supports separated 64-bytes TX and RX FIFO. To use A8105
’
s FIFO mode, user just needs to enable FMS =1 (01h). For
FIFO accessing, TX FIFO (write-only) and RX FIFO (read-only) s
re t
same register address 05h. TX FIFO represents
transmitted payload. On the other hand, RX circuitry synchro
es ID Code and stores received payload into RX FIFO.
21.4 Packet Format of FIFO mode
Data whitening(optional)
FEC encoded/decoded(optional)
CRC -16 calculation(optional)
Preamble
4 bytes
e
4 bytes
Payload
(CRC)
Max. 256 bytes
2 bytes
Figure 21.1 Packet Format of FIFO mode
ID code
ID Byte 0
ID Byte 1
ID Byte 2
ID Byte 3
Figure 21.1 ID Code Format
Preamble:
The packet is led by preamble composed of alternate 0 and 1. If the first bit of ID code is 0, preamble shall be 0101
…
0101. In
the contrast, if the first bit of ID code is 1, preamble shall be 1010
…
1010.
Preamble length is recommended to set 4 bytes by PML [1:0] (20h).
ID code:
ID code is recommended to set 4 bytes by IDL=1 (20h). ID Code is sequenced by Byte 0, 1, 2 and 3. If RX circuitry checks the
ID code correct, payload will be written into RX FIFO. In special case, ID code could be set error tolerance (0~ 3bit error) by
ETH [1:0] (21h) for ID synchronization check.
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Payload:
Payload length is programmable by FEP [7:0] (03h). The physical FIFO depth is 64 bytes. A8105 also supports logical FIFO
extension up to 256 bytes. See section 16.5 for details.
CRC (option):
In FIFO mode, if CRC is enabled (CRCS=1, 20h), 2-bytes of CRC value is transmitted automatically after payload. In the same
way, RX circuitry will check CRC value and show the result to CRC Flag (00h).
21.5 Transceiver Frequency
A8105 is a half-duplex transceiver with embedded PA and LNA. The receiver is a low-IF architecture cons
of a LNA, down
conversion mixers, polyphase channel filters and IF limiting amplifiers with RSSI. The transmitter is di
ect m
dulation
architecture with
6
dBm maximum output power and 35 dB power control range. For TX or RX frequenc
se
ing, user just
needs to set up one register, CHN (0811h), for frequency agility.
A8105
’s main PLL features are:
Frantional-N to generate RX/TX frequencies for all ISM 2.4 GHz channels
Autonomous calibration loops for stable operation within the operating range
Fast PLL settling to support frequency hopping
During receive operation, the frequency synthesizer works as a local oscillator
transmit operation, the voltage-controlled
oscillator (VCO) is directly modulated to generate the RF transmit signal. Th
fre
cy synthesizer is implemented as a
fractional-N PLL.
FLO
= 2400 + (CHN x 0.5) in [MHz],
where CHN is the channel number, a
dr 0Fh.
A8105
’
s LO frequency F
LO
= F
LO_BASE
+ F
OFFSET.
Therefore, A8105
s very easy to implement frequency hopping by
ONE
register setting, (CHN, 0Fh).
In general, user can plan the
ed channels by a CHN Look-Up-Table between master and
slaves for two-way frequency hopping. Below is the LO fre
block diagram.
DBL
F
LO
F
PFD
F
XTAL
1
0
X 2
PFD
VCO
1/(RRC+1)
Divider
BIP[8:0] +
BFP[15:0]/ 2
F
LO_BASE
16
16
F
LO
+
+
CHN x CHR /
2
F
OFFSET
Figure 21.2 Block Diagram of Local Oscillator
21.5.1 RF Clock
The master clock of A8105 (F
CSCK
= 32/64 MHz) is generated by the PLL clock generator which reference frequency (F
CGR
= 2/4
MHz) is derived from frequency divider of crystal oscillator.
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F
XREF
CGR
from crystal oscillator.
GRC
[3
:
0
]
1
, where GRC [3:0] (0Eh) is the divide number to get F
F
CGR
Below is block diagram of system clock where F
XTAL
is the crystal frequency. User can set XS, GRC, CGS to get F
CSCK
=
32/64MHz. F
XREF
is a reference clock to generate F
CGR
and F
SPLL
. After delay circuitry, F
CSCK
(32/64MHz) is derived.
And with BWS setting, the system clock F
SYCK
can be fixed to 8MHz.
CGC
GRC
CGS
CE
XS
CE
F
XREF
System cl
ck
÷
PLL
CE
1
0
(GRC+1)
F
32M/
64MHz
CSC
= 32/64MHz
XI
F
CGR
Delay
F
SYCK
Clock Generator
1
[(1+BWS)*4]
F
SPLL
XO
F
XTAL
Figure 21.3 RF Clock Block Dia
ram
Below is the setting table of system clock for both 1MHz and 2MHz data rate
Data
rate
1M
GRC
[3:0]
[01
CGC
BWS F
CSCK
F
SYCK
F
XTAL
F
XREF
F
CGR
S
CGS
16 MHz
16 MHz
2 MHz
16 MHz
16 MHz
2 MHz
1
1
1
1
0
1
0
1
32MHz 8MHz
64MHz 8MHz
2M
[001
21.5.2 LO Frequency Setting
To set up 2.4GHz LO Frequency (F
can refer to below 4 steps.
1.
Set the base frequency
F
LO_BASE
) by PLL Register II (0812h) and III (0813h).
Recommend to set
F
LO_
SE
~ 2400.001MHz
.
2.
3.
Set channel step
CHSP
500KHz by PLL Register IV (0814h).
Set CHN [7
to get offset frequency by PLL Register I (0811h).
F
OFFSET
= CHN
7:0] * F
CHSP
4.
LO
equen
y is equal to base frequency plus offset frequency.
F
LO
LO_BASE
+ F
OFFSET
F
LO
F
LO_BASE
F
OFFSET
21.5.2.1 How to set F
LO_BASE
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Regarding to LO frequency setting, Table 21.1 shows 2400.001 MHz base frequency by 16MHz Xtal.
STEP
ITEMS
F
XTAL
VALUE
16 MHz
NOTE
Crystal Frequency
1
2
3
4
BIP[7:0]
BFP[15:0]
F
LO_BASE
0x96
To get F
LO_BASE
=2400 MHz
To get F
LO_BASE
~ 2400.001 MHz
LO Base frequency
0x0004
~2400.001 MHz
Table 21.1 How to configure F
LO_BASE
21.5.2.2 How to set F
LO
= F
LO_BASE
+ F
OFFSET
Regarding to frequency offset scheme, Table 21.2 shows Channel 11 (2405.001 MHz) by 16MHz Xtal.
STEP
ITEMS
F
LO_BASE
CHR[14:0]
CHN[7:0]
F
OFFSET
F
LO
VALUE
~2400.001 MHz
0x0800
0x0A
5 MHz
~2405.001 MHz
NOTE
1
2
3
4
5
After cofigure B
and
FP
To get F
CHS
= 500 KHz
To set cha
nel number = 10
To get
FSE
=
00 KHz * (CHN) = 5MHz
To
F
LO_BASE
+ F
OFFSET
Table 21.2 How to configure
O
21.6 State machine
In chapter 9.2 and chapter 21.1, user can learn both accessing A
05
’
s
ontrol registers as well as issuing Strobe commands.
21.6.1 Key states
A8105 supports 6 key operation states. Those are,
(1) Standby
mode
(2) Sleep
mode
(3) Idle
mode
(4) PLL
mode
(5) TX
mode
(6) RX
mode
After power on reset or software reset o
deep sleep mode, user has to do calibration process because all control registers are
in initial values. The calibrat
n process of A8105 is very easy, user only needs to issue Strobe commands and enable
calibration registers. After calibration, A8105 is ready to do TX and RX operation. User can start wireless transmission.
Strobe
ommand
Description
b7
b6
b
b
b3
b2
b1
b0
1
1
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Sleep mode
Idle mode
Standby mode
PLL mode
RX mode
TX mode
RF Register
retention Regulator
RF
Mode
Xtal Osc.
VCO PLL
RX
TX
Strobe Command
Sleep
Idle
Yes
Yes
Yes
Yes
Yes
Yes
ON
ON
ON
ON
ON
ON
OFF
OFF
ON
OFF
OFF
OFF
ON
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
ON
(1000-xxxx)b
(1001-xxxx)b
(1010-xxxx)b
(1011-xxxx)b
(1101-xxxx)b
(1100-xxxx)b
Standby
PLL
ON
TX
ON
ON
ON
RX
ON
ON
ON
OFF
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2.4GHz FSK/GFSK SoC
Remark: x means
“
don
’
t care
”
Table 21.3 Operation mode and strobe command
21.6.2 FIFO mode
This mode is suitable for the requirements of general purpose applications and can be chosen by setting FMS = 1. After
calibration, user can issue Strobe command to enter standby mode where write TX FIFO or read RX FIFO. From standby mode
to packet data transmission, only one Strobe command is needed. Once transmission is done, A8105 is auto back to standby
mode. Figure 21.4 and Figure 21.5 are TX and RX timing diagram respectively. Figure 21.6 illustrates state diagram of FIFO
mode.
Strob
e
C
MD
(SCS,SCK,SDIO)
TX
Next Ins
ucti
n
Strobe
RF settling
(PDL+TDL)
RFO Pin
preamble+ID+payload
Transmitting Tim
GIO1 Pin – WTR
(GI
O
1
S[2:0]=001 )
Auto Back
Standby Mode
T0
T1
T2
Figure 21.4 TX timing of FIFO Mode
Strob
e
C
MD
(SCS,SCK,SDIO)
RX
Next Instruction
strobe
Wait
Packe
RX settling
RFI
Pin
preamble+ID+payload
ReceivingTime
G
I
O1 Pin- WTR
(GI
O
1
S[2:0]=001 )
Auto Back
Standb
y
M
ode
T1
T3
T2
Figure 21.5 RX timing of FIFO Mode
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IC reset
(POR, RST-CMD)
AK
PLL
PLL
Auto CAL
.
Standby
3mA
AK
Auto
STB
Sleep
STB
STB
(1.2ms)
Standby
SLEEP
2.5uA
Deep
Sleep
STB
(2ms)
Sleep
(1.2ms)
Deep
Standby
3mA
SLEEP
0.02uA
R-FIFO
W-FIFO
TX / RX
Strobe
PLL
9.5mA
Auto
PDL
Auto
Auto
SYMBOL EXPLAIN
( RX FIFO Full
*
)
( TX FI
Empty
WPLL
9.5mA
State
PLL
9.5mA
RX
settling
TDL
State current
Strobe CMD
ST
(1ms)
MCU delay time
RF auto delay
RX
18mA
TX
1ms
ST
: apply Strobe command
AK
: enable control register
Auto : auto entry
Auto
Auto
RSSI Measure
(ARSSI=1)
Figure 21.6 State diagram of FIFO Mode
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22. Encryption and Autherfication
For Bluetooth Low Energy application, it uses AES-128 link layer encryption block with Counter Mode CBC MAC defined in
IETF RFC 3610. A8105 32Kbytes version (A8105F5) integrates AES-128 encryption core for user to encrypt data using AES
algorithm with 128-bits key. The AES core also supports CBC-MAC for authentication.
22.1 AES
AES (Advanced Encryption Standard) is a symmetric block cipher on 128-bits data blocks, it consists 10 encryption rounds
during encryption process. Figure 22.1 shows the structure of the AES encryption. AES can be divided into four basic operation
block where data are treated at either byte or bit level. The array of bytes organized as a 4×4 matrix is als
called
s
ate
”
and
those four basic steps, AddRoundKey, SubBytes, ShiftRows, and MixColumns. These four steps describe
ound of the AES
operation. The number of rounds is depended on the key length, i.e., 10, 12, and 14 rounds for the ke
leng
h of 128, 192, and
256 bits respectively. The block diagram of the AES with 128 bit data is shown below in Figure 22
1.
AES_IN
128-bits
MUX
AES_KEY
128-bits
MUX
AddRoundKey
AES_OUT
128-bits
Key
Expansion
ubBy
iftRows
MixColumns
gure 22.1 Structure of the AES-128 Core.
22.1.1 AddRoundKey
Each byte of the array is ad
ed to
byte of the corresponding array of round subkeys. Excluding the first and the last round,
the AES with 128-bits ro
nd key proceeds for 9 iterations. Round keys are generated by a procedure called round key
expansion or key sched
ling.
hose sub-keys are derived from the original key by XOR the two previous columns. For columns
that are in multiples o
fou
, the process involves round constants addition, S-Box and shift operations.
22.1.2 SubBytes
This operation is
non-linear byte substitution. It composes of two sub-transformations; multiplicative inverse and affine
transform
tion. In most implementations, these two sub-steps are combined into a single table lookup called S-Box.
22.1.3 Sh
tRows
This step is a simple permutation process, operates on individual rows, i.e. each row of the array is rotated by a certain
number of byte positions.
22.1.3 MixColumns
The MixColumns transformation is a substitution step that makes of arithmetic over GF(2
8
). Column vector is multiplied by a
fixed matrix where bytes are treated as a polynomial of degree less than 4.
22.2 CCM
CCM is an authenticated encryption algorithm designed to provide both authentication and confidentiality. It is only defined for
block ciphers with a block length of 128 bits. It uses encryption algorithm to generate encrypted and authenticated data at the
same time. The AES-CCM process is shown in Figure 22.2.
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2.4GHz FSK/GFSK SoC
AES-128
Encryption
AES-128
Encryption
A1
A2
Payload-1
B2
Payload-0
B1
B0
Cipher-0
Cipher-1
AES-128
Encryption
AES-128
Encryption
A
AES-128
Encryption
AES-128
Encryption
MAC
MIC
Figure 22.2 CCM Encryption Proced
CCM authentication starts by defining a sequence of blocks B
0
, B
1
, a
d B
and thereafter CBC-MAC is applied to those blocks
so that the authentication field MIC can be obtained. CCM uses the A
0
, A
and A
2
blocks to generate key-stream that is used to
encrypt the MIC and the payload. Block A
0
is always used to encrypt and d
crypt the MIC. A
1
and A
2
blocks are generated as
needed for encryption or decryption of the payload.
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23. Flash memory controller
SFR RELATED REGISTERS
FLASH memory is controlled using
PCON(0x87)’s
PWE bit, FLSHCTRL(0x9A) and
FLSHTMR (0x9B), FLSHTPG(0x9C) and
FLSHTER(0x9D). An SFR register named FLASHCTRL (0x9A) is used to control communication between CPU and flash.
FLSHCTRL(0x9A) is consisted of 6bits used to control all FLASH related operations. Lower five bits of FLSHTMR (0x9B)
named FREQ[4:0] determine real CLK frequency with 1MHz step resolution. FREQ[4:0] after reset is set to 20MHz by default,
provides optimal timing for flash macro. Please contact AMICCOM FAE for more details flash operation reference code.
Address/Name R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
9Ah
FLSHCTRL
R/W CTRL.7
CTRL.6 CTRL.5 CTRL.4 CTRL.3 CTRL.2 CTRL.1 CTRL
Reset
0
0
0
0
0
0
0
0
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
9Bh
FLSHTMR
R/W
Fewq.4 Fe
Fe
.2 Fewq.1 Fewq.0
Reset
0
0
0
0
0
0
0
0
Address/Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
9Ch
R/W
FLSHTPG
Reset
0
0
1
0
0
1
1
1
Address/Name R/W Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
9Dh
R/W
FLSHTER
Reset
1
1
1
1
1
0
0
1
Setting higher clock frequency is not supported since given Flash macro has limited its clock frequency up to 20MHz by Tkp
read cycle time. FLASHCTRL register is write protected by TA enable procedure listed below:
CLR EA
;disable interrupt system
MOV TA, #0xAA
MOV TA, #0x55
MOV FLASHCTRL,#<value> ; Any direct addressing instruction writing FLASHCTRL register.
SETB EA ;Enable
interrupt system
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The Program Write Enable (PWE) bit, located in PCON register, is used to enable/ disable PRGROMWR and PRGRRAMWR
pin active during MOVX instructions.
PCON (087h) Power control
Address/Name R/W Bit
7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
87h
R/W SMOD
PCON
–
–
PWE
–
SWB STOP
CKSE
Reset
0
0
0
0
0
0
0
0
When PWE bit is set to logic 1, the MOVX @DPTR,A instruction writes data located in accumulator register in to
rogram
Memory addressed by DPTR register (active: DPH:DPL). The MOVX @ Rx,A instruction writes data locat
accumulator
register into program memory addressed by
P2 register (bit 15:8)
and Rx register (bit 7:0). Program Memo
can be read by
MOVC only regardless of PWE bit.
CHIP ERASE OPERATION
Chip erase operation is enabled by setting CTRL[5:0]=0x04 of FLSHCTRL register accor
ng to MCU TA enable procedure.
PCON.PWE bit must be also set, then first MOVX instruction writing to program memory sp
ce at address belong to certain
FLASH macro begins sector erase operation. During erase operation MCU is halt
d by asserting FLASHBUSY pin. When
FLASH macro is blank and ready for new programming. To erase another FL
ma
ro, the whole procedure needs to be
repeated with change MOVX address pointing to certain FLASH macro. Prep
ming of whole FLASH macro is executed
automatically without any interaction with user, before real chip erase. It ext
nds
ycle of FLASH macro.
SECTOR ERASE OPERATION
The 16KB Flash macro has 129 sectors (128Bytes each) which can
e er
sed separately. Sector erase operation is enabled by
setting CTRL[5:0] = 0x22 of FLSHCTRL register according to MCU TA
nable procedure. PCON.PWE bit must be also set. The
first MOVX instruction writing to program memory space at sele
ted sector address begins sector erase operation. During
sector erase operation, MCU is galted by asserting FLA
SY pin. When sector has been erased, FLASHBUSY pin is
deactivated and FNOP is automatically written. MCU exe
xt instruction. Selected FLASH macro sector(s) is blank and
ready for new programming. To erase another sectors whole
cedure needs to be repeated. Programming of whole sector is
executed automatically without any interaction with user, before real erase. It extends lifecycle of FLASH macro.
PROGRAM OPERATION
Word program operation is enabled by setting
TRL[5:0]=0x01 of FLSHCTRL register according to MCU TA enable procedure.
PCONE.PWE bit
must be set too, then
ea
h w
te to program memory
space by MOVX instruction addressing
odd bytes
begins word program operation. Durin
rogram operation MCU is halted by asserting FLASHBUSY pin. When word has been
programmed FLASHBUSY pin is d
ed. MCU executes next instruction which can be (i) programming of next memory
word (ii) CTRL[5:0] = 0x00 accordin
CU TA enable procedure. Number of programmed by bytes must be always even
number(2,4,6
…
) . For
exam
e to
program byte at address 0x003, first must be written byte
at address 0x002
then second
MOVX instruction write at ad
ress 0x003 begins physical write to FLASH macro. When number of programmed bytes is not
even then it must be filled with extra neutral byte. The neutral bytes does not program any bit in a FLASH macro.
Note: Flash
memory can program
ed once. Please erase sector firstly if change the content in the flash memory.
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2.4GHz FSK/GFSK SoC
24 In Circuit Emulator (ICE)
A8105 support In Circuit Emulator on chip. It is a real-time hardware debugger as a non-intrusive system. It doesn
’
t need
to occupy any hardware resource such as the UART and Timer. User develops firmware complete producing code without any
modification using ICE. It helps user to track down hidden bugs within the application running with microcontroller. The ICE
with Hardware USB dongle provides a powerful SOC development tool with silicon using 2-wire protocol. The ICE fully
supports Keil uVision2/3/4 interface to hardware debuggers. It allows Keil software user to work with uvision2/3/4. For more
detail information, please reference Application note.
24.1 PIN define
Fig 24.1 Th
B connectors
Fig22.2 The Pin define within USB connector
Note: RSTO pin is
en dr
in (od) type active low. It forces logic zero to issue reset. When RSTO is inactive its output is floating, and should
be connected to global
ystem reset with pull-up resistor. This pin can be left unconnected.
There are 10 pin in the ICE connectors. 2-wire ICE only use 2 pins (PIN1 and PIN3). The PIN9 is optional and it can
connects
signal. PIN2 and PIN10 are GND pin. PIN4 is VCCIO pin. The recommended circuit shows as the below figure.
(Fig21.3).
here is a resister (100 ohm) between A8510 and pin connected the connector.
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2.4GHz FSK/GFSK SoC
Fig 24.3 The connections between A8105 and
nnectors
24.2 ICE Key feature
The ICE supports source level debugging, 2 hardware breakpoi
t, a
o refresh of all register and In System
Programming (ISP). User can use ICE to download firmware by
il s
ware or AMICCOM tool.
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25. Application circuit
Below are AMICCOM
’
s ref. design circuits. For more details, please refer AMICCOM standard module , MD8105-Axx.
CRYSTAL(32.768KHz/CL=12.5pF)
Y3
3
2
REGI
1
4
R1
100K
RESETN
C1
22p
C2
22p
C3
1U
U1
1 CO
5P 1.27
RTCO
VPP
1
2
30
P1_4/TTDIO
P1_3/C
O
1_2/
P1
P3_7
P1_4
P1_3
P1_2
P1
P1
_7
5
P0_4
P0_3
29
28
27
6
5
24
23
22
21
VPP
RESETN
VDD_S
VDD_D
BPBG
3
RESTN
VDD_S
VDD_D
BP_BG
VDD_R
VDD_A
RFI
1uF
C6
C9
C7
C10
C8
C4
4
1uF
5
P1_0
amc054_QFN40_OTP
330pF
120pF
1uF
L2
3.9nH
6
P0_7/GIO1
P0_6
VREF
7
VDD_A
8
P0_5
L1
5.6nH
3.9pF
RFI
RFO
9
P0_4/DEBUG_EN
P0_3
ANTENNA
L4
L5
C20
10pF
L3
10
RFO
0R
2.4nH
C18
1.2pF
C19
1.2pF
C15
NC
8105
J2
CON/11P 1.27
10nH
VDD_P
C11
NC
C21
100pF
C22
0.1uF
C12
1uF
C13
C5
2.2uF
100pF
Y1
GND
C23
3.3nF
4
1
3
2
GND
CRYSTAL/3.2*2.5 (16MHz/CL=12pF)
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2.4GHz FSK/GFSK SoC
26. Abbreviations
ADC
AIF
Analog to Digital Converter
Auto IF
FC
Frequency Compensation
Automatic Gain Control
Bit Error Rate
AGC
BER
BW
Bandwidth
CD
Carrier Detect
CHSP
CRC
DC
Channel Step
Cyclic Redundancy Check
Direct Current
FEC
FIFO
FSK
ID
Forward Error Correction
First in First out
Frequency Shift Keying
Identifier
ICE
In Circuit Emulator
I
2
C
Inter-Integrated Circuit
Intermediate Frequency
Industrial, Scientific and Medical
Local Oscillator
IF
ISM
LO
MCU
PFD
PLL
Micro Controller Unit
Phase Frequency Detector for PLL
Phase Lock Loop
POR
PWM
RX
Power on Reset
Pulse width modulation
Receiver
RXLO
RSSI
SPI
SYCK
TX
Receiver Local Oscillator
Received Signal Strength Indicator
Serial to Parallel Interface
System Clock for digital circuit
Transmitter
TXRF
UART
VCO
XOSC
XREF
XTAL
Transmitter Radio Frequency
Universal Asynchronous Rece
r/T
ansmitter
Voltage Controlled Oscillat
Crystal Oscillator
Crystal Reference frequ
Crystal
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27. Ordering Information
Part No.
Package
Units Per Reel / Tray
A8105F5 (32KB)
A81X05F5009AQ6C/Q
A81X05F5009AQ6C
A81X05F5001AQ5A/Q
A81X05F5001AQ5A
A81X05F5001AH
QFN48L, Pb Free, Tape & Reel, -40
℃～
85
℃
QFN48L, Pb Free, Tray, -40
℃～
85
℃
QFN40L, Pb Free, Tape & Reel, -40
℃～
85
℃
QFN40L, Pb Free, Tray, -40
℃～
85
℃
Die form, -40
℃～
85
℃
3K
490EA
3K
490
A
1
0EA
A8105F4 (16KB)
A81X05F4001AQ5A/Q
A81X05F4001AQ5A
A81X05F4001AH
QFN40L, Pb Free, Tape & Reel, -40
℃～
85
℃
QFN40L, Pb Free, Tray, -40
℃～
85
℃
Die form, -40
℃～
85
℃
3K
490EA
100EA
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2.4GHz FSK/GFSK SoC
28. Package Information
QFN6*6 48L Outline Dimensions
Top View
Bottom View
Dimensions in inches
Dimensions in mm
Symbol
Min
0.028
0
Nom
0.030
0.001
Max
0.031
0.002
Min
0.7
0.00
Nom
0.75
0.02
Max
0.8
0.05
A
A
1
A
3
0.009 REF.
0.23REF.
0.006
0.008
0.010
0.15
0.2
0.25
b
D
D
2
E
0.240
0.177
0.240
6.0 BSC
4.50
6.0BSC
4.50
0.146
0.146
0.179
0.179
3.70
3.70
4.55
4.55
E
2
0.177
e
L
k
0.016BSC
0.016
0.008
0.4BSC
0.4
0.2
0.013
0.020
0.32
0.48
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2.4GHz FSK/GFSK SoC
QFN5*5 32L Outline Dimensions
Top View
Bottom View
0
. 2
C
D
D
2
32
25
25
32
1
24
24
8
17
17
8
0.25
C
9
16
9
e
b
0.10 M
C A B
//
C
Seating Plane
C
C
mensions in inches
Dimensions in mm
Symbol
n
Nom
0.030
Max
0.036
0.002
Min
0.70
0.00
Nom
0.75
Max
0.90
0.05
A
3
b
.028
0.000
0.001
0.02
0.010 REF
0.010
0.20 REF
0.25
0.007
0.193
0.049
0.193
0.049
0.012
0.200
0.141
0.200
0.141
0.18
4.90
1.25
4.90
1.25
0.30
5.10
3.60
5.10
3.60
D
0.197
5.00
D
2
E
0.106
2.70
0.197
5.00
E
2
e
0.106
2.70
0.020 BSC
0.016
0.50 BSC
0.40
L
0.012
0.020
0.30
0.50
y
0 – 0.004
0 – 0.10
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2.4GHz FSK/GFSK SoC
29. Top Marking Information
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2.4GHz FSK/GFSK SoC
Part No.
Pin Count
Package Type
:
QFN
Dimension
Mark Method
Character Type
:
Arial
:
A81X05F4001AQ5A
:
40
:
5*5 mm
:
Laser Mark
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2.4GHz FSK/GFSK SoC
Part No.
Pin Count
Package Type
:
QFN
Dimension
Mark Method
Character Type
:
Arial
:
A81X05F5001AQ5A
:
40
:
5*5 mm
:
Laser Mark
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2.4GHz FSK/GFSK SoC
30. Reflow Profile
Actual Measurement Graph
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31. Tape Reel Information
Cover / Carrier Tape Dimension
Unit: mm
Cover
TYPE
P
A0
B0
P0
P1
D0
D1
E
F
W
K0
t
tape
width
3.2
5
±
0.1
4.35
±
0.1
5.25
±
0.1
1.75
±
0.1
1.75
±
0.1
1.75
±
0.1
1.75
±
0.1
5.5
±
0.05
5.5
±
0.05
5.5
±
0.05
7.5
±
0.1
1.25
±
0.1
1.2
5
±
0.1
±
0.05
1.25
±
0.1
1.15
0.3
±
0.05
0.3
3.25
±0.1
4.35
±
0.1
5.25
±
0.1
8
±
0.1
8
±
0.1
8
±
0.1
4
±
0.2 2
±
0.1 1.5
±
0.1
4
±
0.2 2
±
0.1 1.
4
±
0.2 2
±
0
1 1.5
±
0.1
12
±
0.3
12
±
0.3
12
±
0.3
16
±
0.3
9.3
±
0.1
9.3
±
0.1
9.3
±
0.1
QFN 3*3
QFN 4*4
QFN 5*5
QFN 6*6
1.
1.5
1.5
0.3
±
0.05
0.3
±
0.05
13.3
±
0.1
12
±
0.1 6.3
±
0.1 6.3
±
0.1 4
±
0.2 2
±
0.1 1.5
±
0.1 1.5
±
0.5
±
0.2
REEL DIMENSIONS
T
L
R
D
N
M
K
Unit: mm
TYPE
QFN3*3/4*4/5*5
QFN6*6
G
N
M
D
K
L
R
12.9
±
0.5
17
±
0.5
102 REF
±
2.0
102 REF
±
2.0
2.3
±
0.2
2.3
±
0.2
13.15
±
0.35
13.15
±
0.35
2.0
±
0.5
2.0
±
0.5
330
±
3.0
330
±
3.0
19.6
±
2.9
19.6
±
2.9
Sep., 2014, Version 0.6 (Preliminary)
135
AMICCOM Electronics Corporation
A8105
2.4GHz FSK/GFSK SoC
32. Product Status
Data Sheet Identification
Product Status
Definition
Objective
Planned or Under Development
This data sheet contains the design specifications
for product development. Specifications may
change in any manner without notice.
Preliminary
Engineering Samples
and First Production
This data sheet contains preliminary data, and
supplementary data will be published
t a later
date. AMICCOM reserves the right to make
changes at any time without noti
order to
improve design and supply
he
st possible
product.
No Identification
Obsolete
Noted Full Production
Not In Production
This data sheet contai
s the f
nal specifications.
AMICCOM reserves the r
ht to make changes at
any time without notic
in order to improve design
and supply the best poss
ble product.
This data she
contains specifications on a
product th
as b
n discontinued by AMICCOM.
The data
s printed for reference information
only.
RF ICs
AMICCOM
Headquarter
A3, 1F, No.1, Li-Hsin 1
st
Rd., Hsinchu Science Park,
Hsinchu, Taiwan 30078
Tel: 886-3-5785818
Shenzhen Office
Rm., 2003, DongFeng Building, No. 2010,
Shennan Zhonglu Rd., Futian Dist., Shenzhen, China
Post code: 518031
Web Site
Sep., 2014, Version 0.6 (Preliminary)
136
AMICCOM Electronics Corporation
