Ampleon-BLC9G20XS-400AVTY
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BLC9G20XS-400AVT
Power LDMOS transistor
Rev. 3 — 24 November 2017
Product data sheet
1. Product
profile
1.1 General
description
400 W LDMOS packaged asymmetric Doherty power transistor for base station
applications at frequencies from 1805 MHz to 1880 MHz and 1930 MHz to 1995 MHz.
Table 1.
Typical RF performance at T
case
= 25
C in an asymmetrical Doherty production test circuit.
DS
= 32 V; I
Dq
= 800 mA (main); V
GS(amp)peak
= 0.5 V, unless otherwise specified.
Typical performance
V
Test signal
f
V
DS
(V)
32
P
L(AV)
(W)
G
p
D
ACPR
(dBc)
39
[1]
(MHz)
(dB)
16.2
(%)
45
1-carrier W-CDMA
1805 to 1880
87
[1]
T
e
st
signal: 1-carrier W-CDMA; 3GPP test model 1; 64 DPCH; PAR = 9.6 dB at 0.01 % probability on
CCD
F
.
1.2 Features
and benefits
Excellent ruggedness
High efficiency
Low thermal resistance providing excellent thermal stability
Lower output capacitance for improved performance in Doherty applications
Designed for low memory effects providing excellent digital pre-distortion capability
Internally matched for ease of use
Integrated ESD protection
Compliant to Directive 2002/95/EC, regarding Restriction of Hazardous Substances
(RoHS)
1.3 Applications
RF power amplifiers for base stations and multi carrier applications in the 1805 MHz to
1880 MHz and 1930 MHz to 1995 MHz frequency range
BLC9G20XS-400AVT
Power LDMOS transistor
2. Pinning
information
Table 2.
Pinning
Pin
1
Description
Simplified outline
Graphic symbol
drain2 (peak)
2, 7
7
2
1
6
2
drain1 (main)
5
3
gate1 (main)
3
4
gate2 (peak)
5
3
4
4
[1]
5
source
6
video decoupling (peak)
video decoupling (main)
1, 6
7
aaa-014884
[1] Connected
to flange.
3. Ordering
information
Table 3.
Ordering information
Type number
Package
Name Description
Version
BLC9G20XS-400AVT
–
air cavity plastic earless flanged package;
6 leads
SOT1258-4
4. Limiting
values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
Parameter
Conditions
Min Max
Unit
V
drain-source voltage
–
65
V
GS(amp)main
V
GS(amp)peak
T
stg
main amplifier gate-source voltage
peak amplifier gate-source voltage
storage temperature
6
6
+13
+13
V
V
65 +150
C
[1]
[1]
T
j
junction temperature
–
225
C
T
case
case temperature
operating
40 +125
C
[1] Continuous
use at maximum temperature will affect the reliability, for details refer to the online MTF
calculator.
5. Thermal
characteristics
Table 5.
Symbol Parameter
R
th(j-c)
thermal resistance from junction
V
DS
= 32 V; I
Dq
= 800 mA (main);
Thermal characteristics
Conditions
Typ
Unit
to case
V
GS(amp)peak
= 0,4 V; T
case
= 80
C
P
L
= 85 W
0.25 k/W
0.26 k/W
P
L
= 110 W
BLC9G20XS-400AVT
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© Ampleon Netherlands B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 24 November 2017
2 of 17
BLC9G20XS-400AVT
Power LDMOS transistor
6. Characteristics
Table 6.
DC characteristics
T
j
= 25
C unless otherwise specified.
Symbol Parameter
Conditions
Min Typ
Max Unit
Main device
V
(BR)DSS
drain-source breakdown voltage
V
GS
= 0 V; I
D
= 1.62 mA
65
–
–
V
V
V
GS(th)
V
GSq
I
DSS
I
DSX
I
GSS
g
fs
gate-source threshold voltage
gate-source quiescent voltage
drain leakage current
V
DS
= 10 V; I
D
= 162 mA
V
DS
= 32 V; I
D
= 850 mA
V
GS
= 0 V; V
DS
= 32 V
V
GS
= V
GS(th)
+ 3.75 V
V
GS
= 11 V; V
DS
= 0 V
V
DS
= 10 V; I
D
= 8.1 A
1.5 2.0
2.5
1.65 2.15
2.65 V
–
–
–
–
–
–
2.8
A
drain cut-off current
32
–
–
A
gate leakage current
280 nA
forward transconductance
11.5
85
–
S
R
DS(on)
drain-source on-state resistance
V
GS
= V
GS(th)
+ 3.75 V;
I
D
= 5.67 A
149 m
Peak device
V
(BR)DSS
drain-source breakdown voltage
V
GS
= 0 V; I
D
= 3.0 mA
65
–
–
V
V
V
GS(th)
V
GSq
I
DSS
I
DSX
I
GSS
g
fs
gate-source threshold voltage
gate-source quiescent voltage
drain leakage current
V
DS
= 10 V; I
D
= 300 mA
V
DS
= 32 V; I
D
= 1500 mA
V
GS
= 0 V; V
DS
= 32 V
V
GS
= V
GS(th)
+ 3.75 V
V
GS
= 11 V; V
DS
= 0 V
V
DS
= 10 V; I
D
= 15 A
1.5 2.0
2.5
1.65 2.15
2.65 V
–
–
–
–
–
–
2.8
A
drain cut-off current
52
–
–
A
gate leakage current
280 nA
forward transconductance
20.5
46
–
S
R
DS(on)
drain-source on-state resistance
V
GS
= V
GS(th)
+ 3.75 V;
I
D
= 10.5 A
85
m
Table 7.
Test signal: 1-carrier W-CDMA; PAR = 9.6 dB at 0.01 % probability on the CCDF;
3GPP test model 1; 1 to 64 DPCH; f
1
= 1807.5 MHz; f
2
= 1877.5 MHz; RF performance at
RF characteristics
V
DS
= 32 V; I
Dq
= 850 mA (main); V
GS(amp)peak
= 0.9 V; T
case
= 25
C; unless otherwise specified; in
an asymmetrical Doherty production test circuit at frequencies from 1805 MHz to 1880 MHz.
Symbol Parameter
Conditions
Min
15.2
–
Typ
16.2
15
45
Max
–
Unit
dB
G
p
power gain
P
L(AV)
= 87 W
P
L(AV)
= 87 W
P
L(AV)
= 87 W
P
L(AV)
= 87 W
RL
in
D
input return loss
10
–
dB
drain efficiency
41.5
–
%
ACPR
adjacent channel power ratio
39
34
dBc
Table 8.
RF characteristics
Test signal: 1-carrier W-CDMA; PAR = 9.6 dB at 0.01 % probability on the CCDF;
3GPP test model 1; 1 to 64 DPCH; f = 1877.5 MHz; RF performance at V
DS
= 32 V;
I
Dq
= 850 mA (main); V
GS(amp)peak
= 0.9 V; T
case
= 25
C; unless otherwise specified; in an
asymmetrical Doherty production test circuit at a frequency of 1880 MHz.
Symbol Parameter
Conditions
Min
6.25
500
Typ
6.8
Max Unit
PAR
O
P
L(M)
output peak-to-average ratio
peak output power
P
L(AV)
= 120 W
P
L(AV)
= 120 W
–
–
dB
W
570
BLC9G20XS-400AVT
All information provided in this document is subject to legal disclaimers.
© Ampleon Netherlands B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 24 November 2017
3 of 17
BLC9G20XS-400AVT
Power LDMOS transistor
7. Test
information
7.1 Ruggedness
in Doherty operation
The BLC9G20XS-400AVT is capable of withstanding a load mismatch corresponding to
VSWR = 10 : 1 through all phases under the following conditions: V
DS
= 32 V;
I
Dq
= 850 mA; V
GS(amp)peak
= 0.9 V; f = 1807.5 MHz; P
L
= 126 W (5 dB OBO); 100 %
clipping
.
7.2 Impedance
information
Table 9.
Typical impedance of main device
Measured load-pull data of main device; I
Dq
= 800 mA (main); V
DS
= 32 V; pulsed CW (t
p
= 100
s;
= 10 %).
[1]
[1]
[2]
[2]
[2]
f
Z
S
(
)
Z
L
P
L
D
G
p
(MHz)
(
)
(W)
(%)
(dB)
Maximum power load
1805
1840
1880
1.0
j4.5
1.2
j4.8
1.3
j5.1
1.2
j3.0
1.2
j3.1
1.2
j3.1
260
260
260
58.3
58.4
57.9
19.2
19.4
19.3
Maximum drain efficiency load
1805
1840
1880
1.0
j4.5
1.1
j4.8
1.3
j5.1
2.5
j2.2
2.0
j2.5
2.0
j3.5
180
200
200
66.0
65.4
65.3
21.7
21.3
21.3
[1] Z
S
and Z
L
defined in
Figure 1
.
[2] At
3 dB gain compression.
BLC9G20XS-400AVT
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© Ampleon Netherlands B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 24 November 2017
4 of 17
BLC9G20XS-400AVT
Power LDMOS transistor
Table 10.
Typical impedance of peak device
Measured load-pull data of peak device; I
Dq
= 1800 mA (peak); V
DS
= 32 V; pulsed CW (t
p
= 100
s;
= 10 %).
[1]
[1]
[2]
[2]
[2]
f
Z
S
(
)
Z
L
P
L
D
G
p
(MHz)
(
)
(W)
(%)
(dB)
Maximum power load
1805
1840
1880
1.7
j6.0
2.3
j6.6
3.1
j7.1
1.7
j3.2
1.9
j3.3
1.9
j3.2
430
430
430
56.4
56.4
56.4
18.9
19.0
19.1
Maximum drain efficiency load
1805
1840
1880
1.7
j6.0
2.2
j6.6
3.1
j7.2
2.7
j2.9
2.6
j2.4
2.6
j2.3
380
360
360
63.8
63.5
63.7
20.0
20.4
20.5
[1] Z
S
and Z
L
defined in
Figure 1
.
[2] At
3 dB gain compression.
drain
Z
L
gate
Z
S
001aaf059
Fig 1.
Definition of transistor impedance
7.3 Recommended
impedances for Doherty design
Table 11.
Typical impedance of main at 1 : 1 load
Measured load-pull data of main device; I
Dq
= 800 mA (main); V
DS
= 32 V; pulsed CW (t
p
= 100
s;
= 10 %).
[1]
[1]
[2]
[2]
[2]
f
Z
S
Z
L
P
L(3dB)
(W)
D
G
p
(MHz)
1805
1840
1880
(
)
(
)
(%)
(dB)
19.1
19.3
19.5
1.0
j4.8
1.1
j5.0
1.1
j5.2
1.4
j3.2
1.4
j2.9
1.4
j2.5
210
42.0
42.3
44.0
210
205
[1] Z
S
and Z
L
defined in
Figure 1
.
[2] At
P
L(AV)
= 85 W.
BLC9G20XS-400AVT
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© Ampleon Netherlands B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 24 November 2017
5 of 17
BLC9G20XS-400AVT
Power LDMOS transistor
Table 12.
Typical impedance of main device at 1 : 2.5 load
Measured load-pull data of main device; I
Dq
= 800 mA (main); V
DS
= 32 V; pulsed CW (t
p
= 100
s;
= 10 %).
[1]
[1]
[2]
[2]
[2]
f
Z
S
Z
L
P
L(3dB)
(W)
D
G
p
(MHz)
1805
1840
1880
(
)
(
)
(%)
(dB)
21.8
22.0
22.0
1.0
j4.8
1.1
j5.0
1.1
j5.2
3.5
j2.8
3.4
j2.6
3.4
j2.4
115
59.0
58.0
57.4
110
110
[1] Z
S
and Z
L
defined in
Figure 1
.
[2] At
P
L(AV)
= 85 W.
Table 13.
Typical impedance of peak device at 1 : 1 load
Measured load-pull data of peak device; I
Dq
= 1750 mA (peak); V
DS
= 32 V; pulsed CW (t
p
= 100
s;
= 10 %).
[1]
[1]
[2]
[2]
[2]
f
Z
S
Z
L
P
L(3dB)
(W)
D
G
p
(MHz)
1805
1840
1880
(
)
(
)
(%)
(dB)
19.5
19.6
20.0
1.6
j6.0
2.1
j6.5
3.0
j7.0
2.2
j3.2
2.1
j2.9
2.1
j2.7
320
31.4
31.5
32.2
320
320
[1] Z
S
and Z
L
defined in
Figure 1
.
[2] At
P
L(AV)
= 85 W.
Table 14.
Off-state impedances of peak device
f
Z
off
(MHz)
1805
1840
1880
(
)
3.5
j5.5
1.4
j2.9
0.8
j1.6
BLC9G20XS-400AVT
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© Ampleon Netherlands B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 24 November 2017
6 of 17
BLC9G20XS-400AVT
Power LDMOS transistor
7.4 Test
circuit
110.2 mm
R1
C3
C15
C1
C20
C13
C11
C7
C5
C17
C18
R2
X1
C8
C9
80 mm
C6
C10
C19
C12
C14
C16
C4
R3
C2
C21
amp00057
Printed-Circuit Board (PCB): Rogers 4350B:
r
= 3.66; thickness = 0.508 mm; thickness copper
plating = 35
m. See
T
a
ble 15
for a list of components.
Fig 2.
Component layout
Table 15.
List of components
See
Figure 2
for component layout.
Component
Description
Value
Remarks
[1]
[1]
C1, C2, C11,
C12, C15, C16
multilayer ceramic chip capacitor
4.7
F
,
5
0 V
Murata
GRM32ER71H475KA88L
C3, C4, C5, C6,
multilayer ceramic chip capacitor
10 pF
C13, C14 C19
Murata Hi-Q 0805
[1]
[1]
[1]
[1]
[1]
C7
multilayer ceramic chip capacitor
3.0 pF
multilayer ceramic chip capacitor
2.4 pF
multilayer ceramic chip capacitor
1.5 pF
multilayer ceramic chip capacitor
2.0 pF
multilayer ceramic chip capacitor
4.7 pF
Murata Hi-Q 0805
Murata Hi-Q 0805
Murata Hi-Q 0805
Murata Hi-Q 0805
Murata Hi-Q 0805
C8
C9
C10
(C17, C18)
C20, C21
R1, R2
R3
electrolytic capacitor
SMD resistor
100
F
10
, 1 %
50
, 25 W
2 dB, 90
SMD 0805
SMD resistor
Anaren C16A50Z4
Anaren Xinger III
X1
hybrid coupler
[1] Murata
or capacitor of same quality
BLC9G20XS-400AVT
All information provided in this document is subject to legal disclaimers.
© Ampleon Netherlands B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 24 November 2017
7 of 17
BLC9G20XS-400AVT
Power LDMOS transistor
7.5 Graphical
data
7.5.1 Pulsed
CW
amp00058
amp00059
17
16
15
14
13
12
11
60
50
40
30
20
10
0
4
AM to PM
(deg
)
)
G
η
η
D
(%)
p
G
(dB)
p
(1)
(2)
(3)
0
(1)
(2)
(3)
(3
)
)
(2
)
)
-4
(1
)
)
-8
η
D
-12
0
100
200
300
400
500
(W)
600
0
100
200
300
400
P (W)
L
500
P
L
V
DS
= 32 V; I
Dq
= 850 mA; V
GS(amp)peak
= 0.6 V;
V
DS
= 32 V; I
Dq
= 850 mA; V
GS(amp)peak
= 0.6 V.
t
p
= 100
s;
= 10 %.
(1) f
= 1807.5 MHz
(2) f
= 1842.5 MHz
(3) f
= 1877.5 MHz
(1) f
= 1807.5 MHz
(2) f
= 1842.5 MHz
(3) f
= 1877.5 MHz
Fig 3.
Power gain and drain efficiency as function of
output power; typical values
Fig 4.
AM to PM as a function of output power;
typical values
BLC9G20XS-400AVT
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© Ampleon Netherlands B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 24 November 2017
8 of 17
BLC9G20XS-400AVT
Power LDMOS transistor
7.5.2 1-Carrier
W-CDMA
PAR = 9.6 dB per carrier at 0.01 % probability on the CCDF; 3GPP test model 1 with
64 DPCH (100 % clipping).
amp00060
amp00061
17
16
15
14
13
12
11
60
50
40
30
20
10
0
-20
5M
G
η
η
ACPR
(dBc)
p
D
G
p
(dB)
(%)
-30
(
(
1
1
)
)
(
(
2
2
)
)
(
(
3
3
)
)
-40
-50
-60
(1
)
)
(2
)
)
(3
)
)
η
D
0
50
100
150
200
(W)
250
0
50
100
150
200
P (W)
L
250
P
L
V
DS
= 32 V; I
Dq
= 850 mA; V
GS(amp)peak
= 0.6 V.
V
DS
= 32 V; I
Dq
= 850 mA; V
GS(amp)peak
= 0.6 V.
(1) f
= 1807.5 MHz
(2) f
= 1842.5 MHz
(3) f
= 1877.5 MHz
(1) f
= 1807.5 MHz
(2) f
= 1842.5 MHz
(3) f
= 1877.5 MHz
Fig 5.
Power gain and drain efficiency as function of
output power; typical values
Fig 6.
Adjacent channel power ratio (5 MHz) as a
function of output power; typical values
amp00062
amp00063
10
26
PA
R
R
(dB)
RL
in
(dB)
9
8
22
18
14
10
(3
)
)
(2
)
)
(1
)
)
7
(1)
(2)
(3)
6
5
0
50
100
150
200
(W)
250
0
50
100
150
200
P (W)
L
250
P
L
V
DS
= 32 V; I
Dq
= 850 mA; V
GS(amp)peak
= 0.6 V.
(1) f
= 1807.5 MHz
V
DS
= 32 V; I
Dq
= 850 mA; V
GS(amp)peak
= 0.6 V.
(1) f
= 1807.5 MHz
(2) f
= 1842.5 MHz
(3) f
= 1877.5 MHz
(2) f
= 1842.5 MHz
(3) f
= 1877.5 MHz
Fig 7.
Peak-to-average power ratio as a function of
output power; typical values
Fig 8.
Input return loss as a function of output
power; typical values
BLC9G20XS-400AVT
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© Ampleon Netherlands B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 24 November 2017
9 of 17
BLC9G20XS-400AVT
Power LDMOS transistor
7.5.3 2-Carrier
W-CDMA
PAR = 9.6 dB at 0.01 % probability on the CCDF; 3GPP test model 1 with 64 DPCH
(46 % clipping).
amp00064
amp00065
17
16
15
14
13
12
11
60
50
40
30
20
10
0
-20
5M
G
η
η
ACPR
(dBc)
p
D
G
p
(dB)
(%)
-25
(
(
1
1
)
)
(
(
2
2
)
)
(
(
3
3
)
)
-30
-35
-40
-45
-50
η
D
(1
)
)
(2
)
)
(3
)
)
0
50
100
150
200
(W)
250
0
50
100
150
200
P (W)
L
250
P
L
V
DS
= 32 V; I
Dq
= 850 mA; V
GS(amp)peak
= 0.6 V.
V
DS
= 32 V; I
Dq
= 850 mA; V
GS(amp)peak
= 0.6 V.
(1) f
= 1807.5 MHz
(2) f
= 1842.5 MHz
(3) f
= 1877.5 MHz
(1) f
= 1807.5 MHz
(2) f
= 1842.5 MHz
(3) f
= 1877.5 MHz
Fig 9.
Power gain and drain efficiency as function of
output power; typical values
Fig 10.
Adjacent channel power ratio (5 MHz) as a
function of output power; typical values
amp00066
22
RL
in
(dB)
(3
)
)
20
18
16
14
12
10
(2
)
)
(1
)
)
0
50
100
150
200
(W)
250
P
L
V
DS
= 32 V; I
Dq
= 850 mA; V
GS(amp)peak
= 0.6 V.
(1) f
= 1807.5 MHz
(2) f
= 1842.5 MHz
(3) f
= 1877.5 MHz
Fig 11.
Input return loss as a function of output power; typical values
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Product data sheet
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BLC9G20XS-400AVT
Power LDMOS transistor
7.5.4 2-Tone
VBW
amp00067
-10
IM
D
D
(dBc)
-20
(1
)
)
(2
)
)
-30
-40
-50
-60
-70
IM
D
D
3
3
(1
)
)
(2
)
)
IM
D
D
5
5
IM
D
D
7
7
(1
)
)
(2
)
)
2
3
1
10
10
10
carrier spacing (MHz)
V
DS
= 32 V; I
Dq
= 850 mA; V
GS(amp)peak
= 0.6 V.
(1) IMD
low
(2) IMD
high
Fig 12.
VBW capability
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Rev. 3 — 24 November 2017
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Power LDMOS transistor
8. Package
outline
Air cavity plastic earless flanged package; 6 leads
SOT1258-4
D
A
F
5
w
D
B
1
1
v
A
L
b
c
7
2
1
6
y
Į
H
1
Z
1
Z
H
U
E
E
2
1
A
3
4
e
Q
w
b
B
2
1
U
B
1
y
Į
Z
Z
1
0.1 65°
3.17 5.79
61° 2.67
5.29
0
10 mm
scale
Dimensions
Unit
(1)
A
b
b
1
c
D
D
E
E
1
e
L
F
H
H
Q
U
U
v
w
w
2
1
1
1
2
1
max 4.52 1.12 11.78 0.18 31.44
31.34 9.60
9.50
mm nom
min 4.12 0.91 11.58 0.13 31.04
31.14 9.20
9.30
36.42 1.73
16.71 8.12
2.25 32.33
10.23 0.5
0.5
0.5
13.72
36.22 1.53
16.51 7.62
2.03 32.13
10.03
Note
1. Dimension Q is measured 0.1 mm away from the flange.
2. Ringframe and/or ringframe glue shall not overhang at the side of the flange.
sot1258-4_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
SOT1258-4
17-08-31
Fig 13.
Package outline SOT1258-4
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Product data sheet
Rev. 3 — 24 November 2017
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Power LDMOS transistor
9. Handling
information
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling
electrostatic sensitive devices.
Such precautions are described in the
ANSI/ESD S20.20
,
IEC/ST 61340-5
,
JESD625-A
or
equivalent standards.
Table 16.
ESD sensitivity
ESD model
Class
C2A
[1]
2
[2]
Charged Device Model (CDM); According to ANSI/ESDA/JEDEC standard JS-002
Human Body Model (HBM); According to ANSI/ESDA/JEDEC standard JS-001
[1] CDM
classification C2A is granted to any part that passes after exposure to an ESD pulse of 500
V
,
b
ut fails
after exposure to an ESD pulse of 750 V.
[2] HBM
classification 2 is granted to any part that passes after exposure to an ESD pulse of 2000
V
,
b
ut fails
after exposure to an ESD pulse of 4000 V.
10. Abbreviations
Table 17.
Abbreviations
Acronym
3GPP
AM
Description
3rd Generation Partnership Project
Amplitude Modulation
CCDF
CW
Complementary Cumulative Distribution Function
Continuous Wave
DPCH
ESD
Dedicated Physical CHannel
ElectroStatic Discharge
LDMOS
MTF
Laterally Diffused Metal-Oxide Semiconductor
Median Time to Failure
OBO
Output Back Off
PAR
Peak-to-Average Ratio
PM
Phase Modulation
SMD
Surface Mounted device
VBW
Video BandWidth
VSWR
W-CDMA
Voltage Standing Wave Ratio
Wideband Code Division Multiple Access
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Product data sheet
Rev. 3 — 24 November 2017
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Power LDMOS transistor
11. Revision
history
Table 18.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
BLC9G20XS-400AVT v.3
20171124
Product data sheet
–
BLC9G20XS-400AVT v.2
Modifications:
•
T
a
ble 2 on page 2
: changed simplified version drawing SOT1258-7 to SOT1258-4
•
T
a
ble 3 on page 2
: changed version SOT1258-7 to SOT1258-4
•
Figure 13 on page 12
: changed package outline drawing SOT1258-7 to SOT1258-4
BLC9G20XS-400AVT v.2
20161202
Product data sheet
–
BLC9G20XS-400AVT v.1
BLC9G20XS-400AVT v.1
20160513
Product data sheet
–
–
BLC9G20XS-400AVT
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Product data sheet
Rev. 3 — 24 November 2017
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Power LDMOS transistor
12. Legal information
12.1 Data
sheet status
Document status
[1][2]
Product status
[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet
Qualification
Product [short] data sheet
Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
Ampleon product can reasonably be expected to result in personal injury,
12.2 Definitions
death or severe property or environmental damage. Ampleon and its
suppliers accept no liability for inclusion and/or use of Ampleon products in
such equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
Draft —
The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Ampleon does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Applications —
Applications that are described herein for any of these
products are for illustrative purposes only. Ampleon makes no representation
or warranty that such applications will be suitable for the specified use without
further testing or modification.
Short data sheet —
A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local Ampleon sales office. In
case of any inconsistency or conflict with the short data sheet, the full data
sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using Ampleon products, and Ampleon accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Ampleon product is suitable and
fit for the customer’s applications and products planned, as well as for the
planned application and use of customer’s third party customer(s). Customers
should provide appropriate design and operating safeguards to minimize the
risks associated with their applications and products.
Product specification —
The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Ampleon and its customer, unless Ampleon and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be valid
in which the Ampleon product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
Ampleon does not accept any liability related to any default, damage, costs or
problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Ampleon products in order to
avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Ampleon does not accept any
liability in this respect.
12.3 Disclaimers
Limited warranty and liability —
Information in this document is believed to
be accurate and reliable. However, Ampleon does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. Ampleon takes no responsibility for
the content in this document if provided by an information source outside of
Ampleon.
Limiting values —
Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall Ampleon be liable for any indirect, incidental, punitive,
special or consequential damages (including – without limitation – lost profits,
lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale —
Ampleon products are sold
subject to the general terms and conditions of commercial sale, as published
individual agreement. In case an individual agreement is concluded only the
terms and conditions of the respective agreement shall apply. Ampleon
hereby expressly objects to applying the customer’s general terms and
conditions with regard to the purchase of Ampleon products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Ampleon’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with the
Terms and conditions of commercial sale
of Ampleon.
No offer to sell or license —
Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Right to make changes —
Ampleon reserves the right to make changes to
information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Export control —
This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Suitability for use —
Ampleon products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-critical
systems or equipment, nor in applications where failure or malfunction of an
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Product data sheet
Rev. 3 — 24 November 2017
15 of 17
BLC9G20XS-400AVT
Power LDMOS transistor
Non-automotive qualified products —
Unless this data sheet expressly
states that this specific Ampleon product is automotive qualified, the product
is not suitable for automotive use. It is neither qualified nor tested in
accordance with automotive testing or application requirements. Ampleon
accepts no liability for inclusion and/or use of non-automotive qualified
products in automotive equipment or applications.
Translations —
A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
12.4 Trademarks
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without Ampleon’s warranty of the product for such
automotive applications, use and specifications, and (b) whenever customer
uses the product for automotive applications beyond Ampleon’s specifications
such use shall be solely at customer’s own risk, and (c) customer fully
indemnifies Ampleon for any liability, damages or failed product claims
resulting from customer design and use of the product for automotive
applications beyond Ampleon’s standard warranty and Ampleon’s product
specifications.
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Any reference or use of any ‘NXP’ trademark in this document or in or on the
surface of Ampleon products does not result in any claim, liability or
entitlement vis-à-vis the owner of this trademark. Ampleon is no longer part of
the NXP group of companies and any reference to or use of the ‘NXP’
trademarks will be replaced by reference to or use of Ampleon’s own
trademarks.
13. Contact information
BLC9G20XS-400AVT
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Product data sheet
Rev. 3 — 24 November 2017
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BLC9G20XS-400AVT
Power LDMOS transistor
14. Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . .
1
1.1
1.2
1.3
General description
. . . . . . . . . . . . . . . . . . . . .
1
Features and benefit
s
. . . . . . . . . . . . . . . . . . . .
1
Applications .
. . . . . . . . . . . . . . . . . . . . . . . . . .
1
2
3
4
5
6
Pinning informatio
n
. . . . . . . . . . . . . . . . . . . . . .
2
Ordering informatio
n
. . . . . . . . . . . . . . . . . . . . .
2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . .
2
Thermal characteristics
. . . . . . . . . . . . . . . . . .
2
Characteristic
s
. . . . . . . . . . . . . . . . . . . . . . . . . .
3
7
7.1
7.2
7.3
7.4
7.5
7.5.1
7.5.2
7.5.3
7.5.4
Test informatio
n
. . . . . . . . . . . . . . . . . . . . . . . . .
4
Ruggedness in Doherty operation
. . . . . . . . . .
4
Impedance information . . . . . . . . . . . . . . . . . . .
4
Recommended impedances for Doherty design 5
T
e
st circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
Graphical data
. . . . . . . . . . . . . . . . . . . . . . . . .
8
Pulsed CW . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
1-Carrier W-CDMA . . . . . . . . . . . . . . . . . . . . . .
9
2-Carrier W-CDMA . . . . . . . . . . . . . . . . . . . . .
10
2-
T
o
ne VBW . . . . . . . . . . . . . . . . . . . . . . . . . .
11
8
Package outline . . . . . . . . . . . . . . . . . . . . . . . .
12
Handling information. . . . . . . . . . . . . . . . . . . .
13
Abbreviation
s
. . . . . . . . . . . . . . . . . . . . . . . . . .
1
3
Revision histor
y
. . . . . . . . . . . . . . . . . . . . . . . .
1
4
9
10
11
12
Legal information. . . . . . . . . . . . . . . . . . . . . . .
15
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
15
Definition
s
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
5
Disclaimer
s
. . . . . . . . . . . . . . . . . . . . . . . . . . .
1
5
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . .
16
12.1
12.2
12.3
12.4
13
14
Contact information. . . . . . . . . . . . . . . . . . . . .
16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© Ampleon Netherlands B.V.
2017.
All rights reserved.
Date of release: 24 November 2017
Document identifier: BLC9G20XS-400AVT
