Analog-Devices-AD6657ABBCZRL

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Quad IF Receiver

AD6657A

Data Sheet

FEATURES

FUNCTIONAL BLOCK DIAGRAM

AVDD

AGND

DRVDD DRGND

11-bit, 200 MSPS output data rate per channel

Integrated noise shaping requantizer

Performance with NSR enabled

SNR: 76.0 dBFS in 40 MHz band to 70 MHz at 185 MSPS

SNR: 73.6 dBFS in 60 MHz band to 70 MHz at 185 MSPS

SNR: 72.8 dBFS in 65 MHz band to 70 MHz at 185 MSPS

Performance with NSR disabled

SNR: 66.5 dBFS to 70 MHz at 185 MSPS

SFDR: 88 dBc to 70 MHz at 185 MSPS

Low power: 1.2 W at 185 MSPS

1.8 V analog supply operation

1.8 V LVDS (ANSI-644 levels) output

1-to-8 integer clock divider

Internal ADC voltage reference

1.75 V p-p analog input range (programmable to 2.0 V p-p)

Differential analog inputs with 800 MHz bandwidth

95 dB channel isolation/crosstalk

AD6657A

DCO±AB

DO±AB

VIN+A

VIN–A

VCMA

VIN+B

VIN–B

VCMB

VIN+C

VIN–C

VCMC

VIN+D

VIN–D

VCMD

PIPELINE

ADC

NOISE SHAPING

REQUANTIZER

PORT A

NOISE SHAPING

REQUANTIZER

PIPELINE

ADC

D10±AB

DCO±CD

DO±CD

NOISE SHAPING

REQUANTIZER

PIPELINE

ADC

PORT B

NOISE SHAPING

REQUANTIZER

PIPELINE

ADC

D10±CD

MODE

SYNC

PDWN

REFERENCE

CLOCK

DIVIDER

SERIAL PORT

Serial port control

User-configurable built-in self test (BIST) capability

Energy saving power-down modes

SCLK SDIO

CSB

CLK+ CLK–

Figure 1.

APPLICATIONS

Communications

Diversity radio and smart antenna (MIMO) systems

Multimode digital receivers (3G)

WCDMA,

E, CDMA2000

WiMAX, TD-SCDMA

I/Q demodulation systems

General-purpose software radios

Each ADC output is connected internally to an NSR block. The

integrated NSR circuitry allows for improved SNR performance in

a smaller frequency band within the Nyquist bandwidth. The

device supports two different output modes selectable via the

external MODE pin or the serial port interface (SPI).

GENERAL DESCRIPTION

AD6657A

is a

n 11-bit, 200 MSPS, quad channel intermediate

frequency (IF) receiver specifically designed to support multiple

antenna systems in telecommunication applications where high

dynamic range performance, low power, and small size are desired.

With the NSR feature enabled, the outputs of the ADCs are

processed such that the

AD6657A

upports enhanced SNR per-

formance within a limited portion of the Nyquist bandwidth while

maintaining an 11-bit output resolution. The NSR block can be

programmed to provide a bandwidth of either 22%, 33%, or 36% of

the sample clock. For example, with a sample clock rate of

185 MSPS, th

AD6657A

can achieve up to 76.0 dBFS SNR for a

40 MHz bandwidth in the 22% mode, up to 73.6 dBFS SNR for a

60 MHz bandwidth in the 33% mode, or up to 72.8 dBFS SNR for a

65 MHz bandwidth in the 36% mode.

The device consists of four high performance ADCs and NSR

digital blocks. Each ADC consists of a multistage, differential

pipelined architecture with integrated output error correction

logic. The ADC features a wide bandwidth switched capacitor

sampling network within the first stage of the differential pipeline.

An integrated voltage reference eases design considerations. A

duty cycle stabilizer (DCS) compensates for variations in the

ADC clock duty cycle, allowing the converters to maintain

excellent performance.

(General Description continued on Page 3)

Rev. A

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registere

rademarks ar

he property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

AD6657A

Data Sheet

TABLE OF CONTENTS

Features …………………………………………………………………………………. 1

Channel/Chip Synchronization………………………………………… 23

Digital Outputs ………………………………………………………………… 24

Timing……………………………………………………………………………… 24

Noise Shaping Requantizer ………………………………………………….. 25

22% BW Mode (>40 MHz at 184.32 MSPS)……………………… 25

33% BW Mode (>60 MHz at 184.32 MSPS)……………………… 26

36% BW Mode (>65 MHz at 184.32 MSPS)……………………… 27

MODE Pin……………………………………………………………………….. 27

Built-In Self

st (BIST) and Output

……………………………. 28

BIST…………………………………………………………………………………. 28

Output Test Modes…………………………………………………………… 28

Serial Port Interface (SPI)…………………………………………………….. 29

Configuration Using the SPI…………………………………………….. 29

Hardware Interface…………………………………………………………… 29

Memory Map ………………………………………………………………………. 30

Reading the Memory Map Register Table…………………………. 30

Memory Map Register Table…………………………………………….. 31

Memory Map Register Descriptions…………………………………. 33

Applications Information …………………………………………………….. 35

Design Guidelines ……………………………………………………………. 35

Packaging and Ordering Information ………………………………….. 36

Outline Dimension

…………………………………………………………. 36

Ordering Guide ……………………………………………………………….. 36

Applications…………………………………………………………………………… 1

Functional Block Diagram …………………………………………………….. 1

General Descriptio

……………………………………………………………… 1

Revision History ……………………………………………………………………. 2

Product Highlights ………………………………………………………………… 3

Specifications…………………………………………………………………………. 4

DC Specifications ………………………………………………………………. 4

AC Specifications……………………………………………………………….. 5

Digital Specifications …………………………………………………………. 7

Switching Specifications …………………………………………………….. 9

Timing Specifications ………………………………………………………. 10

Absolute Maximum Ratings …………………………………………….. 11

Thermal Characteristics …………………………………………………… 11

ESD Caution…………………………………………………………………….. 11

Pin Configuration and Function Descriptions……………………… 12

Typical Performance Characteristics ……………………………………. 14

Equivalent Circuits ………………………………………………………………. 18

Theory of Operation ……………………………………………………………. 19

ADC Architecture ……………………………………………………………. 19

Analog Input Considerations……………………………………………. 19

Clock Input Considerations ……………………………………………… 21

Power Dissipation and Standby Mode………………………………. 23

REVISION HISTORY

2/14—Rev. 0 to Rev. A

Changed DCO to Data Skew (t

SKEW

) Parameter Unit from ns to

ps, Table 4 ……………………………………………………………………………… 9

10/11—Revision 0: Initial Version

Rev. A | Page 2 of 36

Data Sheet

AD6657A

With the NSR block disabled, the ADC data is provided directly to

the output with a resolution of 11 bits. The

AD6657A

can achieve

up to 66.5 dBFS SNR for the entire Nyquist bandwidth when

operated in this mode. This allows the

AD6657A

to be used in

telecommunication applications such as a digital predistortion

observation path where wider bandwidths are used.

(CSP_BGA) that is specified over the industrial temperature

range of −40°C to +85°C.

PRODUCT HIGHLIGHTS

1. Four

analog-to-digital converters (ADCs) are contained in

a small, space-saving, 10 mm × 10 mm × 1.4 mm, 144-ball

CSP_BGA package.

2. Pin

selectable noise shaping requantizer (NSR) function

that allows for improved SNR within a reduced bandwidth

of up to 65 MHz at 185 MSPS.

After digital signal processing, multiplexed output data is

routed into two 11-bit output ports such that the maximum

digital data rate (DDR) is 400 Mbps. These outputs are set at

1.8 V LVDS and support ANSI-644 levels.

3. LVDS

digital output interface configured for low cost

The

AD6657A

receiver digitizes a wide spectrum of IF frequencies.

Each receiver is designed for simultaneous reception of a separate

antenna. This IF sampling architecture greatly reduces component

cost and complexity compared with traditional analog techniques

or less integrated digital methods.

FPGA families.

4. 230

mW per ADC core power consumption.

5. Operation

from a single 1.8 V supply.

6. Standard

SPI that supports various product features and

functions, such as data formatting (offset binary or twos

complement), NSR, power-down, test modes, and voltage

reference mode.

7. On-chip

integer 1-to-8 input clock divider and multichip

sync function to support a wide range of clocking schemes

and multichannel subsystems.

Flexible power-down options allow significant power savings.

Programming for device setup and control is accomplished

using a 3-wire SPI-compatible serial interface with numerous

modes to support board level system testing.

The

AD6657A

is available in a Pb-free, RoHS compliant,

144-ball, 10 mm × 10 mm chip scale package ball grid array

Rev. A | Page 3 of 36

AD6657A

Data Sheet

SPECIFICATIONS

DC SPECIFICATIONS

DD = 1.8

RVDD = 1.8

= 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless

otherwise noted.

Table 1.

Parameter

Temperature

Min

Typ

Max

Unit

RESOLUTION

Full

Bits

ACCURACY

No Missing Codes

Offset Error

Gain Error

Differential Nonlinearity (DNL)

Integral Nonlinearity (I

NL)

MATCHING CHARACTERISTIC

Offset Error

Full

Guaranteed

+0.1

+11

0.1

0.17

−0.9

−0.4

−0.55

+0.9

+18

+0.4

+0.55

% FSR

LSB

Full

−5

+2.1

+11

% FSR

Gain Error

TEMPERATURE DRIFT

Offset Error

Gain Error

Full

ppm/°C

ANALOG INPUT

Input Range

Full

1.4

1.75

0.95

2.0

V p-p

kΩ

Input Common-Mode Voltage

Input Resistance (Differential)

Input Capacitance

POWER SUPPLIES

Supply Voltage

AVDD

Full

1.7

1.8

1.9

DRVDD

Supply Current

AVD

Full

466

170

510

183

DRV

(1.8 V LVDS)

POWER CONSUMPTION

Sine Wave Inpu

Standby Power

Power-Down Power

Full

1145

129

3.8

1247

^{1
Measured with a 10 MHz, 0 dBFS sine wave, with 100 Ω termination on each LVDS output pair.}

^{2
Input capacitance refers to the effective capacitance between one differential input pin and AGND.}

^{3
Standby power is measured with a dc input and the CLKx pins inactive (set to AVDD or AGND).}

Rev. A | Page 4 of 36

Data Sheet

AD6657A

AC SPECIFICATIONS

DD = 1.8

RVDD = 1.8

= 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless

otherwise noted.

Table 2.

Parameter

Temperature Min

Typ

Max

Unit

SIGNAL-TO-NOISE-RATIO (SNR)—NSR DISABLED

= 10 MHz

= 50 MHz

= 70 MHz

= 170 MHz

25°C

Full

25°C

66.6

66.5

66.3

dBFS

65.6

= 250 MHz

65.9

SIGNAL-TO-NOISE-RATIO (SNR)—NSR ENABLED

22% BW Mode

= 10 MHz

= 50 MHz

= 70 MHz

= 170 MHz

25°C

Full

76.0

75.7

74.3

dBFS

72.9

71.3

70.7

64.6

= 250 MHz

33% BW Mode

= 10 MHz

= 50 MHz

= 70 MHz

25°C

72.8

25°C

Full

73.6

73.3

72.5

dBFS

= 170 MHz

= 230 MHz

36% BW Mode

= 10 MHz

= 50 MHz

= 70 MHz

25°C

71.2

25°C

Full

72.8

72.6

71.8

dBFS

= 170 MHz

= 250 MHz

SIGNAL-TO-NOISE-AND DISTORTION (SINAD)

= 10 MHz

= 50 MHz

= 70 MHz

25°C

70.8

25°C

Full

65.5

65.3

dBFS

= 170 MHz

= 250 MHz

EFFECTIVE NUMBER OF BITS (ENOB)

= 10 MHz

= 50 MHz

= 70 MHz

25°C

64.8

25°C

10.6

10.5

Bits

= 170 MHz

= 250 MHz

Rev. A | Page 5 of 36

AD6657A

Data Sheet

Parameter

Temperature Min

Typ

Max

Unit

WORST SECOND OR THIRD HARMONIC

= 10 MHz

= 50 MHz

= 70 MHz

= 170 MHz

25°C

Full

−94

−91

−88

−90

dBc

−80

= 250 MHz

25°C

−83

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

= 10 MHz

= 50 MHz

= 70 MHz

= 170 MHz

25°C

Full

25°C

dBc

= 250 MHz

WORST OTHER HARMONIC (FOURTH THROUGH EIGHTH)

= 10 MHz

= 50 MHz

= 70 MHz

= 170 MHz

25°C

Full

−94

−95

−94

dBc

−80

= 250 MHz

25°C

−90

TWO TONE SFDR (−7 dBFS)

IN1

= 169 MHz, f

IN2

= 172 MHz

CROSSTALK

25°C

Full

dBc

ANALOG INPUT BANDWIDTH

25°C

800

MHz

^{1
See th
e
AN-835 Application Note
,
Understanding High Speed ADC Testing and Evaluation
, for a complete set of definitions.}

^{2
Crosstalk is measured at 155 MHz with −1 dBFS on one channel and no input on the alternate channel.}

Rev. A | Page 6 of 36

Data Sheet

AD6657A

DIGITAL SPECIFICATIONS

DD = 1.8

RVDD = 1.8

= 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless

otherwise noted.

Table 3.

Parameter

Temperature Min

Typ

Max

Unit

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance

CMOS/LVDS/LVPECL

0.9

Internal Common-Mode Bias

Differential Input Voltage

Input Voltage Range

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Resistance

Full

0.2

AGND − 0.3

3.6

AVDD + 0.2

V p-p

1.2

−10

2.0

0.8

+10

µA

kΩ

Input Capacitance

SYNC INPUT

Logic Compliance

Internal Bias

CMOS

0.9

Full

Input Voltage Range

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Resistance

AGND

1.2

AGND

−100

AVDD

0.6

+100

µA

kΩ

Input Capacitance

LOGIC INPUT (CSB)

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Resistance

Full

1.22

−10

2.1

0.6

+10

132

µA

kΩ

Input Capacitance

LOGIC INPUT (SCLK)

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Resistance

Full

1.22

−92

−10

2.1

0.6

−135

+10

µA

kΩ

Input Capacitance

LOGIC INPUT/OUTPUT (SDIO

)

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Resistance

Full

1.22

−10

2.1

0.6

+10

128

µA

kΩ

Input Capacitance

Rev. A | Page 7 of 36

AD6657A

Data Sheet

Parameter

Temperature Min

Typ

Max

Unit

LOGIC INPUT (MO

DE)

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Resistance

Full

1.22

−10

2.1

0.6

+10

132

µA

kΩ

Input Capacitance

LOGIC INPUT (PDWN

)

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Resistance

Full

1.22

−90

−10

2.1

0.6

−134

+10

µA

kΩ

Input Capacitance

DIGITAL OUTPUTS (LVDS)

Differential Output Voltage (V

)

Output Offset Voltage (V

)

Full

247

1.125

454

1.375

^{1
Pull up.}

^{2
Pull down.}

Rev. A | Page 8 of 36

Data Sheet

AD6657A

SWITCHING SPECIFICATIONS

DD = 1.8

RVDD = 1.8

= 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless

otherwise noted.

Table 4.

Parameter

Temperature Min

Typ

Max

Unit

CLOCK INPUT PARAMETERS

Input Clock Rate

Full

625

200

MHz

MSPS

ps rms

Conversion Rate

Full

185

2.7

1.3

CLK Pulse Width High (t

)

Aperture Delay (t

)

Aperture Uncertainty (Jitter, t

)

0.13

DATA OUTPUT PARAMETERS

Data Propagation Delay (t

)

Full

3.0

3.1

−41

4.9

+33

Cycles

µs

4.0

+6.1

0.5

310

DCO Propagation Delay (t

DCO

)

DCO to Data Skew (t

SKEW

)

Pipeline Delay (Latency)

With NSR Enabled

Wake-Up Time (from Standby)

Wake-Up Time (from Power Down

)

OUT-OF-RANGE RECOVERY TIME

µs

Cycles

^{1
Conversion rate is the clock rate after the divider.}

^{2
S
ee Figure 2
for details.}

^{3
Wake-up time is dependent on the value of the decoupling capacitors.}

Data Output Timing Diagram

N – 1

N + 4

N + 5

N + 3

VIN

N + 1

N + 2

CLK+

CLK–

DCO

DCO+

DCO–

SKEW

D10+AB (MSB)

D10–AB (MSB)

D10A

D0A

D10B

D0B

D10A

D10B

D10A

D10B

D0B

D10A

D0A

D10B

D0B

D10A

D0A

D10B

D0B

D10A

D0A

D10B

D0B

D10A

D0A

D10B

D0B

D0+AB (LSB)

D0–AB (LSB)

D0A

D0B

D0A

Figure 2. Data Output Timing (Timing for Channel C and Channel D Is Identical to Timing for Channel A and Channel B)

Rev. A | Page 9 of 36

AD6657A

Data Sheet

TIMING SPECIFICATIONS

DD = 1.8

RVDD = 1.8

= 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless

otherwise noted.

Table 5.

Parameter

Description

Min

Typ

Max

Unit

SYNC TIMING REQUIREMENTS

ee Figure 3

for details

SSYNC

HSYNC

SYNC to rising edge of CLK setup time

SYNC to rising edge of CLK hold time

ee Figure 60

for details, except where noted

Setup time between the data and the rising edge of SCLK

Hold time between the data and the rising edge of SCLK

Period of the SCLK

Setup time between CSB and SCLK

Hold time between CSB and SCLK

SCLK pulse width high

0.24

0.40

SPI TIMING REQUIREMENTS

CLK

HIGH

LOW

EN_SDIO

SCLK pulse width low

Time required for the SDIO pin to switch from an input to

an output relative to the SCLK falling edge (not pictured in

Figure 60)

DIS_SDIO

Time required for the SDIO pin to switch from an output to

an input relative to the SCLK rising edge (not pictured in

Figure 60)

Sync Input Timing Diagram

CLK+

SSYNC

HSYNC

SYNC

Figure 3. SYNC Input Timing Requirements

Rev. A | Page 10 of 36

Data Sheet

AD6657A

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

Table 6.

The values in

Table 7

are per JEDEC JESD51-7 and JEDEC

JESD25-5 for a 2S2P test board. Typical θ

is specified for a

4-layer printed circuit board (PCB) with a solid ground plane.

As shown i

n Table 7,

airflow improves heat dissipation, which

reduces θ

. In addition, metal in direct contact with the

package leads from metal traces, through holes, ground, and

power planes reduces θ

Parameter

Rating

AVDD to AGND

DRVDD to AGND

VIN+x, VIN−x to AGND

CLK+, CLK− to AGND

SYNC to AGND

VCMx to AGND

CSB to AGND

SCLK to AGND

−0.3 V to +2.0 V

−0.3 V to AVDD + 0.2 V

−0.3 V to DRVDD + 0.2 V

Table 7.

Airflow

Velocity

SDIO to AGND

Package Type

8.9

6.6

Unit

°C/W

PDWN to AGND

MODE to AGND

Digital Outputs to AGND

DCO+AB, DCO−AB, DCO+CD,

DCO−CD to AGND

Operating Temperature Range

(Ambient)

Maximum Junction Temperature

Under Bias

144-Ball CSP_BGA

0 m/s

1 m/s

2.5 m/s

26.9

24.2

23.0

^{1
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).}

^{2
Per MIL-STD 883, Method 1012.1.}

−40°C to +85°C

150°C

^{3
Per JEDEC JESD51-8 (still air).}

The values in

Table 8

are from simulations. The PCB is a JEDEC

multilayer board. Thermal performance for actual applications

requires careful inspection of the conditions in the application

to determine whether they are similar to those assumed in these

calculations.

Storage Temperature Range

(Ambient)

−65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 8.

Airflow

Velocity

Package Type

Unit

°C/W

144-Ball CSP_BGA

0 m/s

14.4

14.0

13.9

0.23

0.50

0.53

1 m/s

2.5 m/s

ESD CAUTION

Rev. A | Page 11 of 36

AD6657A

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AGND

VIN+D

VIN–D

AGND

VIN+C

AGND

VCMD

AVDD

AGND

VIN–C

VCMC

AGND

AVDD

AGND

CSB

AVDD

SDIO

AVDD

AGND

CLK–

AVDD

SCLK

AVDD

AGND

CLK+

AVDD

PDWN

AVDD

AGND

AVDD

SYNC

AVDD

AGND

MODE

AVDD

AGND

VIN–B

VCMB

AGND

AVDD

AGND

VIN+B

AGND

VCMA

AVDD

AGND

VIN+A

VIN–A

AGND

AVDD

AGND

DRGND DRGND DRGND DRGND DRGND DRGND DRGND DRGND DRGND DRGND DRGND DRGND

DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD

D0–CD

D0+CD

D1–CD

D1+CD

D2–CD

D2+CD

D3–CD

D3+CD

D4–CD

D4+CD

D5–CD

D5+CD

D6–CD

D6+CD

D7–CD

D7+CD

D8–CD D10–CD D0–AB

D8+CD D10+CD D0+AB

D9–CD DCO–CD D1–AB

D9+CD DCO+CD D1+AB

D2–AB

D2+AB

D3–AB

D3+AB

D4–AB

D4+AB

D5–AB

D5+AB

D6–AB

D6+AB

D7–AB

D7+AB

D8–AB D10–AB

D8+AB D10+AB

D9–AB DCO–AB

D9+AB DCO+AB

Figure 4. Pin Configuration (Top View)

Table 9. Pin Function Descriptions

Pin No.

Mnemonic

Type

Description

A5, A8, B5 to B8, D4 to

D9, E2 to E11

AVDD

Supply

Analog Power Supply. 1.8 V nominal.

A1, A4, A9, A12, B1, B2,

B4, B9, B11, B12, C2, C3,

C10, C11, D3, D10, E1,

E12, F1 to F12

AGND

Ground

Analog Ground.

H1 to H12

G1 to G12

DRVDD

DRGND

CLK+

Supply

Ground

Input

Digital Output Driver Supply. 1.8 V nominal.

Digital Output Driver Ground.

ADC Clock Input—True.

CLK−

Input

ADC Clock Input—Complement.

C12

D12

D11

A11

A10

B10

VIN+A

VIN−A

VCMA

VIN+B

VIN−B

VCMB

Input

Output

Input

Output

Input

Output

Input

Output

Differential Analog Input Pin (+) for Channel A.

Differential Analog Input Pin (−) for Channel A.

Common-Mode Level Bias Output for Analog Input Channel A.

Differential Analog Input Pin (+) for Channel B.

Differential Analog Input Pin (−) for Channel B.

Common-Mode Level Bias Output for Analog Input Channel B.

Differential Analog Input Pin (+) for Channel C.

Differential Analog Input Pin (−) for Channel C.

Common-Mode Level Bias Output for Analog Input Channel C.

Differential Analog Input Pin (+) for Channel D.

VIN+C

VIN−C

VCMC

VIN+D

VIN−D

VCMD

D0+AB

D0−AB

D1+AB

D1−AB

D2+AB

D2−AB

D3+AB

D3−AB

D4+AB

D4−AB

Differential Analog Input Pin (−) for Channel D.

Common-Mode Level Bias Output for Analog Input Channel D.

Channel A and Channel B LVDS Output Data 0—True.

Channel A and Channel B LVDS Output Data 0—Complement.

Channel A and Channel B LVDS Output Data 1—True.

Channel A and Channel B LVDS Output Data 1—Complement.

Channel A and Channel B LVDS Output Data 2—True.

Channel A and Channel B LVDS Output Data 2—Complement.

Channel A and Channel B LVDS Output Data 3—True.

Channel A and Channel B LVDS Output Data 3—Complement.

Channel A and Channel B LVDS Output Data 4—True.

Channel A and Channel B LVDS Output Data 4—Complement.

Rev. A | Page 12 of 36

Data Sheet

AD6657A

Pin No.

Mnemonic

D5+AB

D5−AB

D6+AB

D6−AB

D7+AB

D7−AB

D8+AB

D8−AB

D9+AB

D9−AB

D10+AB

D10−AB

DCO+AB

DCO−AB

D0+CD

D0−CD

D1+CD

D1−CD

D2+CD

D2−CD

D3+CD

D3−CD

D4+CD

D4−CD

D5+CD

D5−CD

D6+CD

D6−CD

D7+CD

D7−CD

D8+CD

D8−CD

D9+CD

D9−CD

D10+CD

D10−CD

DCO+CD

DCO−CD

MODE

Type

Description

Output

Input

Channel A and Channel B LVDS Output Data 5—True.

Channel A and Channel B LVDS Output Data 5—Complement.

Channel A and Channel B LVDS Output Data 6—True.

Channel A and Channel B LVDS Output Data 6—Complement.

Channel A and Channel B LVDS Output Data 7—True.

Channel A and Channel B LVDS Output Data 7—Complement.

Channel A and Channel B LVDS Output Data 8—True.

Channel A and Channel B LVDS Output Data 8—Complement.

Channel A and Channel B LVDS Output Data 9—True.

Channel A and Channel B LVDS Output Data 9—Complement.

Channel A and Channel B LVDS Output Data 10—True.

Channel A and Channel B LVDS Output Data 10—Complement.

Data Clock LVDS Output for Channel A and Channel B—True.

Data Clock LVDS Output for Channel A and Channel B—Complement.

Channel C and Channel D LVDS Output Data 0—True.

Channel C and Channel D LVDS Output Data 0—Complement.

Channel C and Channel D LVDS Output Data 1—True.

Channel C and Channel D LVDS Output Data 1—Complement.

Channel C and Channel D LVDS Output Data 2—True.

Channel C and Channel D LVDS Output Data 2—Complement.

Channel C and Channel D LVDS Output Data 3—True.

Channel C and Channel D LVDS Output Data 3—Complement.

Channel C and Channel D LVDS Output Data 4—True.

Channel C and Channel D LVDS Output Data 4—Complement.

Channel C and Channel D LVDS Output Data 5—True.

Channel C and Channel D LVDS Output Data 5—Complement.

Channel C and Channel D LVDS Output Data 6—True.

Channel C and Channel D LVDS Output Data 6—Complement.

Channel C and Channel D LVDS Output Data 7—True.

Channel C and Channel D LVDS Output Data 7—Complement.

Channel C and Channel D LVDS Output Data 8—True.

Channel C and Channel D LVDS Output Data 8—Complement.

Channel C and Channel D LVDS Output Data 9—True.

Channel C and Channel D LVDS Output Data 9—Complement.

Channel C and Channel D LVDS Output Data 10—True.

Channel C and Channel D LVDS Output Data 10—Complement.

Data Clock LVDS Output for Channel C and Channel D—True.

Data Clock LVDS Output for Channel C and Channel D—Complement.

Mode Select Pin. Logic low enables NSR; logic high disables NSR.

Digital Synchronization Pin.

K10

J10

M10

L10

K11

J11

M11

L11

K12

J12

M12

L12

SYNC

Input

PDWN

Input

Power-Down Input (Active High).

SCLK

Input

SPI Clock.

SDIO

CSB

Input/Output SPI

Data.

Input SPI

Chip Select (Active Low).

Rev. A | Page 13 of 36

AD6657A

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

DD = 1.8

RVDD = 1.8

ample rate = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS, 32,000 sample, T

= 25°C,

unless otherwise noted.

–20

–40

–20

–40

185MSPS

10.3MHz @ –1dBFS

SNR = 65.6dB (66.6dBFS)

SFDR = 94.0dBc

140.3MHz @ –1dBFS

SNR = 65.4dB (66.4dBFS)

SFDR = 90dBc

–60

–80

–60

–80

SECOND HARMONIC

THIRD HARMONIC

SECOND HARMONIC

–100

–120

–100

–120

9.25 18.50

27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50

FREQUENCY (MHz)

9.25 18.50

27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50

FREQUENCY (MHz)

Figure 5. Single Tone FFT, f

= 10.3 MHz

Figure 8. Single Tone FFT, f

= 140.3 MHz

–20

–40

–20

–40

185MSPS

50.3MHz @ –1dBFS

SNR = 65.6dB (66.6dBFS)

SFDR = 92.0dBc

200.3MHz @ –1dBFS

SNR = 64.9dB (65.9dBFS)

SFDR = 84dBc

–60

–80

–60

–80

THIRD HARMONIC

SECOND HARMONIC

THIRD HARMONIC

–100

–120

–100

–120

9.25 18.50

27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50

FREQUENCY (MHz)

9.25 18.50

27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50

FREQUENCY (MHz)

Figure 6. Single Tone FFT, f

= 50.3 MHz

Figure 9. Single Tone FFT, f

= 200.3 MHz

–20

–40

–20

–40

185MSPS

70.3MHz @ –1dBFS

SNR = 65.5dB (66.5dBFS)

SFDR = 88dBc

230.3MHz @ –1dBFS

SNR = 66.1dB (65.1dBFS)

SFDR = 84dBc

–60

–80

–60

–80

SECOND HARMONIC

THIRD HARMONIC

SECOND HARMONIC

THIRD HARMONIC

–100

–120

–100

–120

9.25 18.50

27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50

FREQUENCY (MHz)

9.25 18.50

27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50

FREQUENCY (MHz)

Figure 7. Single Tone FFT, f

= 70.3 MHz

Figure 10. Single Tone FFT, f

= 230.3 MHz

Rev. A | Page 14 of 36

Data Sheet

AD6657A

–20

–40

–60

185MSPS

230.3MHz @ –1dBFS

NSR 33% BW MODE, TW = 17

SNR = 70.8dB (72.5dBFS)

SFDR = 93.7dBc

185MSPS

247.3MHz @ –1dBFS

SNR = 66dB (65dBFS)

SFDR = 83dBc

–20

–40

–60

SECOND HARMONIC

THIRD HARMONIC

SECOND HARMONIC

THIRD HARMONIC

–80

–100

–120

–80

–100

–120

–140

9.25 18.50

27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50

FREQUENCY (MHz)

9.25 18.50

27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50

FREQUENCY (MHz)

Figure 11. Single Tone FFT, f

= 247.3 MHz

Figure 14. Single Tone FFT, f

= 230.3 MHz, NSR Enabled

in 33% BW Mode, Tuning Word = 17

185MSPS

305.3MHz @ –1dBFS

SNR = 64.9dB (65.9dBFS)

SFDR = 80dBc

230.3MHz @ –1dBFS

NSR 36% BW MODE, TW = 14

SNR = 70.3dB (71.3dBFS)

SFDR = 93.4dBc

–20

–40

–60

–20

–40

–60

THIRD HARMONIC

–80

–100

–120

SECOND HARMONIC

–80

–100

–120

–140

9.25 18.50

27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50

FREQUENCY (MHz)

9.25 18.50

27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50

FREQUENCY (MHz)

Figure 12. Single Tone FFT, f

= 305.3 MHz

Figure 15. Single Tone FFT, f

= 230.3 MHz, NSR Enabled

in 36% BW Mode, Tuning Word = 14

–20

–40

–60

100

185MSPS

140.3MHz @ –1dBFS

NSR 22% BW MODE, TW = 28

SNR = 73.4dB (74.9dBFS)

SFDR = 91dBc

SFDR (dBFS)

SNR (dBFS)

THIRD HARMONIC

SFDR (dBc)

–80

–100

–120

SNR (dBc)

–140

9.25 18.50

27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50

FREQUENCY (MHz)

INPUT AMPLITUDE (dBFS)

Figure 16. Single Tone SNR/SFDR vs. Input Amplitude (A

= 70.3 MHz

Figure 13. Single Tone FFT, f

= 140.3 MHz, NSR Enabled

in 22% BW Mode, Tuning Word = 28

Rev. A | Page 15 of 36

AD6657A

Data Sheet

100

SFDR (dBFS)

SFDR (dBc)

SNR (dBFS)

SFDR (dBc)

SNR (dBFS)

SNR (dBc)

30.00 51.25 72.50 93.75

115.00 136.25 157.50 178.75 200.00

SAMPLE RATE (MSPS)

INPUT AMPLITUDE (dBFS)

Figure 17. Single Tone SNR/SFDR vs. Input Amplitude (A

= 140.3 MHz

Figure 20. Single Tone SNR/SFDR vs. Sample Rate (f

= 70.3 MHz

SFDR (dBc)

SNR (dBFS)

30.00 51.25 72.50 93.75

115.00 136.25 157.50 178.75 200.00

SAMPLE RATE (MSPS)

INPUT FREQUENCY (MHz)

Figure 18. Single Tone SNR/SFDR vs. Input Frequency (f

1.75 V p-p Full Scale

Figure 21. Single Tone SNR/SFDR vs. Sample Rate (f

= 140.3 MHz

185MSPS

169.1MHz @ –7dBFS

172.1MHz @ –7dBFS

SFDR = 88.5dBc

–20

SFDR (dBc)

–40

–60

–80

SNR (dBFS)

–100

–120

9.25 18.50

27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50

FREQUENCY (MHz)

INPUT FREQUENCY (MHz)

Figure 22. Two Tone FFT, f

IN1

= 169.1 MHz and f

IN2

= 172.1 MHz

Figure 19. Single Tone SNR/SFDR vs. Input Frequency (f

2.0 V p-p Full Scale

Rev. A | Page 16 of 36

Data Sheet

AD6657A

–20

–40

–60

0.20

0.15

0.10

0.05

SFDR (dBc)

IMD3 (dBc)

–0.05

–80

SFDR (dBFS)

–0.10

–0.15

–0.20

–100

IMD3 (dBFS)

–120

–90

–78

–66

–54

–42

–30

–18

–6

N + 3

2000

500

1000

1500

2000

INPUT AMPLITUDE (dBFS)

OUTPUT CODE

Figure 23. Two Tone SFDR/IMD3 vs. Input Amplitude (A

_{IN1
= 169.1 MHz and f
IN2
= 172.1 MHz}

Figure 26. DNL, f

= 30.3 MHz

2,500,000

2,000,000

1,500,000

1,000,000

500,000

N – 3

N – 2

N – 1

N + 1

N + 2

OUTPUT CODE

DUTY CYCLE (%)

Figure 24. Grounded Input Histogram

Figure 27. SNR vs. Duty Cycle, f

= 10.3 MHz

1.0

0.8

0.6

0.4

0.2

–0.2

–0.4

–0.6

–0.8

–1.0

500

1000

1500

OUTPUT CODE

Figure 25. INL, f

= 30.3 MHz

Rev. A | Page 17 of 36

AD6657A

Data Sheet

EQUIVALENT CIRCUITS

AVDD

350

Ω

30k

Ω

SCLK

PDWN

VIN

Figure 28. Equivalent Analog Input Circuit

Figure 32. Equivalent SCLK and PDWN Input Circuit

AVDD

kΩ

350

Ω

AVDD

0.9V

CSB

MODE

15kΩ

CLK+

CLK–

Figure 29. Equivalent Clock Input Circuit

Figure 33. Equivalent CSB and MODE Input Circuit

DRVDD

V+

V–

DATAOUT–

V–

DATAOUT+

V+

350Ω

SDIO

30kΩ

Figure 30. Equivalent LVDS Output Circuit

Figure 34. Equivalent SDIO Circuit

AVDD

SYNC

0.9V

16kΩ

0.9V

Figure 31. Equivalent SYNC Input Circuit

Rev. A | Page 18 of 36

Data Sheet

AD6657A

THEORY OF OPERATION

A small resistor in series with each input can help reduce the

ADC ARCHITECTURE

peak transient current required from the output stage of the

driving source. A shunt capacitor can be placed across the

inputs to provide dynamic charging currents. This passive

network creates a low-pass filter at the ADC input; therefore,

the precise values are dependent on the application.

The

AD6657A

architecture consists of a quad front-end sample-

and-hold circuit, followed by a pipelined, switched capacitor

ADC. The quantized outputs from each stage are combined into

a final 14-bit result in the digital correction logic. Alternately,

the 14-bit result can be processed through the NSR block before

it is sent to the digital correction logic.

In intermediate frequency (IF) undersampling applications,

any shunt capacitors should be reduced. In combination with

the driving source impedance, the shunt capacitors limit the

input bandwidth. For more information on this subject, see the

AN-742 Application Note

Frequency Domain Response of

Switched-Capacitor ADCs

;

AN-827 Application Note

A Resonant

Approach to Interfacing Amplifiers to Switched-Capacitor ADCs

;

and the

Analog Dialogue

article, “Transformer-Coupled Front-End

for Wideband A/D Converters” (s

www.analog.com

The pipelined architecture permits the first stage to operate on

a new input sample and the remaining stages to operate on the

preceding samples. Sampling occurs on the rising edge of the clock.

Each stage of the pipeline, excluding the last, consists of a low

resolution flash ADC connected to a switched-capacitor digital-

to-analog converter (DAC) and an interstage residue amplifier

(MDAC). The residue amplifier magnifies the difference between

the reconstructed DAC output and the flash input for the next

stage in the pipeline. One bit of redundancy is used in each stage

to facilitate digital correction of flash errors. The last stage

simply consists of a flash ADC.

BIAS

The input stage of each channel contains a differential sampling

circuit that can be ac- or dc-coupled in differential or single-ended

modes. The output staging block aligns the data, corrects errors,

and passes the data to the output buffers. The output buffers are

powered from a separate supply, allowing adjustment of the output

drive current. During power-down, the output buffers go into a

high impedance state.

VIN+

VIN–

PAR1

PAR2

PAR1

PAR2

BIAS

The

AD6657A

quad IF receiver can simultaneously digitize four

channels, making it ideal for diversity reception and digital pre-

distortion (DPD) observation paths in telecommunication systems.

Figure 35. Switched Capacitor Input

For best dynamic performance, match the source impedances

driving the VIN+ and VIN− pins.

Synchronization capability is provided to allow synchronized

timing between multiple channels or multiple devices.

An internal differential reference buffer creates positive and

negative reference voltages that define the input div of the ADC

Programming and control of the

AD6657A

are accomplished

using a 3-wire SPI-compatible serial interface.

core. The div of the ADC core is set by this buffer to 2 × V

REF

Input Common Mode

ANALOG INPUT CONSIDERATIONS

The analog inputs of the

AD6657A

are not internally dc biased.

In ac-coupled applications, the user must provide this bias

externally. An on-board common-mode voltage reference is

included in the design and is available from the VCMx pins.

Optimum performance is achieved when the common-mode

voltage of the analog input is set by the VCMx pin voltage

(typically 0.5 ×

DD). The VCMx pins must be decoupled

to ground by a 0.1 µF capacitor.

The analog input to the

AD6657A

is a differential switched

capacitor circuit that has been designed for optimum perfor-

mance while processing a differential input signal.

The clock signal alternatively switches the input between sample

mode and hold mode (see

Figure 35)

. When the input is switched

to sample mode, the signal source must be capable of charging

the sample capacitors and settling within 1/2 of a clock cycle.

Rev. A | Page 19 of 36

AD6657A

Data Sheet

Differential Input Configurations

The signal characteristics must be considered when selecting

a transformer. Most RF transformers saturate at frequencies

below a few megahertz (MHz). Excessive signal power can also

cause core saturation, which leads to distortion.

Optimum performance is achieved when driving the

AD6657A

in a differential input configuration. For baseband applications,

the

AD8138

ADA4937-2

and

ADA4938-2

differential drivers

provide excellent performance and a flexible interface to the ADC.

At input frequencies in the second Nyquist zone and above, the

noise performance of most amplifiers is not adequate to achieve

the true SNR performance of the

AD6657A

For applications in

which SNR is a key parameter, differential double balun coupling

is the recommended input configuration (s

ee Figure 38)

. In this

configuration, the input is ac-coupled and the CML is provided to

each input through a 33 Ω resistor. These resistors compensate

for losses in the input baluns to provide a 50 Ω impedance to

the driver.

The output common-mode voltage of the

ADA4938-2

is easily

set with the VCMx pin of the

AD6657A

ee Figure 36)

, and the

driver can be configured in a Sallen-Key filter topology to provide

band limiting of the input signal.

15pF

200Ω

33Ω

5pF

15Ω

90Ω

VIN–

VIN+

AVDD

ADC

VCM

76.8Ω

VIN

In the double balun and transformer configurations, the value

of the input capacitors and resistors is dependent on the input

frequency and source impedance and may need to be reduced

or removed.

Table 10

lists recommended values to set the RC

network. At higher input frequencies, good performance can be

achieved by using a ferrite bead in series with a resistor and

removing the capacitors. However, these values are dependent

on the input signal and should be used as a starting guide only.

ADA4938-2

0.1µF

33Ω

120Ω

15pF

200Ω

Figure 36. Differential Input Configuration Using th

ADA4938-2

For baseband applications where SNR is a key parameter,

differential transformer coupling is the recommended input

configuration. An example is shown i

n Figure 37.

ias the

analog input, the VCM voltage can be connected to the center

tap of the secondary winding of the transformer.

Table 10. Example RC Network

Frequency

Range

(MHz)

R1 Series

(Each)

R2 Series

C2 Shunt

C1 Differential

(Each)

0 to 100

100 to 200

100 to 300

33 Ω

10 Ω

5 pF

Remove

15 Ω

10 Ω

66 Ω

15 pF

10 pF

Remove

VIN+

2V p-p

49.9Ω

ADC

VCM

^{1
In this configuration, R1 is a ferrite bead with a value of 10 Ω @ 100 MHz.}

VIN–

An alternative to using a transformer-coupled input at frequen-

cies in the second Nyquist zone is to use the

AD8352

differential

driver (see

Figure 39).

For more information, see the

AD8352

data sheet.

0.1µF

Figure 37. Differential Transformer-Coupled Configuration

0.1µF

VIN+

2V p-p

33Ω

ADC

0.1µF

VCM

VIN–

Figure 38. Differential Double Balun Input Configuration

0.1µF

0Ω

8, 13

0.1µF

ANALOG INPUT

VIN+

200Ω

ADC

AD8352

200Ω

VCM

VIN–

0.1µF

ANALOG INPUT

0Ω

0.1µF

Figure 39. Differential Input Configuration Using th

AD8352

Rev. A | Page 20 of 36

Data Sheet

AD6657A

ANALOG

INPUT

XFMR 1:4 Z

ETC4-1T-7

33Ω

0.1µF

121Ω

431nH

3.0kΩ

0.1µF

INPUT

Z = 50Ω

3.0pF

ADC

INTERNAL

INPUT Z

0.1µF

VCM

Figure 40. 1:4 Transformer Passive Configuration

1000pF 180nH

220nH

1µH

15pF

165Ω

VPOS

AD6657A

AD8376

301Ω

5.1pF

3.9pF

165Ω

VCM

1nF

3.0kΩ║3.0pF

1nF

68nH

180nH 220nH

1000pF

NOTES

1. ALL INDUCTORS ARE COILCRAFT 0603CS COMPONENTS

WITH THE EXCEPTION OF THE 1µH CHOKE INDU

ORS (0603LS).

Figure 41. Active Front-End Configuration Using th

AD8376

Figure 43

and

Figure 44

show two preferred methods for clocking

the

AD6657A

(at clock rates of up to 625 MHz). A low jitter clock

source is converted from a single-ended signal to a differential

signal using either an RF balun or an RF transformer.

For the popular IF band of 140 MHz,

Figure 40

shows an

example of a 1:4 transformer passive configuration where a

differential inductor is used to resonate with the internal input

capacitance of th

AD6657A

This configuration realizes excellent

noise and distortion performance.

Figure 41

shows an example

of an active front-end configuration using the

AD8376

dual vari-

able gain amplifier (VGA). This configuration is recommended

when signal gain is required.

The RF balun configuration is recommended for clock frequencies

between 125 MHz and 625 MHz, and the RF transformer config-

uration is recommended for clock frequencies from 10 MHz to

200 MHz. The back-to-back Schottky diodes across the trans-

former/balun secondary limit clock excursions into the

AD6657A

to approximately 0.8 V p-p differential. This limit helps to prevent

the large voltage swings of the clock from feeding through to

other portions of the

AD6657A

yet preserves the fast rise and

fall times of the signal that are critical to a low jitter performance.

CLOCK INPUT CONSIDERATIONS

For optimum performance, clock the

AD6657A

sample clock

inputs, CLK+ and CLK−, with a differential signal. The signal is

typically ac-coupled into the CLK+ and CLK− pins via a trans-

former or capacitors. These pins are biased internally and require

no external bias (see

Figure 42).

ADT1-1WT, 1:1Z

AVDD

0.1µF

XFMR

CLOCK

INPUT

CLK+

ADC

100Ω

50Ω

1.2V

0.1µF

CLK–

CLK+

CLK–

SCHOTTKY

DIODES:

HSMS2822

0.1µF

2pF

Figure 43. Transformer-Coupled Differential Clock (Up to 200 MHz)

Figure 42. Equivalent Clock Input Circuit

1nF

50Ω

1nF

0.1µF

CLOCK

INPUT

CLK+

ADC

CLK–

Clock Input Options

The

AD6657A

has a very flexible clock input structure. The

clock input can be a CMOS, LVDS, LVPECL, or sine wave signal.

Regardless of the type of signal being used, clock source jitter is

of the most concern (see th

e Jitter Considerations

section).

SCHOTTKY

DIODES:

HSMS2822

Figure 44. Balun-Coupled Differential Clock (Up to 625 MHz)

Rev. A | Page 21 of 36

AD6657A

Data Sheet

CLK+ can be driven directly from a CMOS gate. Although

If a low jitter clock source is not available, another option is to

ac couple a differential PECL signal to the sample clock input

pins, as shown

ck drivers offer excellent

jitter performance.

the CLK+ input circuit supply is

DD (1.8 V), this input is

designed to withstand input voltages of up to 3.6

aking the

selection of the drive logic voltage very flexible (see

Figure 48).

Ω

OPTIONAL

100

Ω

0.1µF

AD951x

CMOS DRIVER

CLOCK

INPUT

CLK+

ADC

CLK–

0.1µF

Ω

CLOCK

INPUT

CLK+

ADC

CLK–

AD951x

100

Ω

PECL DRIVER

0.1µF

CLOCK

INPUT

Ω

RESISTOR IS OPTIONAL.

240

Ω

240

Ω

50k

Ω

50k

Ω

Figure 48. Single-Ended 3.3 V CMOS Input Clock (Up to 200 MHz)

Figure 45. Differential PECL Sample Clock (Up to 625 MHz)

Input Clock Divider

The

AD6657A

ontains an input clock divider with the ability to

divide the input clock by integer values from 1 to 8.

A third option is to ac couple a differential LVDS signal to the

sample clock input pins, as shown in

The

ock

drivers offer excellent jitter performance.

The

AD6657A

clo

ck divider can be synchronized using the

external SYNC input. Bit 1 of Register 0x3A enables the clock

divider to be resynchronized on every SYNC signal. A valid

SYNC causes the clock divider to reset to its initial state. This

synchronization feature allows multiple parts to have their clock

dividers aligned to guarantee simultaneous input sampling.

0.1µF

CLOCK

INPUT

CLK+

ADC

CLK–

AD951x

LVDS DRIVER

100

Ω

0.1µF

CLOCK

INPUT

Clock Duty Cycle

50k

Ω

50k

Ω

Typical high speed ADCs use both clock edges to generate

a variety of internal timing signals and, as a result, may be

sensitive to clock duty cycle. Commonly, a

5% tolerance is

required on the clock duty cycle to maintain dynamic perfor-

mance characteristics.

Figure 46. Differential LVDS Sample Clock (Up to 625 MHz)

In some applications, it may be acceptable to drive the sample

clock inputs with a single-ended CMOS signal. In such applica-

tions, drive the CLK+ pin directly from a CMOS gate, and

bypass the CLK− pin to ground with a 0.1 μF capacitor in

parallel with a 39 kΩ resistor (s

ee Figure 47).

The

AD6657A

ontains a DCS that retimes the nonsampling

(falling) edge, providing an internal clock signal with a nominal

50% duty cycle. This allows the user to provide a wide range of

clock input duty cycles without affecting the performance of the

AD6657A

Noise and distortion performance are nearly flat for

a wide range of duty cycles with the DCS enabled.

OPTIONAL

100

Ω

0.1µF

Ω

AD951x

CMOS DRIVER

CLOCK

INPUT

CLK+

ADC

CLK–

Ω

Jitter in the rising edge of the input is of paramount concern and

is not easily reduced by the internal stabilization circuit. The duty

cycle control loop does not function for clock rates at less than

40 MHz nominally. The loop has a time constant associated with

it that must be considered in applications in which the clock

rate can change dynamically. A wait time of 1.5 ꢀs to 5 ꢀs is

required after a dynamic clock frequency increase or decrease

before the DCS loop is relocked to the input signal. During the

time period that the loop is not locked, the DCS loop is bypassed,

and internal device timing is dependent on the duty cycle of the

input clock signal.

0.1µF

39k

Ω

RESISTOR IS OPTIONAL.

Figure 47. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)

Rev. A | Page 22 of 36

Data Sheet

AD6657A

1.5

1.4

1.3

1.2

1.1

1.0

0.60

Jitter Considerations

0.55

High speed, high resolution ADCs are sensitive to the quality of

the clock input. The degradation in SNR from the low frequency

SNR (SNR

) at a given input frequency (f

) due to jitter (t

JRMS

can be calculated by

0.50

AVDD

0.45

0.40

)

0.9

0.8

0.7

0.6

0.5

TOTAL POWER

0.35

0.30

SNR

= −10log[(2π ×

JRMS

) +

(−SNR

]

/10)

0.25

0.20

In the equation, the rms aperture jitter represents the clock

input jitter specification. IF undersampling applications are

particularly sensitive to jitter, as shown in

Figure 49.

0.4

0.3

0.15

DRVDD

0.10

0.05

0.2

0.1

0.05ps

30 40 50 60 70 80 90

90 200

SAMPLING FREQUENCY (MSPS)

Figure 50. Power and Current vs. Sampling Frequency

0.20ps

By asserting PDWN (either through the SPI port or by asserting

the PDWN pin high), the

AD6657A

is placed in power-down

mode. In this state, the ADC typically dissipates 4.5 m

During power-down, the output drivers are placed in a high

impedance state. Asserting the PDWN pin low returns the

AD6657A

to its normal operating mode. Note that PDWN is

referenced to the digital output driver supply (DRVDD) and

should not exceed that supply voltage.

0.50ps

1.00ps

1.50ps

100

INPUT FREQUENCY (MHz)

Low power dissipation in power-down mode is achieved by

shutting down the reference, reference buffer, biasing networks,

and clock. Internal capacitors are discharged when entering

power-down mode and must be recharged when returning to

normal operation. As a result, wake-up time is related to the

time spent in power-down mode; shorter power-down cycles

result in proportionally shorter wake-up times.

Figure 49. SNR vs. Input Frequency and Jitter

In cases where aperture jitter may affect the dynamic range of

the

AD6657A

treat the clock input as an analog signal. Separate

power supplies for clock drivers should be separated from the

ADC output driver supplies to avoid modulating the clock signal

with digital noise. Low jitter, crystal controlled oscillators make

the best clock sources. If the clock is generated from another type

of source (by gating, dividing, or another method), it should be

retimed by the original clock at the last step. Refer to the

AN-501

Application Note

and

AN-756 Application Note

for more informa-

tion about jitter performance as it relates to ADCs (available at

.analog.com

)

When using the SPI port interface, the user can place the ADC

in power-down mode or standby mode. Standby mode allows

the user to keep the internal reference circuitry powered when

faster wake-up times are required. See th

e Memory Map Register

Descriptions

section for more details.

CHANNEL/CHIP SYNCHRONIZATION

POWER DISSIPATION AND STANDBY MODE

The

AD6657A

has a SYNC input that offers the user flexible

synchronization options for synchronizing the clock divider. The

clock divider sync feature is useful for guaranteeing synchronized

sample clocks across multiple ADCs.

The power dissipated by the

AD6657A

is proportional to its clock

rate (s

ee Figure 50)

. The digital power dissipation does not vary

significantly because it is determined primarily by the DRVDD

supply and the bias current of the LVDS drivers.

The SYNC input is internally synchronized to the sample clock;

however, to ensure that there is no timing uncertainty between

multiple parts, externally synchronize the SYNC input signal to

the input clock signal, meeting the setup and hold times shown

n Table 5. D

rive the SYNC input using a single-ended CMOS

type signal.

Reducing the capacitive load presented to the output drivers can

minimize digital power consumption. The data in

Figure 50

was

obtained using the same operating conditions as those used in

the

Typical Performance Characteristics

section, with a 5 pF

load on each output driver.

Rev. A | Page 23 of 36

AD6657A

Data Sheet

Minimize the length of the output data lines and minimize the

loads placed on them to reduce transients within th

AD6657A

because these transients can degrade converter dynamic per-

formance.

DIGITAL OUTPUTS

The

AD6657A

output drivers are configured to interface with

LVDS outputs using a DRVDD supply voltage of 1.8

output bits are DDR LVDS as shown in

Figure 2.

Applications

that require the ADC to drive large capacitive loads or large

fanouts may require external buffers or latches.

The lowest typical conversion rate of th

AD6657A

is 40 MSPS.

At clock rates below 40 MSPS, dynamic performance can degrade.

Data Clock Output (DCO)

As described in the

AN-877 Application Note

Interfacing to

High Speed ADCs via SPI

, the data format can be selected for

offset binary or twos complement when using the SPI control.

The

AD6657A

provides a data clock output (DCO) signal

intended for capturing the data in an external register. The

output data for Channel A and Channel C is valid when DCO

is high; the output data for Channel B and Channel D is valid

when DCO is low (see

Figure 2).

TIMING

The

AD6657A

provides latched data with a latency of

nine clock cycles. Data outputs are available one propagation

delay (t

) after the rising edge of the clock signal.

Table 11. Output Data Format

Input (V)

Condition (V)

< −V

REF

− 0.5 LSB

= −V

REF

Offset Binary Output Mode

Twos Complement Mode

100 0000 0000

000 0000 0000

011 1111 1111

VIN+ − VIN−

000 0000 0000

100 0000 0000

111 1111 1111

= 0

= +V

REF

− 1.0 LSB

> +V

REF

− 0.5 LSB

011 1111 1111

Rev. A | Page 24 of 36

Data Sheet

AD6657A

NOISE SHAPING REQUANTIZER

The

AD6657A

features a noise shaping requantizer (NSR) to allow

higher than an 11-bit SNR to be maintained in a subset of the

Nyquist band. The harmonic performance of the receiver is

unaffected by the NSR feature.

Figure 51

o Figure 53

show the typical spectrum that can be

expected from th

AD6657A

in the 22% BW mode for three

different tuning words.

185MSPS

140.3MHz @ –1dBFS

When enabled, the NSR contributes an additional 0.6 dB of

loss to the input signal, such that a 0 dBFS input is reduced to

−0.6 dBFS at the output pins.

NSR 22% BW MODE, TW = 13

SNR = 73.4dB (75.0dBFS)

SFDR = 91dBc

–20

–40

–60

The NSR feature can be independently controlled per channel

via the SPI or via the MODE pin.

THIRD HARMONIC

–80

–100

–120

Two different bandwidth modes are provided; the mode can be

selected from the SPI port. In each of the two modes, the center

frequency of the band can be tuned such that IFs can be placed

anywhere in the Nyquist band.

22% BW MODE (>40 MHz at 184.32 MSPS)

–140

9.25 18.50

27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50

FREQUENCY (MHz)

The first bandwidth mode offers excellent noise performance

over 22% of the ADC sample rate (44% of the Nyquist band)

and can be centered by setting the NSR mode bits in the NSR

control register (Address 0x3C) to 000. In this mode, the useful

frequency range can be set using the 6-bit tuning word in the

NSR tuning word register (Address 0x3E).

Figure 51. 22% BW Mode, Tuning Word = 13

–20

–40

–60

185MSPS

140.3MHz @ –1dBFS

NSR 22% BW MODE, TW = 28

SNR = 73.4dB (75.0dBFS)

SFDR = 91dBc

There are 57 possible tuning words (TW); each step is 0.5% of

the ADC sample rate. The following three equations describe

the left band edge (f

), the channel center (f

CENTER

), and the right

band edge (f

), respectively.

THIRD HARMONIC

–80

–100

–120

ADC

× .005 ×

CENTER

+ 0.11 ×

ADC

+ 0.22 ×

ADC

–140

9.25 18.50

27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50

FREQUENCY (MHz)

Figure 52. 22% BW Mode, Tuning Word = 28 (f

/4 Tuning)

185MSPS

140.3MHz @ –1dBFS

NSR 22% BW MODE, TW = 41

SNR = 73.4dB (75.0dBFS)

SFDR = 91dBc

–20

–40

–60

THIRD HARMONIC

–80

–100

–120

–140

9.25 18.50

27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50

FREQUENCY (MHz)

Figure 53. 22% BW Mode, Tuning Word = 41

Rev. A | Page 25 of 36

AD6657A

Data Sheet

–20

–40

–60

33% BW MODE (>60 MHz AT 184.32 MSPS)

185MSPS

140.3MHz @ –1dBFS

NSR 33% BW MODE, TW = 17

SNR = 70.9dB (72.5dBFS)

SFDR = 91dBc

The second bandwidth mode offers excellent noise performance

over 33% of the ADC sample rate (66% of the Nyquist band)

and can be centered by setting the NSR mode bits in the NSR

control register (Address 0x3C) to 001. In this mode, the useful

frequency range can be set using the 6-bit tuning word in the

NSR tuning word register (Address 0x3E).

THIRD HARMONIC

–80

–100

–120

There are 34 possible tuning words (TW); each step is 0.5% of

the ADC sample rate. The following three equations describe

the left band edge (f

), the channel center (f

CENTER

), and the right

band edge (f

), respectively.

–140

9.25 18.50

27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50

FREQUENCY (MHz)

ADC

× .005 ×

CENTER

+ 0.165 ×

ADC

Figure 56. 33% BW Mode, Tuning Word = 17

+ 0.33 ×

ADC

Figure 54

o Figure 56

show the typical spectrum that can be

expected from th

AD6657A

in the 33% BW mode for three

different tuning words.

185MSPS

140.3MHz @ –1dBFS

NSR 33% BW MODE, TW = 5

SNR = 70.9dB (72.5dBFS)

SFDR = 91dBc

–20

–40

–60

THIRD HARMONIC

–80

–100

–120

–140

9.25 18.50

27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50

FREQUENCY (MHz)

Figure 54. 33% BW Mode, Tuning Word = 5

–20

–40

–60

185MSPS

140.3MHz @ –1dBFS

NSR 33% BW MODE, TW = 17

SNR = 71.1dB (72.7dBFS)

SFDR = 91dBc

THIRD HARMONIC

–80

–100

–120

–140

9.25 18.50

27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50

FREQUENCY (MHz)

Figure 55. 33% BW Mode, Tuning Word = 17 (f

/4 Tuning)

Rev. A | Page 26 of 36

Data Sheet

AD6657A

–20

–40

–60

36% BW MODE (>65 MHz AT 184.32 MSPS)

185MSPS

140.3MHz @ –1dBFS

NSR 36% BW MODE, TW = 28

SNR = 70.4dB (72.0dBFS)

SFDR = 91dBc

The third bandwidth mode offers excellent noise performance

over 36% of the ADC sample rate (72% of the Nyquist band)

and can be centered by setting the NSR mode bits in the NSR

control register (Address 0x3C) to 010. In this mode, the useful

frequency range can be set using the 6-bit tuning word in the

NSR tuning register (Address 0x3E).

THIRD HARMONIC

–80

–100

–120

There are 28 possible tuning words (TW); each step is 0.5% of

the ADC sample rate. The following three equations describe

the left band edge (f

), the channel center (f

CENTER

), and the right

band edge (f

), respectively.

–140

9.25 18.50

27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50

FREQUENCY (MHz)

ADC

× .005 ×

CENTER

+ 0.18 ×

ADC

Figure 59. 36% BW Mode, Tuning Word = 28

+ 0.36 ×

ADC

MODE PIN

Figure 57

o Figure 59

show the typical spectrum that can be

expected from th

AD6657A

in the 36% BW mode for three

different tuning words.

The MODE pin input allows convenient control of the NSR

feature. A logic low enables NSR mode and a logic high sets the

receiver to a straight 11-bit mode with NSR disabled. By default,

the MODE pin is pulled high internally to disable the NSR.

185MSPS

140.3MHz @ –1dBFS

NSR 36% BW MODE, TW = 0

SNR = 70.4dB (72.0dBFS)

SFDR = 91dBc

–20

–40

–60

Each channel can be individually configured to ignore the

MODE pin state by writing to Bit 4 of the NSR control register

at Address 0x3C. Use of the NSR control register in conjunction

with the MODE pin allows for very flexible control of the NSR

feature on a per channel basis.

THIRD HARMONIC

–80

–100

–120

–140

9.25 18.50

27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50

FREQUENCY (MHz)

Figure 57. 36% BW Mode, Tuning Word = 0

–20

–40

–60

185MSPS

140.3MHz @ –1dBFS

NSR 36% BW MODE, TW = 14

SNR = 70.4dB (72.0dBFS)

SFDR = 91dBc

THIRD HARMONIC

–80

–100

–120

–140

9.25 18.50

27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50

FREQUENCY (MHz)

Figure 58. 36% BW Mode, Tuning Word = 14 (f

/4 Tuning)

Rev. A | Page 27 of 36

AD6657A

Data Sheet

BUILT-IN SELF TEST (BIST) AND OUTPUT TEST

The

AD6657A

includes built-in test features designed to verify

the integrity of each channel and to facilitate board-level debug-

ging. A built-in self test (BIST) feature is included that verifies

the integrity of the digital datapath of the

AD6657A

arious

output test options are also provided to place predictable values

on the outputs of the

AD6657A

The outputs are not disconnected during this test, so the PN

sequence can be observed as it runs. The PN sequence can be

continued from its last value or reset from the beginning, based

on the value programmed in Register 0x0E, Bit 2. The BIST

signature result varies based on the channel configuration.

OUTPUT TEST MODES

BIST

The output test options are shown in

Table 13.

When an output

test mode is enabled, the analog section of the receiver is dis-

connected from the digital back-end blocks, and the test pattern

is run through the output formatting block. Some of the test

patterns are subject to output formatting. The seed value for the

PN sequence tests can be forced if the PN reset bits are used to

hold the generator in reset mode by setting Bit 4 or Bit 5 of

analog signal (if present, the analog signal is ignored), but they

require an encode clock. For more information, see the

AN-877

Application Note

Interfacing to High Speed ADCs via SPI

The BIST is a thorough test of the digital portion of the selected

AD6657A

signal path. When enabled, the test runs from an

internal pseudorandom noise (PN) source through the digital

datapath starting at the ADC block output. The BIST sequence

runs for 512 cycles and stops. The BIST signature value for the

selected channel is written to Register 0x24 and Register 0x25.

If more than one channel is BIST enabled, the channel that

is first according to alphabetical order is written to the BIST

signature registers. For example, if Channel B and Channel C

are BIST enabled, the results from Channel B are written to the

BIST signature registers.

Rev. A | Page 28 of 36

Data Sheet

AD6657A

SERIAL PORT INTERFACE (SPI)

The

AD6657A

serial port interface (SPI) allows the user to con-

figure the receiver for specific functions or operations through a

structured internal register space. The SPI provides added flexibility

and customization, depending on the application. Addresses are

accessed via the serial port and can be written to or read from

via the port. Memory is organized into bytes that can be further

divided into fields, which are documented in the

Memory Map

section. For detailed operational information, see the

AN-877

Application Note

Interfacing to High Speed ADCs via SPI

During an instruction phase, a 16-bit instruction is transmitted.

The first bit of the first byte in a serial data transfer frame indicates

whether a read command or a write command is issued. Data

follows the instruction phase, and its length is determined by

the W0 and W1 bits. All data is composed of 8-bit words.

The instruction phase determines whether the serial frame is a

read or write operation, allowing the serial port to be used both

to program the chip and to read the contents of the on-chip

memory. If the instruction is a read operation, the serial data

input/output (SDIO) pin changes direction from an input to an

output at the appropriate point in the serial frame.

CONFIGURATION USING THE SPI

Three pins define the SPI of th

AD6657A

: S

CLK, SDIO, and

CSB (s

ee Table 12)

. SCLK (a serial clock) is used to synchronize

the read and write data presented from and to the

AD6657A

SDIO (serial data input/output) is a bidirectional pin that allows

data to be sent to and read from the internal memory map

registers. CSB (chip select bar) is an active low control that

enables or disables the read and write cycles.

Data can be sent in MSB first mode or in LSB first mode. MSB

first is the default mode on power-up and can be changed via

the SPI port configuration register. For more information about

this and other features, see the

AN-877 Application Note

Inter-

facing to High Speed ADCs via SPI

HARDWARE INTERFACE

Table 12. Serial Port Interface Pins

The pins described in

Table 12

constitute the physical interface

between the user

’

s programming device and the serial port of

the

AD6657A

The SCLK pin and the CSB pin function as

inputs when using the SPI interface. The SDIO pin is

bidirectional, functioning as an input during the write phase

and as an output during readback.

Function

SCLK

Serial clock. Serial shift clock input. SCLK is used to

synchronize serial interface reads and writes.

SDIO

CSB

Serial data input/output. Bidirectional pin that serves

as an input or an output, depending on the instruction

being sent and the relative position in the timing frame.

Chip select bar (active low). This control gates the read

and write cycles.

The SPI interface is flexible enough to be controlled by either

FPGAs or microcontrollers. One method for SPI configuration

is described in detail in

AN-812 Application Note

Micro-

controller-Based Serial Port Interface (SPI) Boot Circuit

The falling edge of the CSB pin, in conjunction with the rising

edge of the SCLK pin, determines the start of the framing. An

example of the serial timing can be found in

Figure 60

(for

symbol definitions, see

Table 5).

The SPI port should not be active during periods when the full

dynamic performance of the

AD6657A

is required. Because the

SCLK signal, the CSB signal, and the SDIO signal are typically

asynchronous to the ADC clock, noise from these signals can

degrade

AD6657A

performance. If the on-board SPI bus is used

for other devices, it may be necessary to provide buffers between

this bus and the

AD6657A

to prevent these signals from transi-

tioning at the receiver inputs during critical sampling periods.

CSB can be held low indefinitely, which permanently enables

the device; this is called streaming. CSB can stall high between

bytes to allow for additional external timing. When CSB is tied

high, SPI functions are placed in high impedance mode.

HIGH

CLK

LOW

CSB

SCLK

SDIO

DON’T

CARE

DON’T CARE

DON’T

CARE

R/W

A12

A11

A10

DON’T CARE

Figure 60. Serial Port Interface Timing Diagram

Rev. A | Page 29 of 36

AD6657A

Data Sheet

MEMORY MAP

Logic Levels

An explanation of logic level terminology follows:

READING THE MEMORY MAP REGISTER TABLE

Each row in the memory map register table has eight bit loca-

tions (see

Table 13)

. The memory map is roughly divided into

four sections: the chip configuration registers (Address 0x00

and Address 0x01); the channel index and transfer registers

(Address 0x05 and Address 0xFF); the ADC function registers,

including setup, control, and test (Address 0x08 to Address 0x25);

and the digital feature control registers (Address 0x3A to

Address 0x3E).

•

“Bit is set” is synonymous with “bit is set to Logic 1” or

“writing Logic 1 for the bit

”

•

“Clear a bit” is synonymous with “bit is set to Logic 0” or

“writing Logic 0 for the bit

”

Transfer Register Map

Address 0x08 to Address 0x3E are shadowed. Writes to these

addresses do not affect part operation until a transfer command

is issued by writing 0x01 to Address 0xF

hereby setting the

transfer bit. This allows these registers to be updated internally

and simultaneously when the transfer bit is set. The transfer bit

is autoclearing.

The memory map register table (s

ee Table 13)

provides the

default hexadecimal value for each hexadecimal address shown.

The column with the heading (MSB) Bit 7 is the start of the

default hexadecimal value given. The

AN-877 Application Note

Interfacing to High Speed ADCs via SPI

, documents the functions

controlled by Register 0x00 to Register 0xF

he remaining

registers, Register 0x3A to Register 0x3E, are documented in

the

Memory Map Register Descriptions

section.

Channel Specific Registers

Some channel setup functions, such as the NSR control func-

tion, can be programmed differently for each channel. In these

cases, channel address locations are internally duplicated for

each channel. These registers and bits are designated in

Table 13

as local. Local registers and bits can be accessed by setting the

appropriate channel bits in Register 0x05.

Open Locations

All address and bit locations that are not included

in Table 13

are

not currently supported for this device. Unused bits of a valid

address location should be written with 0s. Writing to these

locations is required only when part of an address location is

open (for example, Address 0x18). If the entire address location

is open (for example, Address 0x13), this address location should

not be written.

If multiple channel bits are set, the subsequent write affects the

registers of all selected channels. In a read cycle, select a single

channel only to read one of the registers. If multiple channels are

selected during a SPI read cycle, the device returns the value for

Channel A only. Registers and bits designated as global i

n Table 13

affect the entire device or the channel features for which there are

no independent per channel settings. The settings in Register 0x05

do not affect the global registers and bits.

Default Values

After th

AD6657A

is reset, critical registers are loaded with

default values. The default values for the registers are given in

the memory map register table (s

ee Table 13).

Rev. A | Page 30 of 36

Data Sheet

AD6657A

MEMORY MAP REGISTER TABLE

All address and bit locations that are not included in

Table 13

are not currently supported for this device.

Table 13. Memory Map Registers

Default

Value

(Hex)

Addr. Register

(Hex) Name

(MSB)

Bit 7

(LSB)

Bit 0

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Comments

Chip Configuration Registers

0x00

SPI port

configuration

(global)

Open

LSB first

Soft reset

LSB first

Open

0x18

Nibbles are

mirrored so

that LSB first

or MSB first

mode is set

correctly,

regardless of

shift mode.

To control

this register,

all channel

index bits in

must be set.

0x01

Chip ID

(global)

8-bit chip ID, Bits[7:0]

AD6657A

= 0x7B (default)

0x7B

Read only.

Channel Index and Transfer Registers

0x05

Channel

index

Enable

output

port for

Enable

output

port for

Open

Channel D

Channel C

Channel B

Channel A

0xCF

Bits are set to

determine

which

enable

Channel C

Channel A

and and

Channel D

Channel B

channel on

the chip

receives the

next write

command;

applies to

local

registers.

0xFF

Transfer

Open

0x00

Synchro-

nously

transfers

data from

the master

shift register

to the slave.

transfer

1 = on

0 = off

(default)

ADC Function Registers

External

power-

down pin

function

(global)

0 = full

power-

down

Internal power-down

mode (local)

00 = normal operation

(default)

Determines

generic

modes of

chip opera-

tion.

0x08

Power modes

Open

01 = full power-down

10 = standby

1 =

standby

0x0B

0x0C

Clock divide

(global)

Open

Clock divide phase

Clock divide ratio

0x00

0x01

000 = 0 input clock cycles delayed

001 = 1 input clock cycle delayed

010 = 2 input clock cycles delayed

000 = divide by 1

001 = divide by 2

010 = divide by 3

011 = divide by 4

100 = divide by 5

101 = divide by 6

110 = divide by 7

111 = divide by 8

Shuffle mode

(local)

Open

Shuffle mode enable

00 = shuffle disabled

Enables or

disables

shuffle

01 = shuffle enabled

mode.

Rev. A | Page 31 of 36

AD6657A

Data Sheet

Default

Addr. Register

(Hex) Name

(MSB)

Bit 7

(LSB)

Bit 0

Value

(Hex)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Comments

Output test mode

000 = off (normal operation)

0x00

When set,

the test data

is placed on

the output

pins in place

of normal

data.

0x0D

Test mode

(local)

Open

Reset

long PN

generator generator

0 = on

1 = off

(default)

Reset

short PN

Open

001 = midscale short

010 = positive FS

011 = negative FS

0 = on

1 = off

(default)

100 = alternating checkerboard

101 = PN sequence long

110 = PN sequence short

111 = 1/0 word toggle

0x0E

0x10

BIST enable

(local)

Open

BIST reset

0 = on

1 = off

Open

BIST

0x00

When Bit 0

is set, the

built-in self

test function

is initiated.

enable

1 = on

0 = off

(default)

Offset adjust

(local)

Offset adjustment in LSBs from +127 to −128

(twos complement format)

011111 = +31 LSB

011110 = +30 LSB

011101 = +29 LSB

…

Device offset

trim.

000010 = +2 LSB

000001 = +1 LSB

000000 = 0 LSB

…

111111 = −1 LSB

111110 = −2 LSB

111101 = −3 LSB

…

100001 = −31 LSB

100000 = −32 LSB

Output mode

Open

(local)

Open

Output

enable

bar

(local)

1 = off

0 = on

Open

Output

invert

(local)

1 = on

0 = off

Output format (local)

00 = offset binary

01 = twos

0x00

0x01

Configures

the outputs

and the

format of

the data.

0x14

0x15

complement

Output

adjust

(local)

Open

Output port LVDS drive current

0000 = 3.72 mA

Output

current

adjustments.

0001 = 3.5 mA (default)

0010 = 3.3 mA

0011 = 2.96 mA

0100 = 2.82 mA

0101 = 2.57 mA

0110 = 2.27 mA

0111 = 2.0 mA

1000 = 2.0 mA

0x16

0x17

Clock phase

control

(local)

Invert

DCO clock

0 = off

1 = on

Open

0x00

When Bit 7

is set, clock

polarity is

reversed.

DCO output

delay

(local)

DCO

Output port DCO clock delay

Enable DCO

delay and set

the delay

time.

delay

enable

0 = off

1 = on

00000 = 100 ps additional delay on the DCO pin

00001 = 200 ps additional delay on the DCO pin

00010 = 300 ps additional delay on the DCO pin

…

11101 = 3.0 ns additional delay on the DCO pin

11110 = 3.1 ns additional delay on the DCO pin

11111 = 3.2 ns additional delay on the DCO pin

0x18

_REF
select

Open

Internal V

REF

full-scale adjustment

Main reference full-scale V

REF

adjustment

01111: internal 2.087 V p-p

…

0x00

Select

adjustments

for V

REF

(global)

00001: internal 1.772 V p-p

00000: internal 1.75 V p-p

…

11111: internal 1.727 V p-p

…

10000: internal 1.383 V p-p

Rev. A | Page 32 of 36

Data Sheet

AD6657A

Default

Value

(Hex)

Addr. Register

(Hex) Name

(MSB)

Bit 7

(LSB)

Bit 0

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Comments

0x24

BIST

BIST Signature[7:0]

0x00

Read only.

signature LSB

(local)

0x25

BIST signa-

ture MSB

(local)

BIST Signature[15:8]

0x00

Read only.

Digital Feature Control Registers

Master

sync

enable

0 = off

1 = on

0x00

Control

0x3A

0x3C

Sync control

(global)

Open

Clock divider

sync mode

0 = conti-

Clock

divider

sync

enable

0 = off

1 = on

synchronize

the clock

divider.

nuous

1 = next sync

mode, next

rising edge of

sync resets

clock divider

NSR control

(local)

Open

MODE

disable

0 =

MODE

pin used

1 =

MODE

pin dis-

abled

NSR mode

NSR

Noise

000 = 22% BW mode

001 = 33% BW mode

010 = 36% BW mode

enable

0 = off

1 = on

(used only

Bit 4 = 1;

otherwise

ignored)

shaping

requantizer

(NSR)

controls.

0x3E

NSR tuning

word

(local)

Open

NSR tuning word

See th

e Noise Shaping Requantizer

section.

Equations for the tuning word are dependent on the NSR mode.

0x1C

NSR

frequency

tuning word.

NSR Control (Register 0x3C)

MEMORY MAP REGISTER DESCRIPTIONS

Bits[7:5]—Reserved

For additional information about functions controlled

in Register 0x00 to Register 0xF

ee the

AN-877 Application

Note

Interfacing to High Speed ADCs via SPI

Bit 4—MODE Pin Disable

Bit 4 specifies whether the selected channels are to be controlled

by the MODE pin. Local registers act on the channels that are

selected by the channel index register (Address 0x05).

Sync Control (Register 0x3A)

Bits[7:3]—Reserved

Bit 2—Clock Divider Sync Mode

Bits[3:1]—NSR Mode

Bit 2 selects the mode of the clock divider sync function. When

Bit 2 is low, continuous sync mode is enabled. When Bit 2 is

high, the clock divider is reset on the next rising edge of the

sync signal. Subsequent rising edges of the sync signal are

ignored.

Bits[3:1] determine the bandwidth (BW) mode of the NSR.

When Bits[3:1] are set to 000, the NSR is configured for a 22%

BW mode that provides enhanced SNR performance over 22%

of the sample rate. When Bits[3:1] are set to 001, the NSR is

configured for a 33% BW mode that provides enhanced SNR

performance over 33% of the sample rate. When Bits[3:1] are

set to 010, the NSR is configured for a 36% BW mode that pro-

vides enhanced SNR performance over 36% of the sample rate.

Bit 1—Clock Divider Sync Enable

Bit 1 gates the sync pulse to the clock divider. The sync signal is

enabled when Bit 1 is high and Bit 0 is high. This is continuous

sync mode.

Bit 0—NSR Enable

The NSR is enabled when Bit 0 is high and disabled when Bit 0

is low. Bit 0 is ignored unless the MODE pin disable bit (Bit 4)

is set.

Bit 0—Master Sync Enable

Bit 0 must be high to enable any of the sync functions. If

the sync capability is not used, this bit should remain low

to conserve power.

Rev. A | Page 33 of 36

AD6657A

Data Sheet

NSR Tuning Word (Register 0x3E)

Bits[7:6]—Reserved

there are 28 possible tuning words. For either mode, each step

represents 0.5% of the ADC sample rate. For the equations used

to calculate the tuning word based on the BW mode of

operation, see the

Noise Shaping Requantizer

section.

Bits[5:0]—NSR

ning

The NSR tuning word sets the band edges of the NSR band. In

22% BW mode, there are 57 possible tuning words; in 33% BW

mode, there are 34 possible tuning words; in 36% BW mode,

Rev. A | Page 34 of 36

Data Sheet

AD6657A

APPLICATIONS INFORMATION

VCMx Pins

DESIGN GUIDELINES

The VCMx pins are provided to set the common-mode level

of the analog inputs. Decouple the VCMx pins to ground with a

0.1 μF capacitor, as shown in

Figure 37.

Before starting the design and layout of the

AD6657A

in a

system, it is recommended that the designer become familiar

with these guidelines, which discuss the special circuit

connections and layout requirements needed for certain pins.

SPI Port

Power and Ground Recommendations

The SPI port should not be active during periods when the full

dynamic performance of the

AD6657A

is required. Because the

SCLK signal, the CSB signal, and the SDIO signal are typically

asynchronous to the ADC clock, noise from these signals can

degrade

AD6657A

performance. If the on-board SPI bus is used

for other devices, it may be necessary to provide buffers between

this bus and the

AD6657A

to prevent these signals from transi-

tioning at the receiver inputs during critical sampling periods.

When connecting power to th

AD6657A

it is recommended

that two separate 1.8 V supplies be used. Use one supply for

analog (

DD); use a separate supply for the digital outputs

(DRVDD). The AVDD and DRVDD supplies should be isolated

with separate decoupling capacitors. Several different decoupling

capacitors can be used to cover both high and low frequencies.

Locate these capacitors close to the point of entry at the PCB

level and close to the pins of the part, with minimal trace length.

A single PCB ground plane is sufficient when using the

AD6657A

With proper decoupling and smart partitioning of the PCB

analog, digital, and clock sections, optimum performance is

easily achieved.

Rev. A | Page 35 of 36

AD6657A

Data Sheet

PACKAGING AND ORDERING INFORMATION

OUTLINE DIMENSIONS

10.10

A1 BALL

CORNER

10.00 SQ

9.90

A1 BALL

CORNER

12 11 10

8.80

BSC SQ

0.80

0.60

REF

TOP VIEW

DETAIL A

BOTTOM VIEW

1.40 MAX

0.65 MIN

DETAIL A

0.25 MIN

0.50

0.45

0.40

COPLANARITY

0.20

SEATING

PLANE

BALL DIAMETER

COMPLIANT WITH JEDEC STANDARDS MO-275-EEAB-1

WITH EXCEPTION TO PACKAGE HEIGHT.

Figure 61. 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

(BC-144-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

BC-144-1

AD6657ABBCZ

AD6657ABBCZRL

AD6657AEBZ

−40°C to +85°C

144-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

Evaluation Board

^{1
Z = RoHS Compliant Part.}

registered trademarks are the property of their respective owners.

D09684-0-2/14(A)

www.analog.com/AD6657A

Rev. A | Page 36 of 36

Analog-Devices-AD6657ABBCZRL

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