Analog-Devices-ADPA1105ACGZN
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46 dBm (40 W), 0.9 GHz to 1.6 GHz,
GaN Power Amplifier
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Output power with P
IN
= 19 dBm: 46 dBm typical
Small signal gain: 34.5 dB typical at 0.9 GHz to 1.4 GHz
Power gain with P
IN
= 19 dBm: 27 dB typical
Bandwidth: 0.9 GHz to 1.6 GHz
PAE with P
IN
= 19 dBm: 60% typical at 0.9 GHz to 1.4 GHz
Supply voltage: V
DD
= 50 V at 400 mA on 10% duty cycle
ADPA1105
1
2
3
4
5
6
7
8
GND
NC
NC
24 GND
23 NC
NC
22
21 RFOUT
20 RFOUT
19 GND
RFIN
RFIN
GND
NC
GND
APPLICATIONS
NC
18
17 GND
Weather radar
Marine radar
Military radar
PACKAGE
BASE
GND
Figure 1.
GENERAL DESCRIPTION
The ADPA1105 is a gallium nitride (GaN), broadband power
amplifier that delivers 46 dBm (40 W) with 60% typical power
added efficiency (PAE) across a bandwidth of 0.9 GHz to
1.4 GHz. The ADPA1105 provides
0.5 dB gain flatness across
a bandwidth of 0.9 GHz to 1.4 GHz.
The ADPA1105 is ideal for pulsed applications such as wireless
infrastructure, radar, public mobile radio, and general-purpose
amplifications.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice.
No license is granted by implication or otherwise under any patent or patent rights of Analog
Devices. Trademarks and registere
d
t
rademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
©2020 Analog Devices, Inc. All rights reserved.
Data Sheet
TABLE OF CONTENTS
REVISION HISTORY
10/2020—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
Data Sheet
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
T
A
= 25°C, supply voltage (V
DD
) = 50 V, I
DQ
= 400 mA, pulse width = 100 μs, 10% duty cycle, and frequency range = 0.9 GHz to 1.4 GHz, unless
otherwise noted.
Table 1.
Parameter
FREQUENCY RANGE
GAIN
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
0.9
1.4
GHz
Small Signal Gain
Gain Flatness
RETURN LOSS
Input
32
34.5
0.5
dB
dB
16
9
dB
dB
Output
POWER
Output Power (P
OUT
)
Input Power (P
IN
) = 19 dBm
Power Gain
P
IN
= 19 dBm
44
25
46
27
dBm
dB
PAE
P
IN
= 19 dBm
60
%
TARGET QUIESCENT CURRENT
I
DQ
400
mA
Adjust the gate control voltage (V
GG1
, V
GG2
) to be between −4 V
and 0 V to achieve an I
DQ
= 400 mA typical value
T
A
= 25°C, V
DD
= 50 V, I
DQ
= 400 mA, pulse width = 100 μs, 10% duty cycle, and frequency range = 1.4 GHz to 1.6 GHz, unless otherwise noted.
Table 2.
Parameter
FREQUENCY RANGE
GAIN
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
1.4
1.6
GHz
Small Signal Gain
Gain Flatness
RETURN LOSS
Input
30.5
32.5
0.9
dB
dB
11
14
dB
dB
Output
POWER
P
OUT
P
IN
= 19 dBm
Power Gain
P
IN
= 19 dBm
PAE
44
25
46
27
dBm
dB
P
IN
= 19 dBm
TARGET QUIESCENT CURRENT
57
%
I
DQ
400
mA
Adjust the gate control voltage (V
GG1
, V
GG2
) to be between
−4 V and 0 V to achieve an I
DQ
= 400 mA typical value
Rev. 0 | Page 3 of 16
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 3.
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
the PCB thermal design is required.
Parameter
Rating
Drain Bias Voltage (V
DD1
, V
DD2
Gate Bias Voltage (V
GG1
, V
GG2
Radio Frequency Input Power (RFIN)
Maximum Drain Bias
)
55 V dc
−5 V to 0 V dc
30 dBm
)
θ
JC
is the junction to case thermal resistance (°C/W) of the device.
Table 4. Thermal Resistance
Package Type
1
Pulse Width
Duty Cycle
500 μs
20%
θ
JC
Unit
Drain Bias Pulse Width = 100 μs at 10% Duty Cycle
CG-32-2
Drain Bias Pulse Width = 100 μs
2
Drain Bias Pulse Width = 200 μs
3
Maximum Pulsed Power Dissipation (P
DISS
),
Base Temperature (T
BASE
) = 85°C, Derate
473 mW/°C Above 85°C
Nominal Pulsed Peak Channel Temperature,
P
IN
= 19 dBm, P
DISS
= 33.6 W at 0.9 GHz
54.5 W
155.9°C
2.11
2.82
°C/W
°C/W
1
The θ
JC
value was determined by measuring θ
JC
under the following
conditions: the heat transfer is solely because of the thermal conduction
from the channel through the ground pad to the PCB, and the ground pad is
held constant at the operating temperature of 85°C.
2
At 10% duty cycle.
Drain Bias Pulse Width = 200 μs at 20% Duty Cycle
Maximum Pulsed Power Dissipation (P
DISS
)
40.8 W
3
At 20% duty cycle.
(Base Temperature (T
BASE
) = 85°C, Derate
355 mW/°C Above 85°C)
ELECTROSTATIC DISCHARGE (ESD) RATINGS
Nominal Pulsed Peak Channel Temperature
P
IN
= 19 dBm, P
DISS
= 33.6 W at 0.9 GHz
1
Maximum Channel Temperature
Maximum Peak Reflow Temperature
Storage Temperature Range
179.7°C
The following ESD information is provided for handling of
ESD-sensitive devices in an ESD protected area only.
200°C
260°C
−60°C to
+125°C
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
ESD Ratings for ADPA1105
Table 5. ADPA1105, 32-Lead LFCSP_CAV
Operating Temperature Range
−40°C to +85°C
ESD Model
Withstand Threshold (V)
Class
1
Worst case frequency for P
DISS
.
HBM
250
1A
Stresses at or above those listed under Absolute Maximum Ratings
may cause permanent damage to the product. This is a stress
rating only; functional operation of the product at these or any
other conditions above those indicated in the operational section
of this specification is not implied. Operation beyond the
maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. 0 | Page 4 of 16
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
GND
NC
NC
24 GND
23 NC
NC
22
21 RFOUT
20 RFOUT
19 GND
ADPA1105
TOP VIEW
(Not to Scale)
RFIN
RFIN
GND
NC
GND
NC
18
17 GND
NOTES
1. THE NC PINS ARE NOT CONNECTED INTERNALL
Y
.
HOWEVER, ALL DATA SHOWN IS MEASURED
WITH THE NC PINS CONNECTED TO RF AND DC
GROUND EXTERNALL
Y
.
2. EXPOSED PAD. THE EXPOSED PAD MUST BE
CONNECTED TO RF AND DC GROUND.
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic Description
1, 6, 8, 9, 16, 17, 19,
24, 25, 32
GND
2, 3, 7, 12, 13, 18, 22,
NC
23, 26, 27, 29, 30
The NC pins are not connected internally. However, all data shown is measured with the NC pins
connected to RF and dc ground externally.
4, 5
10
RFIN
V
GG1
RF Input. The RFIN pins are ac-coupled and are matched to 50 Ω. See
Figure 3
for the interface schematic.
11
V
GG2
14
VDET
Detector Diode to Measure RF Output Power. Output power detection via VDET requires the application
of a dc bias voltage through an external series resistor. Used in combination with the VREF pin, the
difference in voltage (VREF − VDET) is a temperature compensated dc voltage that is proportional to
the RF output power.
15
VREF
Reference Diode for Temperature Compensation of VDET RF Output Power Measurements. VREF
requires the application of a dc bias voltage through an external series resistor.
20, 21
28
31
RFOUT
V
DD2
V
DD1
RF Output. The RFOUT pins are ac-coupled and are matched to 50 Ω. Se
e Figure 4 fo
r the interface schematic.
Exposed Pad. The exposed pad must be connected to RF and dc ground.
EPAD
INTERFACE SCHEMATICS
V
DD1
RFIN
VREF
V
GG1
Figure 5. VREF Interface
Figure 3. RFIN, V
GG1
, and V
DD1
Interface
V
DD2
RFOUT
GND
V
GG2
VDET
Figure 6. GND Interface
Figure 4. RFOUT, V
GG2
, V
DD2
, and VDET Interface
Rev. 0 | Page 5 of 16
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
40
35
30
38
36
34
32
30
28
26
24
25
SMALL SIGNAL GAIN
20
15
INPUT RETURN LOSS
OUTPUT RETURN LOSS
10
5
0
–5
–10
–15
–20
+85°C
+25°C
–40°C
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 7. Small Signal Gain and Return Loss vs. Frequency
Figure 10. Small Signal Gain vs. Frequency at Various Temperatures
0
0
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
-2
-4
–2
-6
–4
–6
-8
-10
-12
-14
–16
–18
–20
–8
–10
–12
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 8. Input Return Loss vs. Frequency at Various Temperatures
Figure 11. Output Return Loss vs. Frequency at Various Temperatures
38
38
36
34
32
30
28
50V
45V
40V
36
34
32
30
28
26
24
500mA
26
400mA
300mA
24
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 9. Small Signal Gain vs. Frequency at Various Supply Voltages,
I
DQ
= 400 mA
Figure 12. Small Signal Gain vs. Frequency at Various I
DQ
, V
DD1
and V
DD2
= 50 V
Rev. 0 | Page 6 of 16
Data Sheet
48
35
30
25
20
15
10
5
47
46
45
44
43
42
41
40
39
21dBm
20dBm
19dBm
18dBm
17dBm
16dBm
15dBm
21dBm
20dBm
19dBm
18dBm
17dBm
16dBm
15dBm
0
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 13. Output Power (P
OUT
) vs. Frequency at Various P
IN
Levels
Figure 16. Gain vs. Frequency at Various P
IN
Levels
70
60
50
40
30
47
46
45
44
43
42
41
40
21dBm
20
20dBm
19dBm
18dBm
10
+85°C
+25°C
–40°C
17dBm
16dBm
15dBm
0
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 14. PAE vs. Frequency at Various P
IN
Levels
Figure 17. P
OUT
vs. Frequency at Various Temperatures, P
IN
= 19 dBm
47
70
60
50
40
30
20
46
45
44
43
42
41
40
39
38
10
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
0
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 15. P
OUT
vs. Frequency at Various Temperatures, P
IN
= 16 dBm
Figure 18. PAE vs. Frequency at Various Temperatures, P
IN
= 16 dBm
Rev. 0 | Page 7 of 16
Data Sheet
70
60
50
40
30
20
10
32
30
28
26
24
22
20
18
16
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
0
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 19. PAE vs. Frequency at Various Temperatures, P
IN
= 19 dBm
Figure 22. Gain vs. Frequency at Various Temperatures, P
IN
= 19 dBm
32
30
47
46
45
44
43
42
28
26
24
22
20
41
+85°C
+25°C
–40°C
50V
45V
40V
18
16
0.9
40
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.0
1.1
1.2
1.3
1.4
1.5
1.6
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 20. Gain vs. Frequency at Various Temperatures, P
IN
= 16 dBm
Figure 23. P
OUT
vs. Frequency at Various Supply Voltages, P
IN
= 19 dBm,
I
DQ
= 400 mA
47
46
45
44
43
42
70
60
50
40
30
20
41
10
50V
45V
40V
50V
45V
40V
40
0.9
0
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.0
1.1
1.2
1.3
1.4
1.5
1.6
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 24. PAE vs. Frequency at Various Supply Voltages, P
IN
= 16 dBm,
I
DQ
= 400 mA
Figure 21. P
OUT
vs. Frequency at Various Supply Voltages, P
IN
= 16 dBm,
I
DQ
= 400 mA
Rev. 0 | Page 8 of 16
Data Sheet
70
60
50
40
30
20
10
32
30
28
26
24
22
20
18
16
50V
45V
40V
50V
45V
40V
0
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 25. PAE vs. Frequency at Various Supply Voltages, P
IN
= 19 dBm,
I
DQ
= 400 mA
Figure 28. Gain vs. Frequency at Various Supply Voltages, P
IN
= 19 dBm,
I
DQ
= 400 mA
32
30
47
46
45
44
43
42
28
26
24
22
20
41
50V
45V
40V
500mA
400mA
300mA
18
16
0.9
40
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.0
1.1
1.2
1.3
1.4
1.5
1.6
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 26. Gain vs. Frequency at Various Supply Voltages, P
IN
= 16 dBm,
I
DQ
= 400 mA
Figure 29. P
OUT
vs. Frequency at Various I
DQ
Supply Currents, P
IN
= 19 dBm,
V
DD
= 50 V
47
46
45
44
43
42
70
60
50
40
30
20
41
10
500mA
400mA
300mA
500mA
400mA
300mA
40
0.9
0
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.0
1.1
1.2
1.3
1.4
1.5
1.6
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 30. PAE vs. Frequency at Various I
DQ
Supply Currents, P
IN
= 16 dBm,
V
DD
= 50 V
Figure 27. P
OUT
vs. Frequency at Various I
DQ
Supply Currents, P
IN
= 16 dBm,
V
DD
= 50 V
Rev. 0 | Page 9 of 16
Data Sheet
70
60
50
40
30
20
10
32
30
28
26
24
22
20
18
16
500mA
400mA
300mA
500mA
400mA
300mA
0
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.6
1.6
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 31. PAE vs. Frequency at Various I
DQ
Supply Currents, P
IN
= 19 dBm,
V
DD
= 50 V
Figure 34. Gain vs. Frequency at Various I
DQ
Currents,
P
IN
= 19 dBm
32
30
47
46
45
28
26
24
22
20
44
43
42
41
PW = 500µs, DUTY CYCLE = 20%
PW = 200µs, DUTY CYCLE = 20%
PW = 100µs, DUTY CYCLE = 10%
PW = 50µs, DUTY CYCLE = 5%
PW = 20µs, DUTY CYCLE = 2%
500mA
400mA
300mA
18
16
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
0.9
1.0
1.1
1.2
1.3
1.4
1.5
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 32. Gain vs. Frequency at Various I
DQ
Supply Currents, P
IN
= 16 dBm,
V
DD
= 50 V
Figure 35. P
OUT
vs. Frequency at Various Pulse Widths
and Duty Cycles, P
IN
= 19 dBm
47
46
70
60
50
40
30
20
10
45
44
43
42
41
PW = 500µs, DUTY CYCLE = 20%
PW = 500µs, DUTY CYCLE = 20%
PW = 200µs, DUTY CYCLE = 20%
PW = 100µs, DUTY CYCLE = 10%
PW = 50µs, DUTY CYCLE = 5%
PW = 20µs, DUTY CYCLE = 2%
PW = 200µs, DUTY CYCLE = 20%
PW = 100µs, DUTY CYCLE = 10%
40
PW = 50µs, DUTY CYCLE = 5%
PW = 20µs, DUTY CYCLE = 2%
39
0.9
0
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.0
1.1
1.2
1.3
1.4
1.5
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 33. P
OUT
vs. Frequency at Various Pulse Widths (PW)
and Duty Cycles, P
IN
= 16 dBm
Figure 36. PAE vs. Frequency at Various Pulse Widths
and Duty Cycles, P
IN
= 16 dBm
Rev. 0 | Page 10 of 16
Data Sheet
70
60
50
40
30
20
32
30
28
26
24
22
20
18
16
PW = 500µs, DUTY CYCLE = 20%
PW = 500µs, DUTY CYCLE = 20%
PW = 200µs, DUTY CYCLE = 20%
PW = 100µs, DUTY CYCLE = 10%
PW = 50µs, DUTY CYCLE = 5%
PW = 20µs, DUTY CYCLE = 2%
PW = 200µs, DUTY CYCLE = 20%
PW = 100µs, DUTY CYCLE = 10%
PW = 50µs, DUTY CYCLE = 5%
PW = 20µs, DUTY CYCLE = 2%
10
0
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 37. PAE vs. Frequency at Various Pulse Widths
and Duty Cycles, P
IN
= 19 dBm
Figure 40. Gain vs. Frequency at Various Pulse Widths
and Duty Cycles, P
IN
= 19 dBm
32
30
28
26
24
22
20
18
16
65
60
55
50
45
40
35
30
25
20
15
10
5
1600
1500
1400
1300
1200
1100
1000
900
P
OUT
GAIN
PAE
I
DD
800
700
600
PW = 500µs, DUTY CYCLE = 20%
PW = 200µs, DUTY CYCLE = 20%
PW = 100µs, DUTY CYCLE = 10%
PW = 50µs, DUTY CYCLE = 5%
PW = 20µs, DUTY CYCLE = 2%
500
400
0
300
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
–6 –4 –2
0
2
4
6
8
10 12 14 16 18 20 22
FREQUENCY (GHz)
INPUT POWER (dBm)
Figure 38. Gain vs. Frequency at Various Pulse Widths
and Duty Cycles, P
IN
= 16 dBm
Figure 41. P
OUT
, Gain, PAE, and I
DD
vs. Input Power
at 1.2 GHz
60
55
50
45
40
35
30
25
20
15
10
5
1800
1675
1550
1425
1300
1175
1050
925
65
60
55
50
45
40
35
30
25
20
15
10
5
1600
1500
1400
1300
1200
1100
1000
900
P
P
OUT
OUT
GAIN
GAIN
PAE
PAE
I
I
DD
DD
800
800
700
675
600
550
500
425
400
0
300
0
300
–7 –5 –3 –1
1
3
5
7
9
11 13 15 17 19 21 23
P
(dBm)
P
(dBm)
IN
IN
Figure 39. P
OUT
, Gain, PAE, and Supply Current (I
DD
) vs. P
IN
at 0.9 GHz
Figure 42. P
OUT
, Gain, PAE, and I
DD
vs. P
IN
at 1.6 GHz
Rev. 0 | Page 11 of 16
Data Sheet
45
45
40
40
35
30
25
20
15
10
5
35
30
25
20
15
10
5
1.6GHz
1.5GHz
1.4GHz
1.3GHz
1.2GHz
1.1GHz
1.0GHz
0.9GHz
1.6GHz
1.5GHz
1.4GHz
1.3GHz
1.2GHz
1.1GHz
1.0GHz
0.9GHz
0
–6
0
–6
–1
4
9
14
19
24
–1
4
9
14
19
24
P
(dBm)
P
(dBm)
IN
IN
Figure 46. P
DISS
vs. P
IN
, Drain Bias Pulse Width = 200 μs
at 20% Duty Cycle, T
BASE
= 85°C
Figure 43. P
DISS
vs. P
IN
, Drain Bias Pulse Width = 100 μs
at 10% Duty Cycle, T
BASE
= 85°C
45
40
45
40
35
30
25
20
15
10
5
35
30
25
20
15
10
5
1.6GHz
1.5GHz
1.4GHz
1.3GHz
1.2GHz
1.1GHz
1.0GHz
0.9GHz
1.6GHz
1.5GHz
1.4GHz
1.3GHz
1.2GHz
1.1GHz
1.0GHz
0.9GHz
0
–6
0
–6
–1
4
9
14
19
24
–1
4
9
14
19
24
P
(dBm)
P
(dBm)
IN
IN
Figure 47. P
DISS
vs. P
IN
, Drain Bias Pulse Width = 50 μs
at 5% Duty Cycle, T
BASE
= 85°C
Figure 44. P
DISS
vs. P
IN
, Drain Bias Pulse Width = 20 μs
at 2% Duty Cycle, T
BASE
= 85°C
550
500
450
400
350
300
250
200
150
100
50
10
+85°C
+25°C
–40°C
1
0.1
0.01
0
–50
25
27
29
31
33
35
37
39
41
43
OUTPUT POWER (dBm)
V
AND V
(V)
GG2
GG1
Figure 45. Detector Voltage (VREF − VDET) vs. Output Power for
Various Temperatures at 1.2 GHz
Figure 48. I
DQ
vs. V
GG1
and V
GG2
, V
DD1
and V
DD2
= 50 V,
Representative of a Typical Device
Rev. 0 | Page 12 of 16
Data Sheet
THEORY OF OPERATION
The ADPA1105 is a GaN power amplifier that delivers 46 dBm
(40 W) of pulsed power. The device consists of two cascaded
gain stages. A simplified view of this architecture is shown in
The recommended dc biasing results in a typical pulsed RF
output power and PAE of 46 dBm and 60%, respectively, at
1.5 GHz when the input power is 19 dBm.
A portion of the RF output signal is directionally coupled to a
diode to detect the RF output power. When the diode is dc biased,
the diode rectifies the RF power and makes the RF power
available for measurement as a dc voltage at the VDET pin. A
symmetrical diode circuit that is not coupled to the RF output,
which contains a dc voltage output at the VREF pin, is referenced
to accomplish temperature compensation. The difference of
VREF − VDET provides a temperature compensated signal that
is proportional to the RF output.
The ADPA1105 has single-ended RFIN and RFOUT ports that
are dc blocked. The impedances of these ports are nominally
50 Ω over the 0.9 GHz to 1.6 GHz operating frequency range.
Consequently, the ADPA1105 can be directly inserted into a
50 Ω system without the need for external impedance matching
components or ac coupling capacitors.
The pulsed bias voltages applied to the V
DD1
and V
DD2
pins bias
the drains of the first and second gain stages, respectively (a single
common supply voltage must be used). The negative dc voltages
applied to the V
GG1
and V
GG2
pins bias the gates of the first and
second gain stages, respectively, to allow control of the drain
currents for each stage (a single common gate voltage must
be used).
V
V
DD2
DD1
RFIN
RFOUT
DIRECTIONAL
COUPLER
V
V
GG2
GG1
VREF VDET
Figure 49. Basic Block Diagram
Rev. 0 | Page 13 of 16
Data Sheet
APPLICATIONS INFORMATION
Apply a voltage between 0 V and −4 V to the V
GG1
and V
GG2
BASIC CONNECTIONS
lines to set the bias level and drain current. Because the
ADPA1105 cannot support continuous operation, the device
must be operated in pulsed mode by pulsing either the gate
voltage or the drain voltage.
The basic connections for operating the ADPA1105 are shown
to the V
DD1
and V
DD2
pins. Decouple each pin with the capacitor
two 1000 pF power supply decoupling capacitors connected to Pin
28 and Pin 31 (V
DD2
and V
DD1
). Tie together the two gate voltage
Pin 2, Pin 3, Pin 7, Pin 12, Pin 13, Pin 18, Pin 22, Pin 23, Pin 26,
Pin 27, Pin 29, and Pin 30 are designated as no connect (NC) pins.
Although these pins are not internally connected, the pins were
all connected to ground during the characterization of the device
and provide some additional thermal relief.
In gate pulsed mode, V
DD
is held at a fixed level (nominally
+50 V) while the gate voltage is pulsed between −4 V (off) and
approximately −2.3 V (on). The exact on level can be adjusted
to achieve the desired quiescent drain current.
In drain pulsed mode, the V
DD
voltage is pulsed on and off
while the gate voltage is held at a fixed negative level between
0 V and −4 V. Because high currents and voltages are being
switched on and off, a metal-oxide semiconductor field effect
transistor (MOSFET) and a MOSFET switch driver are required
in the circuit. Large capacitors are also required, which act as
local reservoirs of charge and help provide the drain current
required by the ADPA1105 while maintaining a steady drain
voltage during the on time of the pulse.
The decoupling capacitors on the V
DD1
, V
DD2
, V
GG1
, and V
GG2
lines represent the configuration that was used to characterize
and qualify the ADPA1105. The user can reduce the number of
capacitors, but the result varies from system to system. General
guidance is to first remove or combine the largest capacitors
that are farthest from the device.
plugin pulser board that contains the required circuitry to
more information.
External bias is provided to the on-chip RF detection circuit via
two 715 Ω resistors that are pulled up to 5 V, which results in a
current draw of approximately 12 mA. An operation amplifier
configured as a differential amplifier can be used to subtract
VDET from VREF to yield a temperature compensated voltage
that is proportional to the RF output power.
V
DD
50V/2A
C13
0.39nF
C3
1000pF
C14
1000pF
C12
0.39nF
3.9Ω
3.9Ω
V
V
DD2
DD1
1
2
3
4
5
6
7
8
24
GROUND
PAD
23
22
21
20
19
18
17
RFOUT
RFIN
5V
V
V
GG2
GG1
V
715Ω
715Ω
GG
C4
1µF
C6
0.01µF
C10
100pF
(0V TO –4V)
VREF
VDET
C5
1µF
C7
0.01µF
C11
100pF
Figure 50. Basic Connection
Rev. 0 | Page 14 of 16
Data Sheet
POWER DISSIPATED
DURING THE PULSE
THERMAL MANAGEMENT
Proper thermal management is critical to achieve the specified
performance and rated operating life. Pulsed biasing is required
to limit the average power dissipated and maintain a safe channel
temperature. The channel (or die) temperature correlates
closely with the mean time to failure.
T
CHAN
t
RISE
= θ
× P
JC
DISS
T
BASE
TIME
applied, the channel temperature (T
CHAN
) of the device rises
through a turn on transient interval and eventually settles to a
steady state value. Calculate the θ
JC
thermal resistance of the
device as the rise in T
CHAN
above the starting T
BASE
divided by the
total device
P
DISS
with the following equation:
Figure 52. Pulsed Bias at Low Duty Cycle
Transient thermal measurements were performed on the
ADPA1105 amplifier at several different bias pulse widths and
Table 7. Pulse Settings and Thermal Resistance Values
θ
JC
=
t
RISE
/
P
DISS
where:
RISE
is the peak rise in the T
CHAN
of the device above the T
BASE
(°C).
DISS
is the power dissipation (W) of the device.
(1)
Pulse Settings
Pulse Width (μs)
Duty Cycle (%)
θ
JC
(°C/W)
2.11
2.82
t
P
100
200
300
10
20
30
3.54
T
CHAN
Narrower pulse widths and/or lower duty cycles can result in
greater reliability.
t
RISE
= θ
× P
JC
DISS
The ADPA1105 amplifier is designed for low duty cycle pulsed
applications. However, there can be brief periods of time when
the device operates (perhaps accidently) under continuous
bias conditions. The thermal resistance increases to 6.5°C/W
under these conditions. Even at the nominal quiescent bias
T
BASE
TIME
Figure 51. Continuous Bias
When bias is applied, the T
CHAN
of the device can be described
as a series of exponentially rising and decaying pulses. The peak
channel temperature reached during consecutive pulses increases
during the turn on transient interval, and eventually settles to a
steady state condition where peak channel temperatures from
pulse to pulse stabilize.
V
DD1
and V
DD2
= 50 V and I
DD
= 0.4 A), the 20 W power
dissipation results in a 130°C channel temperature rise above
the base temperature. Use extreme caution in this case to ensure
that the device does not exceed the device maximum reliable
channel temperature of 200°C.
Rev. 0 | Page 15 of 16
Data Sheet
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
5.10
5.00 SQ
4.90
0.30
0.25
0.20
PIN 1
INDICATOR
PIN 1
INDICATOR AREA OPTIONS
25
24
32
(SEE DETAIL A)
1
0.50
BSC
3.20
3.10 SQ
3.00
EXPOSED
PAD
17
16
8
9
0.45
0.40
0.35
TOP VIEW
SIDE VIEW
BOTTOM VIEW
3.50 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
1.35
1.25
1.15
0.60 REF
0.40
0.050 MAX
0.035 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
SEATING
PLANE
0.08
0.203 REF
Figure 53. 32-Lead Lead frame Chip Scale Package, Premolded Cavity [LFCSP_CAV]
5 mm × 5 mm Body and 1.25 mm Package Height
(CG-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
1, 2, 3
Temperature MSL
Rating
4
Package Description
Package Option
ADPA1105ACGZN
−40°C to
+85°C
MSL3
32-Lead Lead Frame Chip Scale Package, Premolded Cavity
[LFCSP_CAV]
CG-32-2
ADPA1105ACGZN-R7 −40°C
to
+85°C
MSL3
32-Lead Lead Frame Chip Scale Package, Premolded Cavity
[LFCSP_CAV]
CG-32-2
ADPA1105-EVALZ
Evaluation Board
1
All models are RoHS compliant parts.
2
The lead finish of the ADPA1105ACGZN and the ADPA1105ACGZN-R7 is nickel palladium gold (NiPdAu).
3
When ordering the evaluation board, use the reference model number ADPA1105-EVALZ.
4
See the Absolute Maximum Ratings
section for more information.
©2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D21925-10/20(0)
Rev. 0 | Page 16 of 16
