Analog-Devices-ADRF5026SCCZ-EPR7
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Silicon SPDT Switch, Nonreflective,
100 MHz to 44 GHz
Enhanced Product
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Ultrawideband frequency range: 100 MHz to 44 GHz
Nonreflective design
Low insertion loss: 1.2 dB to 18 GHz, 1.7 dB to 26 GHz, 2.4 dB
to 40 GHz, 3.8 dB to 44 GHz
High isolation: 55 dB to 18 GHz, 53 dB to 26 GHz, 50 dB to
40 GHz, 45 dB to 44 GHz
High input linearity: 27 dBm typical P1dB, 53 dBm typical IP3
High power handling: 24 dBm insertion loss path,
24 dBm isolation path
GND
GND
RFC
GND
GND
1
2
3
4
5
15
VSS
14
EN
50Ω
50Ω
DRIVER
13
GND
12
CTRL
11
VDD
All off state control
No low frequency spurious signals
0.1 dB RF settling time: 40 ns typical
Figure 1.
20-terminal, 3 mm × 3 mm LGA package
ENHANCED PRODUCT FEATURES
Supports defense and aerospace applications (AQEC standard)
Military temperature range (−55°C to +105°C)
Controlled manufacturing baseline
1 assembly/test site
1 fabrication site
Product change notification
Qualification data available on request
APPLICATIONS
Industrial scanners
Test and instrumentation
Cellular infrastructure: 5G mmWave
Military radios, radars, electronic counter measures (ECMs)
Microwave radios and very small aperture terminals (VSATs)
GENERAL DESCRIPTION
The ADRF5026-EP is a nonreflective, single-pole, double-throw
(SPDT) RF switch manufactured in a silicon process.
The ADRF5026-EP RF ports are designed to match a characteris-
tic impedance of 50 Ω. For ultrawideband products, impedance
matching on the RF transmission lines can further optimize
high frequency insertion loss and return loss characteristics.
circuit that achieves a flat insertion loss response of 2.4 dB from
28 GHz to 43 GHz.
The ADRF5026-EP operates from 100 MHz to 44 GHz with
better than 3.8 dB of insertion loss and 45 dB of isolation. The
ADRF5026-EP features an all off control, where both RF ports
are in an isolation state. The ADRF5026-EP has a nonreflective
design and both of the RF ports are internally terminated to 50 Ω.
The ADRF5026-EP comes in a 20-terminal, 3 mm × 3 mm,
RoHS compliant, land grid array (LGA) package and can
operate from −55°C to +105°C.
The ADRF5026-EP requires a dual-supply voltage of +3.3 V
and −3.3 V. The device employs CMOS and low voltage
transistor transistor logic (LVTTL)-compatible controls.
Additional application and technical information can be found
frequency cutoff version, which operates from 9 kHz to 44 GHz.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice.
No license is granted by implication or otherwise under any patent or patent rights of Analog
Devices. Trademarks and registere
d
t
rademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2020 Analog Devices, Inc. All rights reserved.
Enhanced Product
TABLE OF CONTENTS
REVISION HISTORY
10/2020—Revision 0: Initial Version
Rev. 0 | Page 2 of 8
Enhanced Product
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
VDD = 3.3 V, VSS = −3.3 V, CTRL pin voltage (V
CTRL
) = EN pin voltage (V
EN
) = 0 V or VDD, and T
CASE
= 25°C in a 50 Ω system, unless
otherwise noted.
Table 1.
Parameter
Symbol Test
Conditions/Comments
Min
Typ Max
Unit
FREQUENCY RANGE
INSERTION LOSS
100
44,000 MHz
IL
Between RFC and RF1/RF2
100 MHz to 18 GHz
18 GHz to 26 GHz
26 GHz to 35 GHz
35 GHz to 40 GHz
40 GHz to 44 GHz
1
RL
1.2
1.7
2.2
2.4
3.8
dB
dB
dB
dB
dB
RETURN LOSS
RFC and RF1/RF2 (On)
100 MHz to 18 GHz
18 GHz to 26 GHz
26 GHz to 35 GHz
35 GHz to 40 GHz
100 MHz to 18 GHz
18 GHz to 26 GHz
26 GHz to 35 GHz
35 GHz to 40 GHz
22
12
9
10
7
23
23
21
13
12
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
RF1/RF2 (Off)
ISOLATION
Between RFC and RF1/RF2
100 MHz to 18 GHz
18 GHz to 26 GHz
26 GHz to 35 GHz
35 GHz to 40 GHz
40 GHz to 44 GHz
100 MHz to 18 GHz
18 GHz to 26 GHz
26 GHz to 35 GHz
35 GHz to 40 GHz
40 GHz to 44 GHz
55
53
53
50
45
63
60
60
63
55
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Between RF1 and RF2
SWITCHING CHARACTERISTICS
Rise and Fall Time
On and Off Time
RF Settling Time
0.1 dB
t
RISE
, t
FALL
10% to 90% of RF output
3
14
ns
ns
t
ON
, t
OFF
50% of triggered V
CTRL
to 90% of RF output
50% of triggered V
CTRL
to 0.1 dB of final RF output
50% of triggered V
CTRL
to 0.05 dB of final RF output
100 MHz to 40 GHz
40
45
ns
ns
0.05 dB
INPUT LINEARITY
1 dB Compression
Third-Order Intercept
SUPPLY CURRENT
Positive
P1dB
IP3
27
53
dBm
dBm
Two-tone input power = 12 dBm each tone, Δf = 1 MHz
VDD and VSS pins
I
DD
I
SS
2
100
µA
µA
Negative
Rev. 0 | Page 3 of 8
Enhanced Product
Parameter
Symbol Test
Conditions/Comments
Min
Typ Max
Unit
DIGITAL CONTROL INPUTS
CTRL and EN pins
Voltage
Low
High
V
INL
V
INH
0
1.2
0.8
3.3
V
V
Current
Low and High Current
I
INL
, I
INH
<1
µA
RECOMMENDED OPERATING
CONDITONS
Supply Voltage
Positive
Negative
Digital Control Voltage
RF Input Power
2
Insertion Loss Path
VDD
VSS
V
CTRL
, V
EN
P
IN
3.15
−3.45
0
3.45
−3.15
VDD
V
V
V
f = 100 MHz to 40 GHz, T
CASE
= 85°C
3
RF signal is applied to RFC or through connected
RF1/RF2
24
dBm
Isolation Path
Hot Switching
RF signal is applied to terminated RF1/RF2
RF signal is present at RFC while switching between RF1
and RF2
24
24
dBm
dBm
Case Temperature
T
CASE
−55
+105
°C
1
Impedance matching on RF transmission lines improves high frequency performance. Refer to th
e
ADRF5026
data sheet for more information.
2
For power derating vs. frequency, see
Figure 2
and
Figure 3.
This power derating is applicable for insertion loss path, isolation path, and hot switching power
specifications.
3
For 105°C operation, the power handling degrades from the T
CASE
= 85°C specification by 3 dB.
Rev. 0 | Page 4 of 8
Enhanced Product
ABSOLUTE MAXIMUM RATINGS
POWER DERATING CURVES
2
Table 2.
Parameter
0
–2
Rating
Positive Supply Voltage
Negative Supply Voltage
Digital Control Inputs
Voltage
−0.3 V to +3.6 V
−3.6 V to +0.3 V
–4
−0.3 V to VDD + 0.3 V
3 mA
–6
Current
–8
RF Input Power
1
(100 MHz to 40 GHz at
T
CASE
= 85°C
2
)
–10
–12
–14
Insertion Loss Path
Isolation Path
Hot Switching
26 dBm
25 dBm
25 dBm
10k
100k
1M
10M
100M
1G
10G
100G
Temperature
FREQUENCY (Hz)
Junction, T
J
Storage Range
Reflow
135°C
−65°C to +150°C
260°C
Figure 2. Power Derating vs. Frequency, Low Frequency Detail, T
CASE
= 85°C
2
0
–2
Electrostatic Discharge (ESD) Sensitivity
Human Body Model (HBM)
RFC, RF1, RF2 Pins
Digital Pins
500 V
2000 V
1250 V
–4
Charged Device Model (CDM)
–6
derating is applicable for insertion loss path, isolation path, and hot
switching power specifications.
–8
2
For 105°C operation, the power handling degrades from the T
CASE
= 85°C
specification by 3 dB.
–10
–12
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
30
32
34
36
38
40
42
44
46
48
50
FREQUENCY (GHz)
Figure 3. Power Derating vs. Frequency, High Frequency Detail, T
CASE
= 85°C
0.500
0.450
0.400
0.350
0.300
0.250
0.200
0.150
0.100
0.050
0
Only one absolute maximum rating can be applied at any one
time.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θ
JC
is the junction to case bottom (channel to package bottom)
thermal resistance.
–55 –45 –35 –25 –15
–5
5
15 35 35 45 55 65 75 85 95
105
CASE TEMPERATURE (°C)
Table 3. Thermal Resistance
Package Type
Figure 4. Maximum Power Dissipation vs. Case Temperature
θ
JC
Unit
CC-20-4
Through Path
Terminated Path
ESD CAUTION
423
241
°C/W
°C/W
Rev. 0 | Page 5 of 8
Enhanced Product
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADRF5026-EP
20 19 18 17 16
1
2
3
4
5
15
14
13
12
11
GND
GND
RFC
GND
GND
VSS
EN
TOP VIEW
(Not to Scale)
GND
CTRL
VDD
6
7
8
9
10
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED
TO THE RF AND DC GROUND OF THE PCB.
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic Description
1, 2, 4, 5, 6, 7, 9, 10,
13, 16, 17, 19, 20
3
GND
RFC
RF1
Ground. These pins must be connected to the RF and dc ground of the PCB.
RF Common Port. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is
RF1 Port. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is necessary
8
11
12
14
15
18
VDD
CTRL
EN
VSS
RF2
Positive Supply Voltage.
Negative Supply Voltage.
RF2 Port. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is necessary
EPAD
Exposed Pad. The exposed pad must be connected to the RF and dc ground of the PCB.
INTERFACE SCHEMATICS
VDD
VDD
CTRL, EN
RFC,
RF1,
RF2
Figure 7. CTRL, EN Interface Schematic
Figure 6. RFC, RF1, RF2 Interface Schematic
Rev. 0 | Page 6 of 8
Enhanced Product
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 3.3 V, VSS = −3.3 V, V
CTRL
/V
EN
= 0 V or VDD, and T
CASE
= 25°C in a 50 Ω system, unless otherwise noted.
Insertion loss is measured on the probe matrix board using ground-signal-ground (GSG) probes close to the RFx pins. Signal coupling
between the probes limits the isolation performance of the ADRF5026-EP. Isolation is measured on the
ADRF5026-EVALZ
evaluation board.
0
–1
–2
–3
–4
–5
T
T
T
T
T
= +105°C
= +85°C
= +25°C
= –55°C
= –40°C
–6
–7
–8
CASE
CASE
CASE
CASE
CASE
0
5
10
15
20
25
30
35
40
45
50
FREQUENCY (GHz)
Figure 8. Insertion Loss vs. Frequency over Temperature
Rev. 0 | Page 7 of 8
Enhanced Product
OUTLINE DIMENSIONS
3.10
3.00
2.90
0.25
0.20
0.15
0.30
0.25
0.20
CHAMFERED
PIN 1 (0.3 × 4
5
°
)
PIN 1
CORNER AREA
16
20
0.75
REF
1
15
1.60
1.50 SQ
1.40
1.60 REF
SQ
EXPOSED
PAD
11
5
0.40
BSC
10
6
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.13
REF
FOR PROPER CONNECTION OF
THE EXPOSED PADS, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.776
0.726
0.676
0.530 REF
SECTION OF THIS DATA SHEET.
0.236
0.196
0.156
Figure 9. 20-Terminal Land Grid Array [LGA]
3 mm × 3 mm Body and 0.726 mm Package Height
(CC-20-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model
1
Temperature Range
−55°C to +105°C
−55°C to +105°C
Package Description
Package Option
CC-20-4
CC-20-4
Marking Code
ADRF5026SCCZ-EP
ADRF5026SCCZ-EPR7
20-Terminal Land Grid Array [LGA]
20-Terminal Land Grid Array [LGA]
6EP
6EP
1
Z = RoHS Compliant Part.
©2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D23688-10/20(0)
Rev. 0 | Page 8 of 8
