Analog-Devices-ADRF5547BCPZN
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Dual-Channel, 3.7 GHz to 5.3 GHz,
Receiver Front End
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
ADRF5547
Integrated dual-channel RF front end
2-stage LNA and high power SPDT switch
On-chip bias and matching
Single-supply operation
Gain
High gain mode: 33 dB typical at 4.6 GHz
Low gain mode: 18 dB typical at 4.6 GHz
Low noise figure
GND
GND
ANT-ChA
GND
1
2
3
4
5
6
7
8
9
30 GND
29 RxOUT-ChA
28 GND
27 BP-ChA
26 PD-ChAB
25 NIC
24 BP-ChB
23 GND
SWCTRL-ChAB
SWVDD-ChAB
GND
High gain mode: 1.6 dB typical at 4.6 GHz
Low gain mode: 1.6 dB typical at 4.6 GHz
High channel to channel isolation
Between RxOUT-ChA and RxOUT-ChB: 45 dB typical
Between TERM-ChA and TERM-ChB: 53 dB typical
Low insertion loss: 0.50 dB typical at 4.6 GHz
High power handling at T
CASE
= 105°C
Full lifetime
ANT-ChB
GND
22 RxOUT-ChB
21 GND
GND 10
Figure 1.
LTE average power (9 dB PAR): 40 dBm
Single event (<10 sec operation)
LTE average power (9 dB PAR): 43 dBm
High OIP3: 31 dBm typical
Power-down mode and low gain mode for LNA
Low supply current
High gain mode: 86 mA typical at 5 V
Low gain mode: 36 mA typical at 5 V
Power-down mode: 12 mA typical at 5 V
Positive logic control
40-lead, 6 mm × 6 mm LFCSP
APPLICATIONS
Wireless infrastructure
TDD massive multiple input and multiple output (MIMO) and
active antenna systems
TDD-based communication systems
In low gain mode, one stage of the two-stage LNAs is in bypass,
providing 18 dB gain at lower current of 36 mA. In power-down
mode, the LNAs are turned off and the device draws 12 mA.
GENERAL DESCRIPTION
The ADRF5547 is a dual-channel, integrated RF, front end
multichip module designed for time division duplexing (TDD)
applications that operates from 3.7 GHz to 5.3 GHz. The
ADRF5547 is configured in dual channels with a cascading
two-stage low noise amplifier (LNA) and a high power silicon,
single-pole, double-throw (SPDT) switch.
In transmit operation, when RF inputs are connected to a
termination pin (TERM-ChA or TERM-ChB), the switch
provides a low insertion loss of 0.50 dB and handles long term
evolution (LTE) average power (9 dB peak to average ratio
(PAR)) of 40 dBm for full lifetime operation and 43 dBm for
single event (<10 sec) LNA protection operation.
In high gain mode, the cascaded, two-stage LNA and switch
offer a low noise figure of 1.6 dB and high gain of 33 dB at
4.6 GHz with an output third order intercept point (OIP3) of
31 dBm (typical).
The device comes in an RoHS compliant, compact, 40-lead,
6 mm × 6 mm LFCSP.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice.
No license is granted by implication or otherwise under any patent or patent rights of Analog
Devices. Trademarks and registere
d
t
rademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2019–2022 Analog Devices, Inc. All rights reserved.
Data Sheet
TABLE OF CONTENTS
REVISION HISTORY
1/2022—Rev. A to Rev. B
6/2020—Rev. 0 to Rev. A
Changes to Charge Device Model (CDM) Parameter, Table 2……
.
5
Changes to Figure 8, Figure 9, Figure 11, and Figure 13 ………… 8
Changes to Figure 14 and Figure 15 …………………………………………. 9
Changes to Figure 16, Figure 17, Figure 19, and Figure 2
1
.
….. 10
Changes to Figure 22 and Figure 23 …………………………………….. 11
Changes to Figure 24 …………………………………………………………… 12
Changes to Theory of Operation Section …………………………….. 13
Changes to Applications Information Section and Figure 28……. 14
10/2019—Revision 0: Initial Version
Rev. B | Page 2 of 15
Data Sheet
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
VDD1-ChA, VDD1-ChB, VDD2-ChA, VDD2-ChB, and SWVDD-ChAB = 5 V, SWCTRL-ChAB = 0 V or SWVDD-ChAB, BP-ChA =
VDD1-ChA or 0 V, BP-ChB = VDD1-ChB or 0 V, PD-ChAB = 0 V or VDD1-ChA, and T
CASE
= 25°C on a 50 Ω system, unless otherwise
noted.
Table 1
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
FREQUENCY RANGE
3.7
5.3
GHz
Receive operation at 4.6 GHz
High Gain Mode
Low Gain Mode
High Gain Mode
Low Gain Mode
High Gain Mode
Low Gain Mode
33
18
dB
dB
Receive operation in any 100 MHz bandwidth
Receive operation at 4.6 GHz
0.6
0.2
dB
dB
1.6
1.6
dB
dB
OUTPUT THIRD ORDER INTERCEPT POINT
Receive operation, two-tone output power = 8 dBm
per tone at 1 MHz tone spacing
High Gain Mode
Low Gain Mode
31
22
dBm
dBm
OUTPUT 1 dB COMPRESSION (OP1dB)
High Gain Mode
Low Gain Mode
18
6
dBm
dBm
dB
Transmit operation at 4.6 GHz
At 4.6 GHz
Receive operation
Transmit operation
0.50
Between RxOUT-ChA and RxOUT-ChB
Between TERM-ChA and TERM-ChB
45
53
dB
dB
ANT-ChA to TERM-ChA and ANT-ChB to
TERM-ChB
Transmit operation, PD-ChAB = 0 V
20
dB
SWITCHING CHARACTERISTICS (T
ON
, T
OFF
)
50% control voltage to 90%, 10% of RxOUT-ChA or
RxOUT-ChB in receive operation
50% control voltage to 90%, 10% of TERM-ChA or
TERM-ChB in transmit operation
860
800
ns
ns
RECOMMENDED OPERATING CONDITIONS
Bias Voltage Range
Receive operation, LTE average (9 dB PAR)
15
dBm
VDD1-ChA, VDD1-ChB, VDD2-ChA, VDD2-ChB,
SWVDD-ChAB
SWCTRL-ChAB, BP-ChA, BP-ChB, PD-ChAB
4.75
0
5
5.25
V
DD
V
V
RF Input Power at ANT-ChA, ANT-ChB
SWCTRL-ChAB = 5 V, BP-ChA = BP-ChB = 0 V, PD-
Continuous wave
9 dB PAR LTE full lifetime average
9 dB PAR LTE single event (<10 sec) average
40
40
43
+105
dBm
dBm
dBm
°C
Case Temperature Range (T
CASE
)
−40
Receive operation
Transmit operation
132
134
°C
°C
Rev. B | Page 3 of 15
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DIGITAL INPUTS
SWCTRL-ChAB, PD-ChAB
Low (V
IL
)
0
1.4
0.7
V
DD
V
V
High (V
IH
)
2
BP-ChA, BP-ChB
Low (V
IL
)
High (V
IH
)
2
0
1.0
0.3
V
DD
V
V
SUPPLY CURRENT (I
DD
)
VDD1-ChA, VDD1-ChB, VDD2-ChA, and VDD2-ChB =
5 V per channel
High Gain Mode
Low Gain Mode
Power-Down Mode
86
36
12
4.3
mA
mA
mA
mA
Transmit Current (Switch)
SWVDD-ChAB = 5 V
DIGITAL INPUT CURRENTS
SWCTRL-ChAB, PD-ChAB, BP-ChA, BP-ChB =
5 V per channel
SWCTRL-ChAB
PD-ChAB
BP-ChA, BP-ChB
0.0004
0.2
0.4
mA
mA
mA
2
V
DD
(shown in the maximum column) is the voltage of the SWVDD-ChAB, VDD1-ChA, VDD1-ChB, VDD2-ChA, and VDD2-ChB pins.
3
Measured at the exposed pad (EPAD).
Rev. B | Page 4 of 15
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operation environment. Careful attention to
PCB thermal design is required.
Parameter
Rating
Positive Supply Voltage
VDD1-ChA, VDD1-ChB, VDD2-ChA,
VDD2-ChB
7 V
θ
JC
is the junction to case bottom (channel to package bottom)
SWVDD-ChAB
5.4 V
thermal resistance.
Digital Control Input Voltage
SWCTRL-ChAB
−0.3 V to V
DD
1
+ 0.3 V
−0.3 V to V
DD
1
+ 0.3 V
Table 3. Thermal Resistance
Package Type
θ
JC
Unit
BP-ChA, BP-ChB, PD-ChAB
CP-40-15
RF Input Power (LTE Peak)
Transmit
Receive
High Gain and Low Gain Mode
Power-Down Mode
30
8.7
°C/W
°C/W
53 dBm
25 dBm
Temperature
Storage
Reflow (Moisture Sensitivity Level (MSL) 3
Rating)
ESD CAUTION
−65°C to +150°C
260°C
Electrostatic Discharge (ESD) Sensitivity
Human Body Model (HBM)
Charge Device Model (CDM)
1 kV, Class 1C
500 V, Class C2A
1
V
DD
is the voltage of the VDD1-ChA, VDD1-ChB, VDD2-ChA, and VDD2-ChB pins.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
Rev. B | Page 5 of 15
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND
GND
ANT-ChA
GND
1
2
3
4
5
6
7
8
9
30 GND
29 RxOUT-ChA
28 GND
27 BP-ChA
26 PD-ChAB
25 NIC
24 BP-ChB
23 GND
ADRF5547
TOP VIEW
(Not to Scale)
SWCTRL-ChAB
SWVDD-ChAB
GND
ANT-ChB
GND
22 RxOUT-ChB
21 GND
GND 10
NOTES
1. NIC = NOT INTERNALLY CONNECTED. IT IS RECOMMENDED
TO CONNECT NIC TO THE RF GROUND OF THE PCB.
2. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED
TO RF OR DC GROUND.
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 2, 4, 7, 9 to 11, 14 to 16, 21, 23, 28, 30, 35 to 37, 40
GND
RF Input to Channel A.
3
5
ANT-ChA
SWCTRL-ChAB Control
Voltage for Switches on Channel A and Channel B. See
Figure 7
for the interface schematic.
6
SWVDD-ChAB
Supply Voltage for Switches on Channel A and Channel B. See
Figure 7
for the interface schematic.
8
12
ANT-ChB
TERM-ChB
NIC
RF Input to Channel B.
Termination Output. This pin is the transmitter path for Channel B.
Not Internally Connected. It is recommended to connect NIC to the
RF ground of the PCB.
13, 18, 19, 25, 32, 33, 38
17
20
22
24
26
27
29
31
34
39
VDD1-ChB
VDD2-ChB
RxOUT-ChB
BP-ChB
interface schematic.
interface schematic.
for the interface schematic.
interface schematic.
Power-Down All Stages of LNA for Channel A and Channel B. See
Figure 6
for the Interface schematic.
interface schematic.
the interface schematic.
interface schematic.
PD-ChAB
BP-ChA
RxOUT-ChA
VDD2-ChA
VDD1-ChA
interface schematic.
Termination Output. This pin is the transmitter path for Channel A.
Exposed Pad. The exposed pad must be connected to RF or dc ground.
TERM-ChA
EPAD
Rev. B | Page 6 of 15
Data Sheet
INTERFACE SCHEMATICS
PD-ChAB,
BP-ChA,
BP-ChB
CLAMP
GND
GND
GND
Figure 6. PD-ChAB, BP-ChA, and BP-ChB Interface Schematic
Figure 3. GND Interface Schematic
SWVDD-ChAB
CLAMP
VDD
GND
GND
RxOUT-ChA,
RxOUT-ChB
SWCTRL-ChAB
GND
Figure 7. SWCTRL-ChAB, SWVDD-ChAB Interface Schematic
Figure 4. RxOUT-ChA and RxOUT-ChB Interface Schematic
VDD1-ChA, VDD1-ChB,
VDD2-ChA, and VDD2-ChB
CLAMP
GND
GND
Figure 5. VDD1-ChA, VDD1-ChB, VDD2-ChA, and VDD2-ChB
Interface Schematic
Rev. B | Page 7 of 15
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
RECEIVE OPERATION, HIGH GAIN MODE
40
38
36
34
32
30
28
26
24
22
20
35
30
25
20
15
10
T
T
T
= +105°C
= +25°C
= –40°C
T
T
T
= +105°C
= +25°C
= –40°C
A
A
A
A
A
A
5
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
3.5
4.0
4.5
5.0
5.5
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 8. Gain vs. Frequency at Various Temperatures
Figure 11. Gain vs. Frequency at Various Temperatures, 3.5 GHz to 5.5 GHz
–20
–30
–40
–50
–60
–70
0
–5
–10
–15
–20
–25
–30
T
= +25°C
A
INPUT
OUTPUT
ISOLATION RxOUT-ChA TO RxOUT-ChB
ISOLATION RxOUT-ChB TO RxOUT-ChA
–80
2
3
4
5
6
2
3
4
5
6
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 12. Channel to Channel Isolation vs. Frequency
Figure 9. Return Loss vs. Frequency
3.0
40
35
30
2.5
2.0
1.5
1.0
0.5
0
25
20
15
T
T
T
= +105°C
= +25°C
= –40°C
T
T
T
= +105°C
= +25°C
= –40°C
A
A
A
A
A
A
3.5
4.0
4.5
5.0
5.5
3.5
4.0
4.5
5.0
5.5
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 13. OIP3 vs. Frequency for Various Temperatures,
8 dBm Output Tone Power
Figure 10. Noise Figure vs. Frequency for Various Temperatures
Rev. B | Page 8 of 15
Data Sheet
45
40
35
30
25
20
24
22
20
18
16
14
12
T
T
T
= +105°C
= +25°C
= –40°C
A
A
A
T
T
T
= +105°C
= +25°C
= –40°C
A
A
A
10
4.2
15
2
4.4
4.6
4.8
5.0
5.2
4
6
8
10
12
FREQUENCY (GHz)
OUTPUT POWER (dBm)
Figure 15. OP1dB vs. Frequency at Various Temperatures
Figure 14. OIP3 vs. Output Power for Various Temperatures, 4.6 GHz
Rev. B | Page 9 of 15
Data Sheet
RECEIVE OPERATION, LOW GAIN MODE
25
20
18
16
14
12
10
20
15
10
5
T
T
T
= +105°C
= +25°C
= –40°C
T
T
T
= +105°C
= +25°C
= –40°C
A
A
A
A
A
A
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
3.5
4.0
4.5
5.0
5.5
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 16. Gain vs. Frequency at Various Temperatures
Figure 19. Gain vs. Frequency at Various Temperatures,
3.5 GHz to 5.5 GHz
–20
0
–30
–5
–40
–50
–60
–10
–15
–20
–70
–80
–90
T
= 25°C
A
–25
–30
INPUT
OUTPUT
ISOLATION RxOUT-ChA TO RxOUT-ChB
ISOLATION RxOUT-ChB TO RxOUT-ChA
2
3
4
5
6
2
3
4
5
6
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 17. Return Loss vs. Frequency
Figure 20. Channel to Channel Isolation vs. Frequency
3.0
35
30
25
2.5
2.0
1.5
1.0
0.5
0
20
15
10
T
T
T
= +105°C
= +25°C
= –40°C
T
T
T
= +105°C
= +25°C
= –40°C
A
A
A
A
A
A
3.5
4.0
4.5
5.0
5.5
4.2
4.4
4.6
4.8
5.0
5.2
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 18. Noise Figure vs. Frequency at Various Temperatures
Figure 21. OIP3 vs. Frequency at Various Temperatures,
−8 dBm Output Tone Power
Rev. B | Page 10 of 15
Data Sheet
35
30
25
20
15
12
10
8
6
4
2
T
T
T
= +105°C
= +25°C
= –40°C
T
T
T
= +105°C
= +25°C
= –40°C
A
A
A
A
A
A
10
–14
0
4.2
–12
–10
–8
–6
–4
4.4
4.6
4.8
5.0
5.2
OUTPUT POWER (dBm)
FREQUENCY (GHz)
Figure 22. OIP3 vs. Output Power for Various Temperatures, 4.6 GHz
Figure 23. OP1dB vs. Frequency at Various Temperatures
Rev. B | Page 11 of 15
Data Sheet
TRANSMIT OPERATION
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
T
T
T
= +105°C
= +25°C
= –40°C
A
A
A
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
2
3
4
5
6
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 24. Insertion Loss vs. Frequency at Various Temperatures
Figure 26. Channel to Channel Isolation vs. Frequency
0
–5
0
–10
–20
–30
–40
–10
–15
–20
–25
–30
–50
–60
–35
INPUT
OUTPUT
LNA ON
–40
2
3
4
5
6
2
3
4
5
6
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 25. Return Loss vs. Frequency
Figure 27. Antenna to Termination Isolation vs. Frequency
Rev. B | Page 12 of 15
Data Sheet
THEORY OF OPERATION
The ADRF5547 requires a positive supply voltage applied to
VDD1-ChA, VDD2-ChA, VDD1-ChB, VDD2-ChB, and
SWVDD-ChAB. Use bypassing capacitors on the supply lines
to filter noise and use 300 Ω series resistors on the BP-Chx and
PD-ChAB digital control pins for glitch and overcurrent
protection.
When PD-ChAB is set to low, the LNA powers up and the user
can select high gain mode or low gain mode. To select high gain
mode, set BP-ChA or BP-ChB to low. To select low gain mode,
set BP-ChA or BP-ChB to high.
When PD-ChAB is set to high, the ADRF5547 enters power-down
mode. To select power-down high isolation mode, set BP-ChA
or BP-ChB to low. To select power-down low isolation mode,
set BP-ChA or BP-ChB to high.
SIGNAL PATH SELECT
When SWCTRL-ChAB is set to high, the ADRF5547 supports
transmit operations. During this operation, when applying an RF
input to ANT-ChA and ANT-ChB, the signal paths connect from
ANT-ChA to TERM-ChA and from ANT-ChB to TERM-ChB.
BIASING SEQUENCE
To power up the ADRF5547, perform the following steps:
1. Connect
GND to ground.
2. Power
up VDD1-ChA, VDD2-ChA, VDD1-ChB, VDD2-
ChB, and SWVDD-ChAB.
3. Power
up SWCTRL-ChAB.
4. Power
up PD-ChAB.
When SWCTRL-ChAB is set to low, the ADRF5547 supports
receive operations. During this operation, applying an RF input
at ANT-ChA and ANT-ChB connects ANT-ChA to RxOUT-ChA
and ANT-ChB to RxOUT-ChB.
5. Power
up BP-ChA and BP-ChB.
Receive Operation
6. Apply
an RF input signal to ANT-ChA and ANT-ChB.
The ADRF5547 supports high gain mode, low gain mode,
power-down high isolation mode, and power-down low
To power down the ADRF5547, perform these steps in the
reverse order.
Table 5. Truth Table: Signal Path
Signal Path Select
SWCTRL-ChAB
Low
High
Transmit Operation
1
Receive Operation
Off
On
On
Off
Table 6. Truth Table: Operation
Operation
PD-ChAB
BP-ChA, BP-ChB
Low
High
Low
High
Signal Path
Receive Operation
High Gain Mode
Low Gain Mode
Power-Down High Isolation Mode
Power-Down Low Isolation Mode
ANT-ChA to RxOUT-ChA, ANT-ChB to RxOUT-ChB
Low
Low
High
High
Rev. B | Page 13 of 15
Data Sheet
APPLICATIONS INFORMATION
To generate the evaluation PCB used in the application circuit
Signal lines at the RF port must have a 50 Ω impedance, and
the package ground leads and the backside ground slug must
connect directly to the ground plane. Use 300 Ω series resistors
on the BP-Chx and PD-ChAB digital control pins for glitch and
overcurrent protection.
on the evaluation board.
R4
VDD2_ChA
VDD2_A
0Ω
VDD1_A
VDD1_ChA
1
BLU
DNI
VDD2_ChA
ORG
C16
10µF
C17
1000pF
GND
YEL
GND1
YEL
C12
C13
1000pF
10µF
DNI
AGND
C9
2pF
200V
1
1
AGND
1
R7
TERM_A
142-0701-851
TERM_ChA
0Ω
AGND
2
3
4
RxO_A
C24
R1
1
AGND
0Ω
142-0701-851
100pF
DNI
4
3
2
C22
2pF
0.3pF
200V
1
2
30
GND
GND
GND
C26
29
RxOUT_ChA
200V
ANT_A
142-0701-851
RxOUT-ChA
U1
ADRF5547
R22
3
28
27
26
25
24
23
22
21
ANT_ChA
1
AGND
AGND
ANT-ChA
GND
GND
BP-ChA
PD-ChAB
NIC
BP_A
YEL
4
BP_ChA
PD
C6
C1
DNI
0Ω
SWCTRL
ORG
2
3
4
DNI
SWCTRL_ChAB
5
0Ω
(300Ω)
SWCTRL-ChAB
SWVDD-ChAB
GND
0.3pF
200V
0.3pF
200V
6
0Ω
(300Ω)
PD
RED
BP_B
WHT
7
BP-ChB
GND
AGND
C19
100pF
AGND
8
0Ω
(300Ω)
AGND
ANT-ChB
GND
R2
9
RxOUT_ChB
RxOUT-ChB
GND
10
0Ω
C27
DNI
0.3pF
200V
GND
AGND
C4
100pF
C5
C3
100pF
SWVDDB
BLK
100pF
SWVDD_ChAB
AGND
C18
10µF
DNI
VDD2_B
GRN
AGND
AGND
AGND
1
C23
VDD2_ChB
AGND
2pF
200V
C25
ANT_B
RxO_B
1
R23
ANT_CHB
1
C10
1000pF
C11
10µF
AGND
142-0701-851
142-0701-851
VDD1_B
BRN
C8
2pF
200V
100pF
C7
C2
0Ω
4
3
2
DNI
DNI
1
2
3
4
R3
TERM_B
VDD2_ChB
0.3pF
200V
0.3pF
200V
AGND
1
142-0701-851
2
0Ω
AGND
C14
1000pF
C15
10µF
R8
0Ω
AGND
3
4
AGND
AGND
AGND
AGND
THRU1
THRU2
C20
C21
THRU CAL
R5
R6
1
1
142-0701-851
142-0701-851
2
0Ω
0Ω
100pF
100pF
3
4
4
3
2
AGND
AGND
Figure 28. Application Circuit
Rev. B | Page 14 of 15
Data Sheet
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
6.10
6.00 SQ
5.90
0.30
0.25
0.18
PIN 1
INDICATOR
AREA
PIN 1
IONS
INDIC
A
T
OR
A
R
E
A
O
P T
(SEE DETAIL A)
31
40
30
1
0.50
BSC
4.70
EXPOSED
PAD
4.60 SQ
4.50
21
10
20
11
0.45
0.40
0.35
0.20 MIN
TOP VIEW
SIDE VIEW
BOTTOM VIEW
1.00
0.95
0.85
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-5
Figure 29. 40-Lead Lead Frame Chip Scale Package [LFCSP]
6 mm × 6 mm Body and 0.95 mm Package Height
(CP-40-15)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature Range
Package Description
Package Option
CP-40-15
CP-40-15
ADRF5547BCPZN
ADRF5547BCPZN-R7
ADRF5547BCPZN-RL
ADRF5547-EVALZ
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
40-Lead Lead Frame Chip Scale Package [LFCSP]
40-Lead Lead Frame Chip Scale Package [LFCSP]
40-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
CP-40-15
1
Z = RoHS Compliant Part.
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registered trademarks are the property of their respective owners.
D20790-1/22(B)
Rev. B | Page 15 of 15
