Analog-Devices-ADRF6801ACPZ-R7
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750 MHz to 1150 MHz Quadrature
Demodulator with Fractional-N PLL and VCO
Data Sheet
FEATURES
GENERAL DESCRIPTION
IQ demodulator with integrated fractional-N PLL
LO frequency range: 750 MHz to 1150 MHz
Input P1dB: 12.5 dBm
Input IP3: 25 dBm
Noise figure (DSB): 14.3 dB
Voltage conversion gain: 5.1 dB
Quadrature demodulation accuracy
Phase accuracy: 0.3°
The ADRF6801 is a high dynamic range IQ demodulator with
integrated PLL and VCO. The fractional-N PLL/synthesizer
generates a frequency in the range of 3.0 GHz to 4.6 GHz. A
divide-by-4 quadrature divider divides the output frequency of
the VCO down to the required local oscillator (LO) frequency
to drive the mixers in quadrature. Additionally, an output buffer
can be enabled that generates an f
VCO
/2 signal for external use.
The PLL reference input is supported from 10 MHz to 160 MHz.
The phase detector output controls a charge pump whose output
is integrated in an off-chip loop filter. The loop filter output is
then applied to an integrated VCO.
Amplitude accuracy: 0.05 dB
Baseband demodulation: 275 MHz, 3 dB bandwidth
SPI serial interface for PLL programming
40-lead, 6 mm × 6 mm LFCSP
The IQ demodulator mixes the differential RF input with the
complex LO derived from the quadrature divider. The differential
I and Q output paths have excellent quadrature accuracy and
can handle baseband signaling or complex IF up to 120 MHz.
APPLICATIONS
QAM/QPSK RF/IF demodulators
Cellular W-CDMA/CDMA/CDMA2000
Microwave point-to-(multi)point radios
Broadband wireless and WiMAX
The ADRF6801 is fabricated using an advanced silicon-germanium
BiCMOS process. It is available in a 40-lead, exposed-paddle,
RoHS-compliant, 6 mm × 6 mm LFCSP package. Performance is
specified over the −40°C to +85°C temperature range.
FUNCTIONAL BLOCK DIAGRAM
GND VCCLO VCCLO
LOSEL
IBBP
33
IBBN
32
GND
31
35
34
36
17
BUFFER
CTRL
30
ADRF6801
GND
LON
37
29
28
27
VCCBB
GND
BUFFER
BUFFER
38
LOP
VCCRF
DIVIDER
÷1
INTEGER
REG
FRACTION
REG
MODULUS
MUX
11
GND
DATA
CLK
LE
OR
÷2
12
13
14
15
SPI
QUAD
÷2
THIRD-ORDER
INTERFACE
26
RFIN
FRACTIONAL
INTERPOLATOR
PRESCALER
VCO
CORE
GND
N COUNTER
25
24
GNDRF
GND
÷2
×2
6
7
REFIN
GND
–
+
PHASE
MUX
÷
2
23
22
21
TEMP
CHARGE PUMP
250µA,
500µA (DEFAULT),
750µA,
GND
FREQUENCY
DETECTOR
SENSOR
VCCBB
GND
÷
4
3.3V LDO
2.5V LDO
9
VCO LDO
1000µA
8
MUXOUT
1
2
10
16
3
4
5
39
40
18
19
20
VCC1 DECL3
VCC2
CPOUT GND
RSET
VTUNE
DECL1
QBBP QBBN GND
GND
DECL2
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
right
s
o
f third parties that may result fro
m
i
ts use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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d
r
egistere
d
t
rademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2011–2018 Analog Devices, Inc. All rights reserved.
Data Sheet
TABLE OF CONTENTS
REVISION HISTORY
6/2018—Rev. 0 to Rev. A
Change to Register Structure Section …………………………………… 14
Changes to Register Programming Section ………………………….. 22
1/2011—Revision 0: Initial Version
Rev. A | Page 2 of 34
Data Sheet
SPECIFICATIONS
V
S
= 5 V; ambient temperature (T
A
) = 25°C; f
REF
= 26 MHz, f
LO
= 900 MHz, f
BB
= 4.5 MHz, R
LOAD
= 450 Ω differential, all register and PLL
Table 1.
Parameter
Test Conditions/Comments
RFIN pins
With VCO amplitude = 63 (R6 [DB15 to DB10])
With VCO amplitude = 24 (R6 [DB15 to DB10])
Measured at 900 MHz
Min
Typ
Max Unit
RF INPUT AT 900 MHz
Internal LO Frequency Range
750
750
1125 MHz
1150 MHz
dB
Input Return Loss
Input P1dB
Second-Order Input Intercept (IIP2)
Third-Order Input Intercept (IIP3)
Noise Figure
<−20
12.5
>65
25
14.3
18.9
−75
dBm
dBm
dBm
dB
dB
dBm
−5 dBm each tone
−5 dBm each tone
Double sideband from RF to either I or Q output
With a −10 dBm interferer 5 MHz away
At 1×LO frequency, 50 Ω termination at the RF port
IBB
P
,
I
BBN, QBB
P
,
Q
BBN pins
450 Ω differential load across IBB
P
,
I
BBN (or QBB
P
,
Q
BBN)
1 V p-p signal 3 dB bandwidth
LO-to-RF Leakage
I/Q BASEBAND OUTPUTS
Voltage Conversion Gain
Demodulation Bandwidth
Quadrature Phase Error
I/Q Amplitude Imbalance
Output DC Offset (Differential)
Output Common-Mode Voltage
Gain Flatness
5.1
275
0.3
0.05
5
V
POS
− 2.4
0.2
4
2.4
12
dB
MHz
Degrees
dB
mV
V
dB p-p
V p-p
V p-p
mA p-p
Any 5 MHz (<100 MHz)
Differential 450 Ω load
Differential 200 Ω load
Each pin
Maximum Output Swing
Maximum Output Current
LO INPUT/OUTPUT
Output Level
LO
P
,
L
ON
Into a differential 50 Ω load, LO buffer enabled (LO
frequency = 900 MHz, output frequency = 1800 MHz)
−2.5
dBm
Input Level
Input Impedance
VCO Operating Frequency
Externally applied 2×LO, PLL disabled
Externally applied 2×LO, PLL disabled
With VCO amplitude = 63 (R6 [DB15 to DB10])
With VCO amplitude = 24 (R6 [DB15 to DB10])
0
50
dBm
Ω
4500 MHz
3000
3000
4600 MHz
SYNTHESIZER SPECIFICATIONS
All synthesizer specifications measured with
Channel Spacing
PLL Bandwidth
f
PFD
= 26 MHz; modulus = 2047
Can be adjusted with off-chip loop filter component
values and R
SET
25
130
kHz
kHz
SPURS
f
LO
= 900 MHz, f
REF
= 26 MHz, f
PFD
= 26 MHz, measured
at BB outputs with f
BB
= 50 MHz
Reference Spurs
f
REF
= 26 MHz, f
PFD
= 26 MHz
f
PFD
/2
f
PFD
× 2
f
PFD
× 3
−91.6
−107.8
−89.1
−94.2
dBc
dBc
dBc
dBc
Rev. A | Page 3 of 34
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max Unit
PHASE NOISE (USING 130 kHz LOOP FI
L
T
ER)
f
LO
= 900 MHz, f
REF
= 26 MHz, f
PFD
= 26 MHz, measured
at BB outputs with f
BB
= 50 MHz
1 kHz offset
−99.5
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
°rms
10 kHz offset
100 kHz offset
500 kHz offset
1 MHz offset
5 MHz offset
10 MHz offset
−107.8
−106.6
−126.7
−131.7
−143.5
−150.5
0.16
Integrated Phase Noise
1 kHz to 10 MHz integration bandwidth
PHASE NOISE (USING 2.5 kHz LOOP FI
L
T
ER)
f
LO
= 900 MHz, f
REF
= 26 MHz, f
PFD
= 26 MHz, measured
at BB outputs with f
BB
= 50 MHz
1 kHz offset
10 kHz offset
100 kHz offset
500 kHz offset
1 MHz offset
5 MHz offset
10 MHz offset
−71.3
−88.3
−114.1
−129.5
−138.6
−150.2
−150.3
−215.4
−220.9
26
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
PLL FIGURE OF MERIT (FOM)
Measured with f
REF
= 26 MHz, f
PFD
= 26 MHz
Measured with f
REF
= 104 MHz, f
PFD
= 26 MHz
dBc/Hz/Hz
dBc/Hz/Hz
MHz
Phase Detector Frequency
REFERENCE CHARACTERISTICS
REFIN Input Frequency
REFIN Input Capacitance
MUXOUT Output Level
20
10
40
REFIN, MUXOUT pins
Usable range
160
0.25
MHz
pF
V
4
V
OL
(lock detect output selected)
V
OH
(lock detect output selected)
2.7
V
REFOUT Duty Cycle
CHARGE PUMP
50
%
Pump Current
Output Compliance Range
LOGIC INPUTS
500
µA
V
1
2.8
CLK, DATA, LE pins
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
INH
/I
INL
Input Capacitance, C
IN
POWER SUPPLIES
1.4
0
3.3
0.7
V
V
µA
pF
0.1
5
VCC1, VCC2, VCCLO, VCCBB, VCCRF pins
Voltage Range (5 V)
Supply Current (5 V)
4.75
5
5.25
V
Normal Rx mode, internal LO
Rx mode, internal LO with LO buffer enabled
Rx mode, using external LO input (internal VCO, PLL shut
down)
262
288
157
mA
mA
mA
Supply Current (5 V)
Power-down mode
20
mA
Rev. A | Page 4 of 34
Data Sheet
TIMING CHARACTERISTICS
V
S
= 5
V
,
u
nless otherwise noted.
Table 2.
Parameter
Limit at T
MIN
to T
MAX
(B Version)
Unit
Test Conditions/Comments
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
t
1
t
2
t
3
t
4
t
5
t
6
t
7
20
10
10
25
25
10
20
ns min
ns min
ns min
ns min
ns min
ns min
ns min
CLK to LE setup time
LE pulse width
Timing Diagram
t
4
t
5
CLOCK
t
2
t
3
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
DB23 (MSB)
DB22
DB2
DATA
LE
t
7
t
1
t
6
LE
Figure 2. Timing Diagram
Rev. A | Page 5 of 34
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
ESD CAUTION
Parameter
Rating
Supply Voltage, VCC1, VCC2, VCCLO,
VCCBB, and VCCRF (V
S1
)
−0.5 V to +5.5 V
Digital I/O, CLK, DATA, and LE
RFIN
−0.3 V to +3.6 V
16 dBm
θ
JA
(Exposed Paddle Soldered Down)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
30°C/W
150°C
−40°C to +85°C
−65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. A | Page 6 of 34
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VCO
LDO
BUFFER
CTRL
30 GND
VCC1
DECL3
CPOUT
GND
1
2
29 VCCBB
28 GND
SCALE
BLEED
PHASE DETECTOR
AND
3
CHARGE PUMP
27 VCCRF
26 RFIN
4
5
6
7
8
9
DIV
CTRL
RSET
DIV
÷1
OR
÷2
VCO
BAND
VCO
3000MHz
TO
QUADRATURE
÷2
6
6
MUX
×
2
CURRENT
CAL/SET
25 GNDRF
24 GND
REFIN
GND
4600MHz
MUX
÷2
÷4
PROGRAMABLE
DIVIDER
PRESCALER
÷2
ENABLE
23 GND
MUXOUT
DECL2
22 VCCBB
21 GND
2.5V
LDO
THIRD-ORDER
SDM
VCC2 10
MODULUS
FRACTION
INTEGER
SERIAL PORT
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
The 5 V Power Supply Pin for VCO and PLL (VCC1).
Decoupling Node for the 3.3 V LDO. Connect a 0.1 µF capacitor between this pin and ground.
Charge Pump Output Pin. Connect this pin to VTUNE through the loop filter.
Connect these pins to a low impedance ground plane.
1
2
3
VCC1
DECL3
CPOUT
GND
4, 7, 11, 15, 16, 20, 21,
23, 24, 28, 30, 31, 35
Rev. A | Page 7 of 34
Data Sheet
Pin No.
Mnemonic
Description
5
RSET
Charge Pump Current. The nominal charge pump current can be set to 250 µA, 500 µA, 750 µA, or 1
mA using DB10 and DB11 of Register 4 and by setting DB18 to 0 (internal reference current). In this
mode, no external R
SET
is required. If DB18 is set to 1, the four nominal charge pump currents
(I
NOMINAL
) can be externally tweaked according to the following equation where the resulting value is in
units of ohms.
217.
4
×
I
CP
I
NOMINAL
R
SET
=
−
37.8
6
8
REFIN
MUXOUT
Reference Input. Nominal input level is 1 V p-p. Input range is 10 MHz to 160 MHz.
Multiplexer Output. This output can be programmed to provide the reference output signal or
the lock detect signal. The output is selected by programming the appropriate register.
9
DECL2
VCC2
DATA
CLK
Decoupling Node for 2.5 V LDO. Connect a 0.1 µF capacitor between this pin and ground.
The 5 V power supply pin for the 2.5 V LDO.
Serial Data Input. The serial data is loaded MSB first with the three LSBs being the control bits.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the 24-bit shift register on the CLK rising edge. Maximum clock frequency is 20 MHz.
10
12
13
14
LE
Load Enable. When the LE input pin goes high, the data stored in the shift registers is loaded into
one of the six registers, the relevant latch being selected by the first three control bits of the 24-bit
word.
17, 34
18, 19
22, 29
25
VCCLO
QBB
P
,
Q
BBN
VCCBB
GNDRF
RFIN
The 5 V Power Supply for the LO Path Blocks.
Demodulator Q-Channel Differential Baseband Outputs; Differential Output Impedance of 24 Ω.
The 5 V Power Supply for the Baseband Output Section of the Demodulator Blocks.
Ground Return for RF Input Balun.
26
Single-Ended, Ground Referenced 50 Ω, RF Input.
27
32, 33
36
VCCRF
IBBN, IBBP
LOSEL
The 5 V Power Supply for the RF Input Section of the Demodulator Blocks.
Demodulator I-Channel Differential Baseband Outputs; Differential Output Impedance of 24 Ω.
LO Select. Connect this pin to ground for the simplest operation and to completely control the LO
path and input/output direction from the register SPI programming.
For additional control without register reprogramming, this input pin can determine whether the
LOP and LON pins operate as inputs or outputs. LOP and LON become inputs if the LOSEL pin is
set low, the LDRV bit of Register 5 is set low, and the LXL bit of Register 5 is set high. The
externally applied LO drive must be at 2×LO frequency (and the LDIV bit of Register 5 (DB5) set
low). LON and LOP become outputs when LOSEL is high or if the LDRV bit of Register 5 (DB3) is set
high and the LXL bit of Register 5 (DB4) is set low. The output frequency is 2×LO frequency (and
the LDIV bit of Register 5 (DB5) must be set high). This pin should not be left floating.
37, 38
LON, LOP
Local Oscillator Input/Output. When these pins are used as output pins, a differential frequency
divided version of the internal VCO is available on these pins. When the internal LO generation is
disabled, an external M×LO frequency signal can be applied to these pins (where M corresponds
to the LO path divider setting). (Differential Input/Output Impedance of 50 Ω)
39
40
VTUNE
DECL1
EP
VCO Control Voltage Input. This pin is driven by the output of the loop filter. The nominal input
voltage range on this pin is 1.0 V to 2.8 V.
Connect a 10 µF capacitor between this pin and ground as close to the device as possible
because this pin serves as the VCO supply and loop filter reference.
Exposed Paddle. The exposed paddle should be soldered to a low impedance ground plane.
Rev. A | Page 8 of 34
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
V
S
= 5
V
,
T
A
= 25°C, unless otherwise noted. LO = 750 MHz to 1150 MHz.
16
80
75
70
65
60
55
50
14
IP1dB
12
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
10
8
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
GAIN
6
I CHANNEL
Q CHANNEL
4
2
0
750
750
800
850
900
950
1000 1050
1100
1150
800
850
900
950
1000
1050
1100
1150
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 4. Conversion Gain and Input P1dB vs. LO Frequency
Figure 7. Input IP2 vs. LO Frequency
35
20
33
31
29
27
25
23
21
19
17
15
19
18
17
16
15
14
13
12
11
10
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
750
800
850
900
950
1000
1050 1100
1150
750
800
850
900
950
1000
1050
1100
1150
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 5. Input IP3 vs. LO Frequency
Figure 8. Noise Figure vs. LO Frequency
5
1.0
0.8
4
3
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
0.6
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
2
0.4
1
0.2
0
0
–1
–2
–3
–4
–5
–0.2
–0.4
–0.6
–0.8
–1.0
750
800
850
900
950
1000
1050
1100
1150
750
800
850
900
950
1000
1050
1100
1150
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 6. IQ Gain Mismatch vs. LO Frequency
Figure 9. IQ Quadrature Phase Error vs. LO Frequency
Rev. A | Page 9 of 34
Data Sheet
1
0
–50
–55
–60
–65
–70
–75
–80
–85
–90
–1
–2
–3
–4
–5
–6
–7
1
10
100
750
800
850
900
950
1000
1050
1100
1150
LO FREQUENCY (MHz)
BASEBAND FREQUEN
C
Y
(MHz)
Figure 10. LO-to-RF Feedthrough vs. LO Frequency, LO Output Turned Off
Figure 13. Normalized Baseband Frequency Response vs. Baseband
Frequency
–
35
80
IIP2
–40
–45
–50
–55
–60
–65
–70
–75
70
60
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
50
40
30
20
10
0
I CHANNEL
Q CHANNEL
IIP3
IP1dB
750
800
850
900
950
1000
1050
1100 1150
5
10
15
20
25
30
35
40
45
50
LO FREQUENCY (MHz)
BASEBAND FREQUEN
C
Y (MHz)
Figure 11. LO-to-BB Feedthrough vs. LO Frequency, LO Output Turned Off
Figure 14. Input P1dB, Input IP2, and Input IP3 vs. Baseband Frequency
–
30
34
32
30
28
26
24
22
20
18
16
14
12
10
–35
–40
–45
–50
–55
–60
–65
–70
750
800
850
900
950
1000
1050
1100
1150
–35
–30
–25
–20
–15
–10
–5
0
5
RF FREQUENCY (MHz)
INPUT BLOCKER POWER (dBm)
Figure 12. RF-to-BB Feedthrough vs. RF Frequency
Figure 15. Noise Figure vs. Input Blocker Level,
LO
= 900 MHz (RF Blocker 5 MHz Offset)
f
Rev. A | Page 10 of 34
Data Sheet
0
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
–5
–10
–15
–20
–25
–30
–35
–40
750
800
850
900
950
1000
1050
1100
1150
–40
–15
10
35
60
85
RF FREQUENCY (MHz)
TEMPERATURE (°C)
Figure 16. RF Input Return Loss vs. RF Frequency
Figure 19. VPTAT vs. Temperature
0
–2
3.5
3.0
2.5
2.0
1.5
1.0
0.5
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
–4
–6
–8
–10
12
–14
–16
1500
1600
1700
1800 1900
2000
2100
2200
2300
750
800
850
900
950
1000 1050
1100
1150
LO
P
,
L
ON OUTPUT FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 17. LO Output Return Loss vs. LO Output Frequency, LO Output
Enabled (1500 MHz to 2300 MHz), Measured through TC1-1-13 Balun
Figure 20. VTUNE vs. LO Frequency
400
380
360
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
340
320
300
280
260
240
220
200
750
800
850
900
950
1000
1050
1100
1150
LO FREQUENCY (MHz)
Figure 18. 5 V Supply Currents vs. LO Frequency,
LO Output Enabled
Rev. A | Page 11 of 34
Data Sheet
SYNTHESIZER/PLL
V
S
= 5
V
.
S
ee the
Register Structure
section for recommended settings used. External loop filter bandwidths of ~130 kHz and 2.5 kHz
used (see plots within this section for annotations), f
REF
= f
PFD
= 26 MHz, measured at BB output, f
BB
= 50 MHz, unless otherwise noted.
–
40
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
–60
–80
130kHz LOOP FILTER
BANDWIDTH
–100
–120
–140
–160
2.5kHz LOOP FILTER
BANDWIDTH
750
800
850
900
950
1000
1050
1100
1150
1k
10k
100k
1M
10M
OFFSET FREQUENCY (Hz)
LO FREQUENCY (MHz)
Figure 21. Phase Noise vs. Offset Frequency, f
LO
= 900 MHz, Shown for Loop
Filter Bandwidths of 2.5 kHz and 130 kHz
Figure 24. Integrated Phase Noise vs. LO Frequency (Spurs Omitted), Using
Loop Filter Bandwidth of 130 kHz
–70
–50
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
1 × PFD FREQUENCY
3 × PFD FREQUENCY
0.5 × PFD FREQUENCY
1kHz
OFFSET
–75
–80
–70
10kHz
OFFSET
–90
1kHz OFFSET
–85
–90
–110
130kHz LOOP FILTER BANDWIDTH
2.5kHz LOOP FILTER BANDWIDTH
10kHz
OFFSET
–95
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
–130
5MHz
OFFSET
–100
–105
–110
–150
–170
5MHz
OFFSET
750
800
850
900
950
1000
1050
1100
1150
750
800
850
900
950
1000
1050
1100
1150
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 22. PLL Reference Spurs vs. LO Frequency, Using Loop Filter
Bandwidth of 130 kHz
Figure 25. Phase Noise vs. LO Frequency (1 kHz, 10 kHz, and 5 MHz Offsets),
Shown for Loop Filter Bandwidths of 2.5 kHz and 130 kHz
–
90
–70
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
2 × PFD FREQUENCY
4 × PFD FREQUENCY
–75
–80
–100
–110
–120
–130
–140
–150
–160
100kHz OFFSET
–85
100kHz OFFSET
1MHz OFFSET
–90
–95
–100
–105
–110
1MHz OFFSET
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
130kHz LOOP FILTER BANDWIDTH
2.5kHz LOOP FILTER BANDWIDTH
750
800
850
900
950
1000
1050 1100
1150
750
800
850
900
950
1000
1050
1100
1150
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 26. Phase Noise vs. LO Frequency (100 kHz and 1 MHz Offsets), Shown
for Loop Filter Bandwidths of 2.5 kHz and 130 kHz
Figure 23. PLL Reference Spurs vs. LO Frequency, Using Loop Filter
Bandwidth of 130 kHz
Rev. A | Page 12 of 34
Data Sheet
COMPLEMENTARY CUMULATIVE DISTRIBUTION FUNCTIONS (CCDF)
V
S
= 5
V
,
f
LO
= 900 MHz, f
BB
= 4.5 MHz.
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
T
T
T
= +85°C
= +25°C
= –40°C
GAIN
A
A
A
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
I CHANNEL
Q CHANNEL
IP1dB
60
62
64
66
68
70
72
74
18
2
76
20
3
78
22
4
80
24
5
0
2
4
6
8
10
12
14
16
18
GAIN (dB) AND INPUT P1dB (dBm)
INPUT IP2 (dBm)
Figure 27. Gain and Input P1dB
Figure 30. Input IP2
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
I CHANNEL
Q CHANNEL
T
T
T
= +85°C
A
= +25°C
= –40°C
A
A
15
17
19
21
23
25
27
29
31
33
35
4
6
8
10
12
14
16
INPUT IP3 (dBm)
NOISE FIGURE (dB)
Figure 28. Input IP3
Figure 31. Noise Figure
100
90
80
70
60
50
40
30
20
10
0
10
0
90
80
70
60
50
40
30
20
10
0
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
–0.5 –0.4 –0.3 –0.2 –0.1
0
0.1
0.2
0.3
0.4
0.5
–5
–4
–3
–2
–1
0
1
IQ GAIN MISMATCH (dB)
IQ QUADRATURE PHASE ERROR (Degrees)
Figure 29. IQ Gain Mismatch
Figure 32. IQ Quadrature Phase Error
Rev. A | Page 13 of 34
Data Sheet
CIRCUIT DESCRIPTION
The ADRF6801 integrates a high performance IQ demodulator
with a state-of-the-art fractional-N PLL. The PLL also integrates
a low noise VCO. The SPI port allows the user to control the
fractional-N PLL functions, the demodulator LO divider functions,
and optimization functions, as well as allowing for an externally
applied LO.
BIAS CIRCUITRY
There are several band gap reference circuits and three low
dropout regulators (LDOs) in the ADRF6801 that generate the
reference currents and voltages used by different sections. The
first of the LDOs is the 2.5 V LDO, which is always active and
provides the 2.5 V supply rail used by the internal digital logic
blocks. The 2.5 V LDO output is connected to DECL2 (Pin 9)
for the user to provide external decoupling.
The ADRF6801 uses a high performance mixer core that results
in an exceptional input IP3 and input P1dB, with a very low output
noise floor for excellent dynamic range.
The second LDO is the VCO LDO, which acts as the positive
supply rail for the internal VCO. The VCO LDO output is
connected to DECL2 (Pin 40) for the user to provide external
decoupling. The VCO LDO can be powered down by setting
Register 6, DB18 = 0, which allows the user to save power when
not using the VCO.
LO QUADRATURE DRIVE
A signal at 2× the desired mixer LO frequency is delivered to
a divide-by-2 quadrature phase splitter followed by limiting
amplifiers which then drive the I and Q mixers, respectively.
V-TO-I CONVERTER
The third LDO is the 3.3 V LDO, which acts as the 3.3 V
positive supply rail for the reference input, phase frequency
detector, and charge pump circuitry. The 3.3 V LDO output is
connected to DECL3 (Pin 2) for the user to provide external
decoupling. The 3.3 V LDO can be powered down by setting
Register 6, DB19 = 0, which allows the user to save power when
not using the VCO. The demodulator also has a bias circuit that
supplies bias current for the mixer V-to-I stage, which then sets
the bias for the mixer core. The demodulator bias cell can also
be shut down by setting Register 5, DB7 = 0.
The RF input signal is applied to an on-chip balun which then
provides both a ground referenced, 50 Ω single-ended input
impedance and a differential voltage output to a V-to-I converter
that converts the differential voltages to differential output currents.
These currents are then applied to the emitters of the Gilbert
cell mixers.
MIXERS
The ADRF6801 has two double-balanced mixers: one for the
in-phase channel (I channel) and one for the quadrature channel
(Q channel). These mixers are based on the Gilbert cell design
of four cross-connected transistors. The output currents from
the two mixers are summed together in the resistive loads that
then feed into the subsequent emitter follower buffers.
REGISTER STRUCTURE
The ADRF6801 provides access to its many programmable
features through a 3-wire SPI control interface that is used to
program the seven internal registers. The minimum delay and
SPI provides digital control of the internal PLL/VCO as well as
several other features related to the demodulator core, on-chip
referencing, and available system monitoring functions. The
MUXOUT pin provides a convenient, single-pin monitor output
signal that can be used to deliver a PLL lock-detect signal or an
internal voltage proportional to the local junction temperature.
EMITTER FOLLOWER BUFFERS
The output emitter followers drive the differential
I and Q signals
off chip. The output impedance is set by on-chip 12 Ω series
resistors that yield a 24 Ω differential output impedance for each
baseband port. The fixed output impedance forms a voltage divider
with the load impedance that reduces the effective gain. For example,
a 500 Ω differential load has ~0.5 dB lower effective gain than
with a high (10 kΩ) differential load impedance.
Note that internal calibration for the PLL must run when the
ADRF6801 is initialized at a given frequency. This calibration is run
automatically whenever Register 0, Register 1, or Register 2 is
programmed. Because the other registers affect PLL performance,
Register 0, Register 1, and Register 2 must always be programmed
last. For ease of use, starting the initial programming with
Register 6 and then programming the registers in descending
order, ending with Register 0, is recommended. Once the PLL
and other settings are programmed, the user can change the
PLL frequency simply by programming Register 0, Register 1,
or Register 2 as necessary.
The common-mode dc output levels of the emitter followers are set
from VCCBB via the voltage drop across the mixer load resistors,
the V
BE
of the output emitter follower, and the voltage drop
across the 12 Ω series resistor.
Rev. A | Page 14 of 34
Data Sheet
DIVIDE
MODE
INTEGER DIVIDE RATIO
CONTROL BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
DB9 DB8
DB7 DB6 DB5
DB4 DB3 DB2
DB1
DB0
0
0
0
0
0
0
0
0
0
0
0
0
0
DM
ID6 ID5
ID4 ID3
ID2
ID1
ID0 C3(0) C2(0) C1(0)
DM
DIVIDE MODE
0
1
FRACTIONAL (DEFAULT)
INTEGER
DIVIDE RATIO
ID6
0
ID5
0
ID4
1
ID3
0
ID2
1
ID1
0
ID0
21 (INTEGER MODE ONLY)
1
0
22 (INTEGER MODE ONLY)
0
0
1
0
1
1
23 (INTEGER MODE ONLY)
0
0
1
0
1
1
1
24
0
0
1
1
0
0
0
…
…
…
0
…
…
1
…
…
1
…
…
1
…
…
0
…
…
0
…
…
0
…
56 (DEFAULT)
…
…
…
1
…
…
1
…
…
1
…
…
0
…
…
1
…
…
1
…
…
1
…
119
120 (INTEGER MODE ONLY)
121 (INTEGER MODE ONLY)
122 (INTEGER MODE ONLY)
123 (INTEGER MODE ONLY)
1
1
1
1
0
0
0
1
1
1
1
0
0
1
1
1
1
1
0
1
0
1
1
1
1
0
1
1
Figure 33. Integer Divide Control Register (R0)
Register 0—Integer Divide Control
The integer divide ratio sets the INT value in Equation 1. The
IN
T
,
F
RAC, and MOD values make it possible to generate output
frequencies that are spaced by fractions of the PFD frequency.
With R0[2:0] set to 000, the on-chip integer divide control register
frequency (f
VCO
) equation is
Note that the demodulator LO frequency is given by f
LO
= f
VCO
/4.
f
VCO
=
f
PFD
× (
INT
+ (
FRAC
/
MOD
)) × 2
where:
VCO
is the output frequency of the internal VCO.
(1)
Divide Mode
Divide mode determines whether fractional mode or integer mode
is used. In integer mode, the VCO output frequency, f
VCO
, is
calculated by
f
INT
is the preset integer divide ratio value (21 to 123 for integer
mode, 24 to 119 for fractional mode).
MOD
is the preset fractional modulus (1 to 2047).
FRAC
is the preset fractional divider ratio value (0 to MOD − 1).
f
VCO
=
f
PFD
× (
INT
) × 2
(2)
Rev. A | Page 15 of 34
Data Sheet
Register 1—Modulus Divide Control
With R1[2:0] set to 001, the on-chip modulus divide control register is programmed as show
n in Figure 34.
The MOD value is the preset
fractional modulus ranging from 1 to 2047.
MODULUS DIVIDE RATIO
CONTROL BITS
DB2 DB1 DB0
MD0 C3(0)
C2(0) C1(1)
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14
DB13 DB12
DB11 DB10
DB9
MD10 MD9 MD8 MD7 MD6
DB8
MD5
DB7
MD4
DB6
DB5
DB4
DB3
0
0
0
0
0
0
0
0
0
0
MD3 MD2 MD1
MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0
MODULUS VALUE
1
0
0
0
0
0
0
0
0
0
0
1
2
0
0
0
0
0
0
0
0
0
1
0
…
…
…
1
…
…
1
…
…
0
…
…
0
…
…
0
…
…
0
…
…
0
…
…
0
…
…
0
…
…
0
…
…
0
…
1536 (DEFAULT)
…
…
…
1
…
…
1
…
…
1
…
…
1
…
…
1
…
…
1
…
…
1
…
…
1
…
…
1
…
…
1
…
…
1
…
2047
Figure 34. Modulus Divide Control Register (R1)
Register 2—Fractional Divide Control
With R2[2:0] set to 010, the on-chip fractional divide control register is programmed as show
n in Figure 35.
The FRAC value is the preset
fractional modulus ranging from 0 to MOD − 1.
CONTROL BITS
FRACTIONAL DIVIDE RATIO
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
DB9
DB8
FD5
DB7
FD4
DB6
FD3
DB5
FD2
DB4
FD1
DB3
FD0
DB2
DB1
DB0
0
0
0
0
0
0
0
0
0
0
FD10 FD9
FD8
FD7
FD6
C3(0) C2(1) C1(0)
FD10
0
FD9
0
FD8
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
FRACTIONAL VALUE
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
…
…
…
0
…
…
1
…
…
1
…
…
0
…
…
0
…
…
0
…
…
0
…
…
0
…
…
0
…
…
0
…
…
0
…
768 (DEFAULT)
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…
FRACTIONAL VALUE MUST BE LESS THAN MODULUS
<MOD
Figure 35. Fractional Divide Control Register (R2)
Register 3—Σ-Δ Modulator Dither Control
With R3[2:0] set to 011, the on-chip Σ-Δ modulator dither control register is programmed as show
n in Figure 36. The di
ther restart value
can be programmed from 0 to 217 to 1, though a value of 1 is typically recommended.
DITHER
MAGNITUDE
DITHER
ENABLE
DITHER RESTART VALUE
CONTROL BITS
DB23 DB22
DITH1
DB21
DITH0
DB20
DEN
DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DV16 DV15 DV14 DV13 DV12 DV11 DV10
DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0
C3(0) C2(1) C1(1)
0
DEN DITHER
ENABLE
0
1
DISABLE
ENABLE (DEFAULT, RECOMMENDED)
DITH1
DITH0 DITHER
MAGNITUDE
0
0
0
1
15 (DEFAULT)
7
1
1
0
1
3
1 (RECOMMENDED)
DITHER RESTART
VALUE
DV16 DV15 DV14 DV13 DV12 DV11 DV10
DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0
0x00001 (DEFAULT)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
…
…
1
…
…
1
…
…
1
…
…
1
…
…
1
…
…
1
…
…
1
…
…
1
…
…
1
…
…
1
…
…
1
…
…
1
…
…
1
…
…
1
…
…
1
…
…
1
…
…
1
…
…
0x1FFFF
Figure 36. Σ-Δ Modulator Dither Control Register (R3)
Rev. A | Page 16 of 34
Data Sheet
and the divided-down VCO signal. This phase offset is used to
linearize the PFD-CP transfer function and can improve
fractional spurs. The magnitude of the phase offset is
determined by
Register 4—Charge Pump, PFD, and Reference Path
Control
With R4[2:0] set to 100, the on-chip charge pump, PFD, and
reference path control register is programmed as shown in
θ
PFD
,
OFS
ΔΦ[deg
]
=
22.5
I
C
P
,
MULT
The charge pump current is controlled by the base charge
pump current (I
C
P
,
B
ASE
) and the value of the charge pump
current multiplier (I
C
P
,
M
ULT
).
Finally, the phase offset can be either positive or negative
depending on the value of the DB17 bit in Register 4.
The base charge pump current can be set using an internal or
external resistor (according to Bit DB18 of Register 4). When
using an external resistor, the value of I
C
P
,
B
ASE
can be varied
according to
The reference frequency applied to the PFD can be manipulated
using the internal reference path source. The external reference
frequency applied can be internally scaled in frequency by 2×,
1×, 0.5×, or 0.25×. This allows a broader range of reference
frequency selections while keeping the reference frequency
applied to the PFD within an acceptable range.
217.
4
×
I
C
P
,
BASE
R
SET
[
Ω
]
=
−
37.8
250
The ADRF6801 also provides a MUXOUT pin that can be
programmed to output a selection of several internal signals. The
default mode provides a lock-detect output that allows users to
verify when the PLL has locked to the target frequency. In addition,
several other internal signals can be routed to the MUXOUT pin as
The actual charge pump current can be programmed to be a
multiple (1, 2, 3, or 4) of the charge pump base current. The
multiplying value (I
C
P
,
M
ULT
) is equal to 1 plus the value of the
DB11 and DB10 bits in Register 4.
The PFD phase offset multiplier (θ
PFD, OFS
), which is set by Bit
DB16 to Bit DB12 of Register 4, causes the PLL to lock with a
nominally fixed phase offset between the PFD reference signal
Rev. A | Page 17 of 34
Data Sheet
PDF
CHARGE
PUMP
CURRENT
MULTIPLIER
INPUT REF
PATH
SOURCE
CHARGE
PUMP
REF
CP
CNTL
SRC
CHARGE
PUMP
CONTROL
PFD ANTI-
BACKLASH
DELAY
PHASE
OUPUT MUX
SOURCE
PFD PHASE OFFSET
MULTIPLIER VALUE
PFD EDGE
SENSITIVITY
CONTROL BITS
OFFSET
POLARITY
DB23
DB22
DB21 DB20
DB19
DB18
CPM
DB17
DB16 DB15
DB14 DB13 DB12 DB11 DB10
DB9
DB8
DB7
DB6
PE1
DB5
PE0
DB4
DB3
DB2
DB1
DB0
RMS2 RMS1
RMS0
RS1
RS0
CPBD
CPB4 CPB3
CPB2 CPB1 CPB0
CPP1 CPP0
CPS CPC1 CPC0
PAB1 PAB0
C3(1)
C2(0)
C1(0)
PFD ANTIBACKLASH
DELAY
PAB1 PAB0
0
0
0ns (DEFAULT,
RECOMMENDED)
0.5ns
0.75ns
0.9ns
0
1
1
1
0
1
REFERENCE PATH EDGE
SENSITIVITY
PE0
0
1
FALLING EDGE (RECOMMENDED)
RISING EDGE (DEFAULT)
DIVIDER PATH EDGE
SENSITIVITY
PE1
0
1
FALLING EDGE (RECOMMENDED)
RISING EDGE (DEFAULT)
CHARGE PUMP
CONTROL
CPC1 CPC0
BOTH ON
PUMP DOWN
PUMP UP
0
0
1
1
0
1
0
1
TRISTATE (DEFAULT)
CPS CHARGE
PUMP CONTROL SOURCE
0
1
CONTROL BASED ON STATE OF DB7/DB8 (CP CONTROL)
CONTROL FROM PFD (DEFAULT)
CHARGE PUMP
CURRENT MULTIPLIER
CPP1 CPP0
1
0
0
1
1
0
1
0
1
2 (DEFAULT, RECOMMENDED)
3
4
PFD PHASE OFFSET MULTIPLIER
CPB4 CPB3 CPB2 CPB1 CPB0
0 × 22.5°/I
CP, MULT
0
0
0
0
0
1 × 22.5°/I
…
0
…
0
…
0
…
0
…
1
…
CP, MULT
6 × 22.5°/I
…
10 × 22.5°/I
…
(RECOMMENDED)
(DEFAULT)
0
…
0
…
1
0
…
1
…
1
1
…
0
…
1
1
…
1
…
1
0
…
0
…
1
CP, MULT
CP, MULT
31 × 22.5°/I
CP, MULT
CPBD PFD
PHASE OFFSET POLARITY
0
1
NEGATIVE
POSITIVE (DEFAULT, RECOMMENDED)
CHARGE PUMP CURRENT
REFERENCE SOURCE
CPM
INTERNAL (DEFAULT)
EXTERNAL
0
1
INPUT REFERENCE
PATH SOURCE
RS1 RS0
2 × REFERENCE INPUT
0
0
1
1
0
1
0
1
REFERENCE INPUT (DEFAULT)
0.5 × REFERENCE INPUT
0.25 × REFERENCE INPUT
RMS2 RMS1 RMS0 OUTPUT
MUX SOURCE
LOCK DETECT (DEFAULT)
VPTAT
BUFFERED VERSION OF REFERENCE INPUT
BUFFERED VERSION OF 0.5 × REFERENCE INPUT
BUFFERED VERSION OF 2 × REFERENCE INPUT
TRISTATE
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
BUFFERED VERSION OF 0.25 × F
RESERVED (DO NOT USE)
REF
Figure 37. Charge Pump, PFD, and Reference Path Control Register (R4)
Rev. A | Page 18 of 34
Data Sheet
Register 5—LO Path and Demodulator Control
Register 5 controls whether the LOIP and LOIN pins act as an input or output, whether the divider before the polyphase divider is in
divide-by-1 or divide-by-2, and whether the demodulator bias circuitry is enabled as detailed
in Figure 38.
LO
DEMOD
BIAS
ENABLE
LO
LO
IN/OUT
CTRL
OUTPUT
DRIVER
ENABLE
FIRST
CONTROL BITS
DIVIDER
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8 DB7
DB6
0
DB5
DB4
LXL
DB3 DB2
DB1 DB0
LDRV C3(1)
C2(0) C1(1)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMBE
LDIV
LO OUTPUT DRIVER
ENABLE
LDRV
DRIVER OFF (DEFAULT)
DRIVER ON
0
1
LXL LO
IN/OUT CONTROL
LO OUTPUT (DEFAULT)
LO INPUT
0
1
LDIV
DIVIDE RATIO
÷ 1
0
1
÷ 2 (DEFAULT,
NECESSARY FOR VCO USE)
DMBE DEMOD
BIAS ENABLE
DISABLE
ENABLE (DEFAULT)
0
1
Figure 38. LO Path and Demodulator Control Register (R5)
Rev. A | Page 19 of 34
Data Sheet
Register 6—VCO Control and Enables
The VCO amplitude can be controlled through Register 6. The
VCO amplitude setting can be controlled between 0 and 31
decimal, with a default value of 24.
With R6[2:0] set to 110, the VCO control and enables register is
The internal VCO can be disabled using Register 6. The internal
VCO LDO can be disabled if an external clean 3.0 V supply is
available.
VCO band selection is normally selected based on BANDCAL
calibration; however, the VCO band can be selected directly using
Register 6. The VCO BS SRC determines whether the BANDCAL
calibration determines the optimum VCO tuning band or if the
external SPI interface is used to select the VCO tuning band
based on the value of the VCO band select.
The internal charge pump can be disabled through Register 6.
Normally, the charge pump is enabled.
CHARGE
PUMP
3.3V
LDO
VCO
VCO LDO
VCO
VCO
CONTROL BITS
DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
VCO BAND SELECT
BS
VCO AMPLITUDE
ENABLE ENABLE SWITCH
ENABLE ENABLE
CSR
DB23 DB22 DB21
DB20
CPEN
DB19
L3EN
DB18
DB17
DB16 DB15
DB14 DB13 DB12 DB11 DB10
DB9
0
0
0
LVEN VCO
EN VCO
SW VC5 VC4 VC3 VC2 VC1 VC0 VBSRC
VBS5 VBS4 VBS3 VBS2 VBS1 VBS0 C3(1) C2(1) C1(0)
VCO BAND SELECT
FROM SPI
VBS5 VBS4 VBS3 VBS2 VBS1 VBS0
0
0
0
0
0
0
0
…
…
…
…
…
…
…
32 (DEFAULT)
1
…
0
…
0
…
0
…
0
…
0
…
…
63
1
1
1
1
1
1
VBSRC VCO
BAND CAL AND SW SOURCE CONTROL
0
1
BAND CAL (DEFAULT)
SPI
VCO AMPLITUDE
VC5 VC4 VC3 VC2 VC1 VC0
0
0
0
0
0
0
0
…
…
0
…
0
…
1
…
0
…
0
…
0
8 (DEFAULT)
…
47
…
1
…
0
…
1
…
1
…
1
…
1
…
…
1
…
1
…
1
…
1
…
1
…
1
63 (RECOMMENDED)
VCO SW
VCO SWITCH CONTROL FROM SPI
REGULAR (DEFAULT)
BAND CAL
0
1
VCO EN
VCO ENABLE
0
1
DISABLE
ENABLE (DEFAULT)
LVEN VCO
LDO ENABLE
0
1
DISABLE
ENABLE (DEFAULT)
L3EN 3.3V
LDO ENABLE
0
1
DISABLE
ENABLE (DEFAULT)
CHARGE PUMP ENABLE
CPEN
DISABLE
ENABLE (DEFAULT)
0
1
Figure 39. VCO Control and Enables (R6)
Rev. A | Page 20 of 34
Data Sheet
APPLICATIONS INFORMATION
BASIC CONNECTIONS
SYNTHESIZER CONNECTIONS
The basic circuit connections for a typical ADRF6801 application
The ADRF6801 includes an on-board VCO and PLL for LO
synthesis. An external reference must be applied for the PLL to
operate. A 1 V p-p nominal external reference must be applied
to Pin 6 through an ac coupling capacitor. The reference is
compared to an internally divided version of the VCO output
frequency to create a charge pump error current to control and
lock the VCO. The charge pump output current is filtered and
converted to a control voltage through the external loop filter
that is then applied to the VTUNE pin (Pin 39). ADIsimPLL™
can be a helpful tool when designing the external charge pump
loop filter. The typical Kv of the VCO, the charge pump output
current magnitude, and PFD frequency should all be considered
when designing the loop filter. The charge pump current magnitude
can be set internally or with an external RSET resistor connected to
Pin 5 and ground, along with the internal digital settings applied to
Path Control
section for more details).
SUPPLY CONNECTIONS
The ADRF6801 has several supply connections and on-board
regulated reference voltages that should be bypassed to ground
using low inductance bypass capacitors located in close proximity
to the supply and reference pins of the ADRF6801. Specifically
Pin 1, Pin 2, Pin 9, Pin 10, Pin 17, Pin 22, Pin 27, Pin 29, Pin 34,
and Pin 40 should be bypassed to ground using individual bypass
capacitors. Pin 40 is the decoupling pin for the on-board VCO
LDO, and for best phase noise performance, several bypass
capacitors ranging from 100 pF to 10 µF may help to improve
phase noise performance. For additional details on bypassing the
+5V
CHARGE PUMP
LOOP FILTER
IF I-OUTPUT
IF I-OUTPUT
BALUN
40
39
38
37
36
35
34
33
32
31
+5V
VCC1
30
29
GND
+5V
1
2
3
DECL3
CPOUT
VCCBB
GND 28
27
26
4
5
6
VCCRF
RFIN
GND
+5V
OPEN
R2
RSET
RF INPUT
ADRF6801
EXTERNAL
REFERENCE
GND
R
F
2
5
REFIN
G
N
D
7
8
9
24
GND
MONITOR
OUTPUT
G
N
D 23
MUXO
U
T
DECL2
VCCBB
GND
22
21
+5V
10
VCC2
+5V
11
12
13
14
15
16
17
18
19
20
SPI CONTROL
IF Q-OUTPUT
BALUN
IF Q-OUTPUT
+5V
Figure 40. Basic Connections
Rev. A | Page 21 of 34
Data Sheet
I/Q OUTPUT CONNECTIONS
SETTING THE FREQUENCY OF THE PLL
The ADRF6801 has I and Q baseband outputs. Each output
stage consists of emitter follower output transistors with a low
differential impedance of 24 Ω and can source up to 12 mA p-p
differentially. A Mini-Circuits TCM9-1+ balun is used to trans-
form a single-ended 50 Ω load impedance into a nominal 450 Ω
differential impedance.
The frequency of the VCO/PLL, once locked, is governed by the
values programmed into the PLL registers, as follows:
f
PLL
=
f
PFD
× 2 × (
INT
+
FRAC
/
MOD
)
where:
f
f
PLL
is the frequency at the VCO when the loop is locked.
PFD
is the frequency at the input of the phase frequency detector.
RF INPUT CONNECTIONS
INT
is the integer divide ratio programmed into Register 0.
MOD
is the modulus divide ratio programmed into Register 1.
FRAC
is the fractional value programmed into Register 2.
The ADRF6801 is to be driven single-ended and can be either dc
coupled or ac coupled. There is an on-chip ground referenced
balun that converts the applied single-ended signal to a differential
signal that is then input to the RF V-to-I converter.
The practical lower limit of the reference input frequency is
determined by the combination of the desired f
PLL
and the maximum
programmable integer divide ratio of 119 and reference input
frequency multiplier of 2. For a maximum f
PLL
of 4600 MHz,
CHARGE PUMP/VTUNE CONNECTIONS
The ADRF6801 uses a loop filter to create the VTUNE voltage
for the internal VCO. The loop filter in its simplest form is an
integrating capacitor. It converts the current mode error signal
coming out of the CPOUT pin into a voltage to control the VCO
via the VTUNE voltage. The stock filter on the evaluation
board has a bandwidth of 130 kHz. The loop filter contains
seven components, four capacitors, and three resistors. Changing
the values of these components changes the bandwidth of the loop
filter. Note that to obtain the approximately 2.5 kHz loop band-
width, the user can change the values of the following components
on the evaluation board to as follows: C14 = 0.1 µ
F
,
R
10 = 68 Ω,
C15 = 4.7 µ
F
,
R
9 = 270 Ω, C13 = 47 n
F
,
R
60 = 0 Ω, C4 = open.
f
REF
> ~
f
PLL
/(119 × 2 × 2), or 9.7 MHz.
A lock detect signal is available as one of the selectable outputs
through the MUXOUT pin, with logic high signifying that the
loop is locked.
When the internal VCO is used, the actual LO frequency is
f
LO
=
f
PLL
/4
REGISTER PROGRAMMING
Because Register 6 controls the powering of the VCO and
charge pump, it must be programmed once before programming
the PLL frequency (Register 0, Register 1, and Register 2).
LO SELECT INTERFACE
The registers should be programmed starting with the highest
register first and then sequentially down to Register 0 last. When
Register 0, Register 1, or Register 2 is programmed, an internal
VCO calibration is initiated that must execute when the other
registers are set. Therefore, the order must be Register 6, Register 5,
Register 4, Register 3, Register 2, Register 1, and then Register 0.
Whenever Register 0, Register 1, or Register 2 is written to, it
initializes the VCO calibration (even if the value
in these registers does not change). After the device has been
powered up and the registers configured for the desired mode of
operation, only Register 0, Register 1, or Register 2 must be
programmed to change the LO frequency.
The ADRF6801 has the option of either monitoring a scaled
version of the internally generated LO (LOSEL pin driven high
at 3.3 V) or providing an external LO source (LOSEL pin driven
low to ground, the LDRV bit in Register 5 set low, and the LXL bit
Descriptions
section for full operation details.
EXTERNAL LO INTERFACE
The ADRF6801 provides the option to use an external signal
source for the LO into the IQ demodulating mixer core. It is
important to note that the applied LO signal is divided down
by either 2 or 4 depending on the LO path divider bit, LDI
V
,
i
n
Register 5, prior to the actual IQ demodulating mixer core. The
divider is determined by the register settings in the LO path
Demodulator Control
section). The LO input pins (Pin 37 and
Pin 38) present a broadband differential 50 Ω input impedance.
The LOP and LON input pins must be ac-coupled. This is achieved
on the evaluation board via a Mini-Circuits TC1-1-13+ balun with
a 1:1 impedance ratio. When not in use, the LOP and LON pins
can be left unconnected.
If none of the register values is changing from their defaults,
there is no need to program them.
Rev. A | Page 22 of 34
Data Sheet
EVM MEASUREMENTS
EVM is a measure used to quantify the performance of a digital
radio transmitter or receiver. A signal received by a receiver has
all constellation points at their ideal locations; however, various
imperfections in the implementation (such as magnitude imbalance,
noise floor, and phase imbalance) cause the actual constellation
points to deviate from their ideal locations.
The ADRF6801 shows excellent EVM performance for 16 QAM.
Figure 41
shows the EVM of the ADRF6801 being better than
−40 dB over a RF input range of about +35 dB for the 16 QAM
modulated signal at a 10 MHz symbol rate. The pulse shaping
filter
’
s
r
oll-off (alpha) was set to 0.35.
0
In general, a demodulator exhibits three distinct EVM limitations
vs. received input signal power. As signal power increases, the
distortion components increase. At large enough signal levels,
where the distortion components due to the harmonic non-
linearities in the device are falling in-band, EVM degrades
as signal levels increase. At medium signal levels, where the
demodulator behaves in a linear manner and the signal is well
above any notable noise contributions, the EVM has a tendency to
reach an optimal level determined dominantly by either quadrature
accuracy and I/Q gain match of the demodulator or the precision
of the test equipment. As signal levels decrease, such that the
noise is the major contribution, the EVM performance vs. the
signal level exhibits a decibel-for-decibel degradation with
decreasing signal level. At lower signal levels, where noise proves
to be the dominant limitation, the decibel EVM proves to be
directly proportional to the SNR.
–5
–10
–15
–20
–25
–30
–35
–40
–45
–65
–55
–45
–35
–25
–15
–5
5
15
INPUT POWER (dBm)
Figure 41. EVM vs. Input Power, EVM Measurements at f
RF
= 900 MHz;
IF
= 0 MHz (that is, Direct Down Conversion); 16 QAM; Symbol Rate = 10 MHz
f
The basic test setup to test EVM for the ADRF6801 consisted
of an Agilent E4438C, which was used as a signal source. The
900 MHz modulated signal was driven single ended into the
RFIN SMA connector of the ADRF6801 evaluation board. The
difference amplifiers to convert the differential signals into single-
ended signals. A Hewlett Packard 89410A VSA was used to sample
and calculate the EVM of the signal. The ADRF6801 IQ base-
band output pins were presented with a 450 Ω differential load
impedance.
Rev. A | Page 23 of 34
Data Sheet
EVALUATION BOARD LAYOUT AND THERMAL GROUNDING
An evaluation board is available for testing the ADRF6801. The
the component values and suggestions for modifying the
component values for the various modes of operation.
1
2
VCC
VCC_SENSE
OSC_3P3V
VCC_RF
VCC_BB
VCC_LO
VCC4
3
5
7
4
6
8
R55
S1
R29
0Ω
R32
0Ω
R31
0Ω
R13
0Ω
VCC
10kΩ
J1
3P3V_SENSE
2P5V_LDO
R56
VCC_SENSE
VCC
VCC_LO
R33
0Ω
LO
C28
10µF
OUTPUT_EN
LO_EXTERN
10kΩ
LO_EXTERN
R6
0Ω
9
10
VTUNE
VCO_LDO
VCC
VCC_LO
OPEN
R3
R59
OPEN
C8
100pF
C7
0.1µF
IBBP
R4
0Ω
R45
R38
R9
R60
CP
T2
R40
0Ω
3
4
0Ω
10kΩ
10kΩ
0Ω
IOUT_SE
R10
3kΩ
4
3
5
2
OPEN R41
P2
2
C13
6.8pF
R46
C14
22pF
C4
22pF
T1
C15
2.7nF
1
5
0Ω
R5
0Ω
1
R37
0Ω
OPEN
R39
R11
R12
0Ω
IBBN
R1
0Ω
OPEN
VCO_LDO
1nF 1nF
C6 C5
C30
0.1µF
3P3V1
R15
C2
C1
0Ω
10µF 100pF
R27
0Ω
R49
OPEN
3P3V_SENSE
VCC_BB
40
39
38
37
36
35
34
33
32
31
VCC4
VCO_LDO
C26
100pF
C27
0.1µF
R7
VCC_RF
VCC4
VCC1
1
2
3
GND 30
0Ω
R8
VCC_RF
R26
0Ω
C24
100pF
C9
0.1µF
C10
DECL3
CPOUT
GND
VCCBB 29
GND 28
100pF
0Ω
C12
100pF
C11
0.1µF
C25
0.1µF
4
5
6
7
8
9
VCCRF 27
RFIN 26
OPEN
R2
R28
0Ω
RFIN
RSET
ADRF6801
C31
1nF
REFIN
REFIN
GND
GNDRF 25
GND 24
R14
49.9Ω
VCC_BB1
MUXOUT
DECL2
GND 23
R16
R25
REFOUT
VCCBB 22
GND 21
VCC_BB
0Ω
0Ω
C22
100pF
C23
0.1µF
10 VCC2
OPEN
R23
2P5V_LDO
QBBP
R18
11
13
15
17
19
12
14
16
18
20
2P5V
0Ω
C3
10µF
C17
0.1µF
C16
100pF
R21
0Ω
D
A
TA
R47
T3
R43
0Ω
LE
3
4
QOUT_SE
0Ω
2
R44
OPEN
P3
R58
OPEN
VCC
R17
C34
R52
OPEN
R48
C33
OPEN
R51
OPEN
VCC2
OPEN
1
5
0Ω
0Ω
R22
0Ω
C19
0.1µF
C18
100pF
CLK
OPEN
R42
R57
0Ω
R30
0Ω
QBBN
C29
0.1µF
C32
R50
OPEN
OPEN
S2
R20
R35
0Ω
R54
0Ω
VCC
R53
0Ω
10kΩ
OPEN
R19
OPEN
R34
OUTPUT_EN
GND
OPEN
LEGEND
VCC_LO
R24
1
2
3
4
5
NET NAME
GND1
GND2
0Ω
P1
VCC_LO1
C21
100pF
6
7
8
9
TEST POINT
C20
0.1µF
SMA INPUT/OUTPUT
DIG_GND
VTUNE
R36
0Ω
Figure 42. Evaluation Board Schematic
Rev. A | Page 24 of 34
Data Sheet
The package for the ADRF6801 features an exposed paddle on
the underside that should be well soldered to an exposed
illustrates the dimensions used in the layout of the ADRF6801
footprint on the ADRF6801 evaluation board (1 mil. = 0.0254 mm).
Note the use of nine via holes on the exposed paddle. These
ground vias should be connected to all other ground layers on
the evaluation board to maximize heat dissipation from the device
package. Under these conditions, the thermal impedance of the
ADRF6801 was measured to be approximately 30°C/W in still air.
0.012
0.035
0.050
0.168
Figure 44. ADRF6801 Evaluation Board Top Layer
0.025
0.020
0.177
0.232
Figure 43. Evaluation Board Layout Dimensions for the ADRF6801 Package
Figure 45. ADRF6801 Evaluation Board Bottom Layer
Table 5. Evaluation Board Configuration Options
Component
Function
Default Condition
VCC, VCC2, VCC4, VCO_LDO, VCC_LO,
Power supply, ground and other test points.
VCC, VCC2, VCC4, VCC_LO, VCC_RF, VCC_BB1,
VCC_LO1, VCO_LDO, 3P3V1, 2P5V =
Components Corporation TP-104-01-02,
C
P
,
L
E, CLK, DATA =
VCC_LO1, VCC_R
F
,
V
CC_BB1, 3P3V1,
2P5V, CLK, DATA, LE, C
P
,
D
IG_GND,
GND, GND1, GND2
Connect a 5 V supply to VCC.
Components Corporation TP-104-01-06,
GND, GND1, GND2, DIG_GND =
Components Corporation TP-104-01-00
R1, R6, R7, R8, R13, R15, R17, R18,
R24, R25, R26, R27, R29, R31, R32,
R36, R49
Power supply decoupling. Shorts or power supply
decoupling resistors.
R1, R6, R7, R8 = 0 Ω (0402),
R13, R15, R17 = 0 Ω (0402),
R18, R24, R25, R26, R27 = 0 Ω (0402),
R29, R31, R32 = 0 Ω (0402),
R36 = 0 Ω (0402),
Rev. A | Page 25 of 34
Data Sheet
Component
Function
Default Condition
C1, C2, C3, C7, C8, C9, C10, C11, C12,
C16, C17, C18, C19, C20, C21, C22,
C23, C24, C25, C26, C27, C28
The capacitors provide the required decoupling of
the supply-related pins.
C1, C8, C10, C12 = 100 pF (0402),
C16, C18, C21, C22 = 100 pF (0402),
C24, C26 = 100 pF (0402),
C7, C9, C11 = 0.1 µF (0402),
C17, C19, C20, C23 = 0.1 µF (0402),
C25, C27 = 0.1 µF (0402),
C3, C2 = 10 µF (0603), C28 = 10 µF (3216)
T1, C5, C6
External LO path. The T1 transformer provides
single-ended-to-differential conversion. C5 and C6
provide the necessary ac coupling.
C5, C6 = 1 nF (0603),
T1 = TC1-1-13+ Mini-Circuits
R16, R14, R58, C31
REFIN input path. R14 provides a broadband 50 Ω
termination followed by C31, which provides the
ac coupling into REFIN. R16 provides an external
connectivity to the MUXOUT feature described in
Register 4. R58 provides option for connectivity to
the P1-6 line of a 9-pin D-sub connector for dc
measurements.
R14 = 49.9 Ω (0402),
R16 = 0 Ω (0402),
R58 = open (0402),
C31 = 1 nF (0603)
R2, R9, R10, R11, R12, R37, R38, R59,
R60, C4, C14, C15, C13
Loop filter component options. A variety of loop filter
topologies is supported using component
R12, R37, R38 = 0 Ω (0402),
R59 = open (0402),
R9, R60 = 10 kΩ (0402),
R10 = 3 kΩ (0402),
R2, R11 = open (0402),
C13 = 6.8 pF (0402),
C4, C14 = 22 pF (0402),
C15 = 2.7 nF (1206)
placements C4, C13, C14, C15, R9, R10, and R60. R38
and R59 provide connectivity options to numerous
test points for engineering evaluation purposes. R2
provides resistor programmability of the charge
pump current (see Register 4 description). R37
connects the charge pump output to the loop filter.
R12 references the loop filter to the VCO_LDO. Default
values on board provide a loop filter bandwidth of
roughly 130 kHz using a 26 MHz PFD frequency.
R3, R4, R5, R21, R22, R23, R39, R40,
R41, R42, R43, R44, R45, R46, R47,
R48, C29, C30, T2, T3, P2, P3
IF I/Q output paths. The T2 and T3 baluns provide a
R4, R5, R21, R22, = 0 Ω (0402),
9:1 impedance transformation; therefore, with a 50 Ω
R40, R43, R45, R46 = 0 Ω (0402),
load on the single-ended IOUT/QOUT side, the center
R47, R48 = 0 Ω (0402),
tap side of the balun presents a differential 450 Ω
R3, R23, R39, R41, R42, R44 = open (0402),
to the ADRF6806. The center taps of the baluns are
C29, C30, = 0.1 µF (0402),
ac grounded through C29 and C30. The baluns create
T2, T3 = TCM9-1+ Mini-Circuits,
a differential-to-single-ended conversion for ease
of testing and use, but an option to have straight
differential outputs is achieved via populating R3,
R39, R23, and R42 with 0 Ω resistors and removing
R4, R5, R21, and R22. P2 and P3 are differential
measurement test points (not to be used as jumpers).
P2, P3 = Samtec SSW-102-01-G-S
R28
RF input interface. R28 provides the single-ended
RF input path to the on-chip RF input balun.
R28 = 0 Ω (0402)
R30, R35, R50, R51, R52, R57, C32,
C33, C34, P1
Serial port interface. A 9-pin D-sub connector (P1)
is provided for connecting to a host PC or control
hardware. Optional RC filters can be installed on
the CLK, DATA, and LE lines to filter the PC signals
through R50 to R52 and C32 to C34. CLK, DATA, and
LE signals can be observed via test points for debug
purposes. R58 provides a connection to the MUXOUT
for sensing lock detect through the P1 connector.
R30, R35, R57 = 0 Ω (0402),
R50, R51, R52 = open (0402),
C32, C33, C34 = open (0402),
P1 = Tyco Electronics 5747840-3
R33, R55, R56, S1
LO select interface. The LOSEL pin, in combination
with the LDRV and LXL bits in Register 5, controls
R33 = 0 Ω (0402),
R55, R56 = 10 kΩ (0402),
whether the LOP and LON pins operate as inputs or
S1 = Samtec TSW-103-08-G-S
outputs. A detailed description of how the LOSEL pin,
LDRV bit, and the LXL bit work together to control
LOSEL pin description. Using the S1 switch, the
user can pull LOSEL to a logic high (V
CC
/2) or a logic
low (ground). Resistors R55 and R56 form a resistor
divider to provide a logic high of V
CC
/2. LO select
can also be controlled through Pin 9 of J1. The 0 Ω
jumper, R33, must be installed to control LOSEL via J1.
Rev. A | Page 26 of 34
Data Sheet
Component
Function
Default Condition
J1
Engineering test points and external control. J1 is a
J1 = Molex Connector Corp. 10-89-7102
10-pin connector connected to various important
points on the evaluation board that the user can
measure or force voltages upon.
R19, R20, R34, R53, R54, S2
Provides ground connection for Pin 16.
R20, R53 = 0 Ω (0402),
R34, R54 = open (0402),
R19 = open, S2 = open
Rev. A | Page 27 of 34
Data Sheet
ADRF6801 SOFTWARE
The ADRF6801 evaluation board can be controlled from PCs
using a USB adapter board, which is also available from Analog
Devices, Inc. The USB adapter evaluation documentation and
Attempting to program
Ref Input Frequency
,
PFD Frequency
,
VCO Frequency (2×LO)
,
LO Frequency
, or other values in
RF
Using
Synth Form
, the user can specify values for
Local Oscillator
Frequency (MHz)
and
External Reference Frequency (MHz)
.
The user can also enable the LO output buffer and divider options
from this menu. After setting the desired values, it is important
to click
Upload all registers
for the new setting to take effect.
The software allows the user to configure the ADRF6801 for
various modes of operation. The internal synthesizer is controlled
by clicking on any of the numeric values listed in
RF Section
.
Figure 46. Evaluation Board Software Main Window
Rev. A | Page 28 of 34
Data Sheet
CHARACTERIZATION SETUPS
setups used extensively for the ADRF6801. The setup shown in
Figure 48
was used to do the bulk of the testing. An automated
Agilent VEE program was used to control the equipment over the
IEEE bus. This setup was used to measure gain, input P1dB, output
P1dB, input IP2, input IP3, IQ gain mismatch, IQ quadrature
accuracy, and supply current. The evaluation board was used to
perform the characterization with a Mini-Circuits TCM9-1+ balun
on each of the I and Q outputs. When using the TCM9-1+ balun
below 5 MHz (the specified 1 dB low frequency corner of the
balun), distortion performance degrades; however, this is not
the ADRF6801 degrading, merely the low frequency corner of
the balun introducing distortion effects. Through this balun,
the 9-to-1 impedance transformation effectively presented a 450 Ω
differential load at each of the I and Q channels. The losses of the
output baluns were de-embedded from all measurements.
To
d
o phase noise and reference spur measurements, the setup
baseband output (I or Q) at a baseband carrier frequency of
50 MHz. The baseband carrier of 50 MHz was chosen to allow
phase noise measurements to be taken at frequencies of up to
20 MHz offset from the carrier. The noise figure was measured
of 10 MHz.
Rev. A | Page 30 of 34
Data Sheet
IEEE
R&S SMA100
SIGNAL GENERATOR
IEEE
3dB
RF1
MINI-CIRCUITS
ZHL-42W AMPLIFIER
(SUPPLIED WITH +15V dc
FOR OPERATION)
R&S SMT03 SIGNAL GENERATOR
AGILENT 11636A
POWER DIVIDER
(USED AS COMBINER)
3dB
REF
3dB
RF2
IEEE
3dB
RF
R&S SMT03 SIGNAL GENERATOR
IEEE
CH A
CH B
RF SWITCH MATRIX
HP 8508A
VECTOR
VOLTMETER
IEEE
I CH
6dB
RF
Q CH
6dB
AGILENT MXA
SPECTRUM ANALYZER
3dB
IEEE
AGILENT 34980A
MULTIFUNCTION
SWITCH
(WITH 34950 AND 2×
34921 MODULES)
ADRF6801
EVALUATION BOARD
AGILENT DMM
(FOR I
MEAS.)
10-PIN
CONNECTION
(+5V V
SUPPLY
IEEE
,
POS
DC MEASURE)
AGILENT E3631A
POWER SUPPLY
6dB
9-PIN D-SUB CONNECTION
(VCO AND PLL PROGRAMMING)
REF
IEEE
IEEE
Figure 48. General Characterization Setup
Rev. A | Page 31 of 34
Data Sheet
IEEE
AGILENT 8665B
LOW NOISE SYN
SIGNAL GENERATOR
REF
RF1
AGILENT 346B
NOISE SOURCE
3dB
RF
RF SWITCH MATRIX
10MHz
IEEE
LOW-PASS FILTER
AGILENT N8974A
NOISE FIGURE ANALYZER
I CH
6dB
RF
Q CH
6dB
AGILENT DMM
(FOR I
MEAS.)
SUPPLY
3dB
IEEE
AGILENT 34980A
MULTIFUNCTION
SWITCH
(WITH 34950 AND 2×
34921 MODULES)
ADRF6801
EVALUATION BOARD
10-PIN
CONNECTION
(+5V V
1,
IEEE
POS
DC MEASURE)
AGILENT E3631A
POWER SUPPLY
6dB
9-PIN D-SUB CONNECTION
(VCO AND PLL PROGRAMMING)
REF
IEEE
IEEE
Figure 49. Noise Figure Characterization Setup
Rev. A | Page 32 of 34
Data Sheet
IEEE
R&S SMA100
SIGNAL GENERATOR
IEEE
REF
RF1
R&S SMA100
SIGNAL GENERATOR
IEEE
100MHz
LOW-PASS FILTER
3dB
RF
AGILENT E5052 SIGNAL SOURCE
ANALYZER
RF SWITCH MATRIX
IEEE
AGILENT MXA
SPECTRUM ANALYZER
I CH
6dB
RF
Q CH
6dB
AGILENT DMM
(FOR I
MEAS.)
SUPPLY
3dB
IEEE
AGILENT 34980A
MULTIFUNCTION
SWITCH
(WITH 34950 AND 2×
34921 MODULES)
ADRF6801
EVALUATION BOARD
10-PIN
CONNECTION
(+5V V
1,
IEEE
POS
DC MEASURE)
AGILENT E3631A
POWER SUPPLY
6dB
9-PIN D-SUB CONNECTION
(VCO AND PLL PROGRAMMING)
IEEE
REF
IEEE
IEEE
Figure 50. Phase Noise Characterization Setup
Rev. A | Page 33 of 34
Data Sheet
OUTLINE DIMENSIONS
6.10
6.00 SQ
5.90
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
31
30
40
1
5.85
5.75 SQ
5.65
0.50
BSC
PIN 1
INDICATOR
4.25
4.10 SQ
3.95
EXPOSED
PAD
(BOTTOM VIEW)
10
11
21
20
0.50
0.40
0.30
0.20 MIN
TOP VIEW
4.50 REF
0.80 MAX
0.65 TYP
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
12° MAX
1.00
0.85
0.80
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
0.30
0.23
0.18
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
Figure 51. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
6 mm × 6 mm Body, Very Thin Quad
(CP-40-1)
Dimensions shown in millimeters
ORDERING GUIDE
Ordering
Quantity
Model
1
Temperature Range
Package Description
Package Option
CP-40-1
ADRF6801ACPZ-R7
ADRF6801-EVALZ
−40°C to +85°C
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
750
1
Z = RoHS Compliant Part.
©2011–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09576-0-6/18(A)
Rev. A | Page 34 of 34
