Analog-Devices-Inc–Maxim-Integrated-MAX2830ETM-T

Part #	Analog-Devices-Inc–Maxim-Integrated-MAX2830ETM-T
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EVALUATION KIT AVAILABLE

MAX2830

2.4GHz to 2.5GHz 802.11g/b RF

ansceive

, PA,

and Rx/Tx/Antenna Diversity Switch

General Description

Features

2.4GHz to 2.5GHz ISM Band Operation

IEEE 802.11g/b Compatible (54Mbps OFDM and

The MAX2830 direct conversion, zero-IF, RF transceiver

is designed specifically for 2.4GHz to 2.5GHz 802.11g/b

WLAN applications. The MAX2830 completely integrates

all circuitry required to implement the RF transceiver

function, providing an RF power amplifier (PA), an Rx/Tx

and antenna diversity switch, RF-to-baseband receive

path, baseband-to-RF transmit path, voltage-controlled

oscillator (VCO), frequency synthesizer, crystal oscillator,

and baseband/control interface. The MAX2830 includes

a fast-settling sigma-delta RF synthesizer with smaller

than 20Hz frequency steps and a digitally tuned crystal

oscillator allowing use of a low-cost crystal. No I/Q cali-

bration is required; however, the device also integrates

on-chip DC-offset cancellation and I/Q errors and carrier

leakage-detection circuits for improved performance.

Only an RF bandpass filter (BPF), crystal, a pair of

baluns, and a small number of passive components are

needed to form a complete 802.11g/b WLAN RF front-

end solution.

11Mbps CCK)

Complete RF Transceiver, PA, Rx/Tx and Antenna

Diversity Switch, and Crystal Oscillator

Best-in-Class Transceiver Performance

62mA Receiver Current

3.3dB Rx Noise Figure

-75dBm Rx Sensitivity (54Mbps OFDM)

No I/Q Calibration Required

0.1dB/0.35° Rx I/Q Gain/Phase Imbalance

33dB RF and 62dB Baseband Gain Control

Range

60dB Range Analog RSSI per RF Gain Setting

Fast Rx I/Q DC-Offset Settling

Programmable Baseband Lowpass Filter

20-Bit Sigma-Delta Fractional-N PLL with

< 20Hz Step Size

The MAX2830 completely eliminates the need for an

external SAW filter by implementing on-chip monolithic fil-

ters for both the receiver and transmitter. The baseband

filters are optimized to meet the IEEE 802.11g standard

and proprietary turbo modes up to 40MHz channel band-

width. These devices are suitable for the full range of

802.11g OFDM data rates (6Mbps to 54Mbps) and

802.11b QPSK and CCK data rates (1Mbps to 11Mbps).

The ICs are available in a small, 48-pin TQFN package

measuring only 7mm x 7mm x 0.8mm.

Digitally Tuned Crystal Oscillator

+17.1dBm Transmit Power (5.6% EVM with

54Mbps OFDM)

31dB Tx Gain Control Range

Integrated Power Detector

Fully Integrated RF Input and Output

Matching and DC Blocking

Serial or Parallel Gain-Control Interface

> 40dB Tx Sideband Suppression Without

Calibration

Applications

Rx/Tx I/Q Error Detection

Wi-Fi, PDA, VOIP, and Cellular Handsets

Wireless Speakers and Headphones

General 2.4GHz ISM Radios

Transceiver Operates from +2.7V to +3.6V

PA Operates from +2.7V to +4.2V

Low-Power Shutdown Mode

Small 48-Pin TQFN Package

(7mm x 7mm x 0.8mm)

Selector Guide

Ordering Information

PART

INTEGRATED PA

INTEGRATED SWITCH

PART

TEMP RANGE

PIN-PACKAGE

MAX2830

MAX2831

MAX2832

Yes

MAX2830ETM+T

-40°C to +85°C

48 TQFN-EP*

EP = Exposed paddle.

Denotes a lead(Pb)-free/RoHS-compliant package.

T = Tape and reel.

Pin Configuration appears at end of data sheet.

For pricing, delivery, and ordering information, please contact Maxim Direct

at 1-888-629-4642, or visit Maxim’s website at www.maxim

integrated

.com.

19-0774; Rev 2; 3/11

MAX2830

2.4GHz to 2.5GHz 802.11g/b RF

ansceive

, PA,

and Rx/Tx/Antenna Diversity Switch

ABSOLUTE MAXIMUM RATINGS

, V

, and ANT

o GND ………………-0.3V to +4.5V

RF Input Powe

……………………………………………………..+10dBm

CCTXPA CCPA

, V

Continuous Power Dissipation (T

= +70°C)

CCLNA CCTXMX CCPLL CCCP CCXTAL CCVCO

, V

, and V

_ to GND…-0.3V to +3.9V

48-Pin TQFN (derates 27.8mW/°C above +70°C) ………2.22W

Operating Temperature Range ………………………-40°C to +85°C

Junction Temperatur

……………………………………………..+150°C

Storage Temperature Rang

……………………….-65°C to +160°C

Lead Temperature (soldering, 10s) ……………………………+300°C

Soldering Temperature (reflow) …………………………………+260°C

CCRXVGA CCRXFL

CCRXMX

B6, B7, B3, B2,

SHDN

, B5,

, SCLK, DIN, B1, TUNE, B4,

ANTSEL, TXBBI_, TXBBQ_, RXHP, RXTX, RXBBI_, RXBBQ_,

RSSI, BYPASS,

CPOUT, LD, CLOCKOUT, XTAL,

CTUNE to

GND ………………..-0.3V to (Operating V

RXBBI_, RXBBQ_, RSSI, BYPASS, CPOUT, LD, CLOCKOUT

+ 0.3V)

Short-Circuit Duration …………………………………………………10s

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

CAUTION!

ESD SENSITIVE DEVICE

DC ELECTRICAL CHARACTERISTICS

= 2.7V to 4.2V, T

= -40°C to +85°C, Rx set to the maximum gain.

CCTXPA A

(MAX2830 EV kit, V

= 2.7V to 3.6V, V

= V

CC_

CCPA

high, RXHP = SCLK = DIN = ANTSEL = low, RSSI and clock output buffer are off, no signal at RF inputs, all RF inputs and outputs

terminated into 50

Ω

, receiver baseband outputs are open. 100mV

differential I and Q signals (54Mbps IEEE 802.11g OFDM)

RMS

applied to I/Q baseband inputs of transmitter in transmit mode, f

= 40MHz, and registers set to recommended settings and corre-

REF

sponding test mode, unless otherwise noted. Typical values are at V

= 2.8V, V

= 3.3V, and T

= +25°C, LO frequency =

CCPA A

2.437GHz, unless otherwise noted. RF inputs/outputs specifications are referenced to device pins and do not include 1dB loss from

EV kit PCB, balun, and SMA connectors.) (Note 1)

PARAMETERS

Supply Voltage

CONDITIONS

MIN

2.7

TYP

MAX

3.6

UNITS

CC_

, V

2.7

4.2

CCPA CCTXPA

Shutdown mode,

B7: B1 = 0000000,

reference oscillator not

applied

= +25°C

µA

= +25°C

Standby mode

Rx mode

= -40°C to +85°C

= +25°C

Supply Current

= -40°C to +85°C

Tx mode, T

= +25°C,

Transmit section

PA, P

= +17.1dBm

104

= 2.8V, V

CCPA

212

OUT

3.3V (Note 2)

Rx calibration mode

Tx calibration mode

= +25°C

101

Rx I/Q Output Common-Mode

Voltage

= +25°C at default common-mode setting

0.94

0.9

1.2

1.37

= -40°C (relative to T

= +25°C)

-17

Rx I/Q Output Common-Mode

Voltage Variation

= +85°C (relative to T

= +25°C)

Tx Baseband Input Common-

Mode Voltage Operating Range

DC-coupled

1.3

Tx Baseband

put Bias Current

Source current

µA

Maxim Integrated

MAX2830

2.4GHz to 2.5GHz 802.11g/b RF

ansceive

, PA,

and Rx/Tx/Antenna Diversity Switch

DC ELECTRICAL CHARACTERISTICS (continued)

= 2.7V to 4.2V, T

= -40°C to +85°C, Rx set to the maximum gain.

CCTXPA A

(MAX2830 EV kit, V

= 2.7V to 3.6V, V

= V

CC_

CCPA

high, RXHP = SCLK = DIN = ANTSEL = low, RSSI and clock output buffer are off, no signal at RF inputs, all RF inputs and outputs

terminated into 50

Ω

, receiver baseband outputs are open. 100mV

differential I and Q signals (54Mbps IEEE 802.11g OFDM)

RMS

applied to I/Q baseband inputs of transmitter in transmit mode, f

= 40MHz, and registers set to recommended settings and corre-

REF

sponding test mode, unless otherwise noted. Typical values are at V

= 2.8V, V

= 3.3V, and T

= +25°C, LO frequency =

CCPA A

2.437GHz, unless otherwise noted. RF inputs/outputs specifications are referenced to device pins and do not include 1dB loss from

EV kit PCB, balun, and SMA connectors.) (Note 1)

PARAMETERS

CONDITIONS

MIN

TYP

MAX

UNITS

LOGIC INPUTS:

SHDN

, RXTX, SCLK, DIN,

, B7:B1, RXHP, ANTSEL

0.4

–

Digital Input-Voltage High, V

Digital Input-Voltage Low, V

0.4

Digital Input-Current High, I

-1

µA

Digital Input-Current Low, I

LOGIC OUTPUTS: LD, CLOCKOUT

0.4

–

Digital Output-Voltage High, V

Sourcing 100µA

Sinking 100µA

Digital Output-Voltage Low, V

0.4

AC ELECTRICAL CHARACTERISTICS—Rx Mode

= 3.3V, T

=+25°C, f

= 2.439GHz, f

= 2.437GHz; receiver baseband I/Q out-

CCTXPA A

RF LO

(MAX2830 EV kit, V

= 2.8V, V

= V

CC_

CCPA

puts at 112 mV

(-19dBV), f

= 40MHz,

SHDN

= high, RXTX = SCLK = DIN = low, with power matching for the differential

RMS

REF

RF pins using the typical applications and registers set to default settings and corresponding test mode, unless otherwise noted.

Unmodulated single-tone RF input signal is used with specifications that normally apply over the entire operating conditions, unless

otherwise indicated. RF inputs/outputs specifications are referenced to device pins and do not include 1dB loss from EV kit PCB,

balun, and SMA connectors.) (Note 1)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

GHz

RECEIVER SECTION: LNA RF INPUT-TO-BASEBAND I/Q OUTPUTS

RF Input Frequency Range

High RF gain

2.4

2.5

RF Input Return Loss (ANT1)

RF Input Return Loss (ANT2)

Mid RF gain

Low RF gain

High RF gain

Mid RF gain

Low RF gain

= +25°C

Maximum gain, B7:B1 =

1111111

= -40°C to +85°C

Total Voltage Gain (ANT1)

Total Voltage Gain (ANT2)

Minimum gain, B7:B1 =

0000000

= +25°C

Maximum gain, B7:B1 =

1111111

Minimum gain, B7:B1 =

0000000

Maxim Integrated

MAX2830

2.4GHz to 2.5GHz 802.11g/b RF

ansceive

, PA,

and Rx/Tx/Antenna Diversity Switch

AC ELECTRICAL CHARACTERISTICS—Rx Mode (continued)

= 3.3V, T

=+25°C, f

= 2.439GHz, f

= 2.437GHz; receiver baseband I/Q out-

CCTXPA A

RF LO

(MAX2830 EV kit, V

= 2.8V, V

= V

CC_

CCPA

puts at 112 mV

(-19dBV), f

= 40MHz,

SHDN

= high, RXTX = SCLK = DIN = low, with power matching for the differential

RMS

REF

RF pins using the typical applications and registers set to default settings and corresponding test mode, unless otherwise noted.

Unmodulated single-tone RF input signal is used with specifications that normally apply over the entire operating conditions, unless

otherwise indicated. RF inputs/outputs specifications are referenced to device pins and do not include 1dB loss from EV kit PCB,

balun, and SMA connectors.) (Note 1)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

From high-gain mode (B7:B6 = 11) to medium-gain

mode (B7:B6 = 10)

-17

RF Gain Steps (Note 3)

From high-gain mode (B7:B6 = 11) to low-gain mode

(B7:B6 = 0X)

-33.5

0.2

Gain change from high gain to medium gain, high gain to

low, or medium gain to low gain; gain settling to within

2dB of steady state; RXHP = 1

RF Gain-Change Settling Time

Baseband Gain Range

µs

From maximum baseband gain (B5:B1 = 11111) to

minimum baseband gain (B5:B1 = 00000)

Voltage gain = maximum with B7:B6 = 11

Voltage gain = 50dB with B7:B6 = 11

Voltage gain = 45dB with B7:B6 = 10

Voltage gain = 15dB with B7:B6 = 0X

Voltage gain = maximum with B7:B6 = 11

Voltage gain = 50dB with B7:B6 = 11

Voltage gain = 45dB with B7:B6 = 10

Voltage gain = 15dB with B7:B6 = 0X

3.3

3.8

16.7

34.7

4.0

4.5

17.4

35.3

-41

-24

-6

DSB Noise Figure (ANT1)

DSB Noise Figure (ANT2)

B7:B6 = 11

B7:B6 = 10

B7:B6 = 0X

-19dBV

output EVM degrades to

baseband

RMS

In-Band Compression Point

Based on EVM

dBm

In-Band Output P-1dB

Voltage gain = 90dB, with B7:B6 = 11

B7:B6 = 11

2.5

-12

-4

P-P

Out-of-Band Input IP3 (Note 4)

dBm

B7:B6 = 10

B7:B6 = 0X

I/Q Phase Error

variation (without calibration)

Minimum differential resistance

Maximum differential capacitance

0.35

0.1

Degrees

I/Q Gain Imbalance

Ω

RX I/Q Output Load Impedance

(R || C)

Tx-to-Rx Conversion Gain for Rx

I/Q Calibration

For receiver gain, B7:B1 = 1101111 (Note 5)

0.5

0.1

µs

Gain change from B5:B1 = 10111 to B5:B1 = 00111; gain

settling to within

2dB of steady state

Baseband VGA Settling Time

After switching RXHP to logic 0 from initial logic 1, during

ideal short sequence data at -55dBm input in AWGN

channel, for -19dBV output; normalized to RMS signal on

I and Q outputs; transition point varied from 0 to 0.8µs in

steps of 0.1µs

I/Q Output DC Step when RXHP

Transitions from 1 to 0 in

Presence of 802.11g Short

Sequence

-5

dBc

Maxim Integrated

MAX2830

2.4GHz to 2.5GHz 802.11g/b RF

ansceive

, PA,

and Rx/Tx/Antenna Diversity Switch

AC ELECTRICAL CHARACTERISTICS—Rx Mode (continued)

= 3.3V, T

=+25°C, f

= 2.439GHz, f

= 2.437GHz; receiver baseband I/Q out-

CCTXPA A

RF LO

(MAX2830 EV kit, V

= 2.8V, V

= V

CC_

CCPA

puts at 112 mV

(-19dBV), f

= 40MHz,

SHDN

= high, RXTX = SCLK = DIN = low, with power matching for the differential

RMS

REF

RF pins using the typical applications and registers set to default settings and corresponding test mode, unless otherwise noted.

Unmodulated single-tone RF input signal is used with specifications that normally apply over the entire operating conditions, unless

otherwise indicated. RF inputs/outputs specifications are referenced to device pins and do not include 1dB loss from EV kit PCB,

balun, and SMA connectors.) (Note 1)

PARAMETER

I/Q Output DC Droop

I/Q Static DC Offset

CONDITIONS

MIN

TYP

MAX

UNITS

V/s

After switching RXHP to 0, D13:D12, Register 7

(A3:A0 = 0111)

RXHP = 1, B7:B1 = 1101110, 1

variation

Spurious Signal Emissions from

LNA input

RF = 1GHz to 26.5GHz

-51

dBm

ANT1 to receiver (in ANT2 mode)

ANT2 to receiver (in ANT1 mode)

ANT to Receiver Isolation

RECEIVER BASEBAND FILTERS

Gain Ripple in Passband

10kHz to 8.5MHz at baseband

At 8.5MHz

1.3

P-P

Group-Delay Ripple in Passband

P-P

3.2

At 15MHz

Baseband Filter Rejection

(Nominal Mode)

At 20MHz

At > 40MHz

RSSI

RSSI Minimum Output Voltage

RSSI Maximum Output Voltage

RSSI Slope

≥

10k

Ω

|| 5pF

≥

10k

Ω

|| 5pF

0.4

2.4

LOAD

mV/dB

+32dB signal step

-32dB signal step

200

600

To within 3dB of steady

state

RSSI Output Settling Time

Maxim Integrated

MAX2830

2.4GHz to 2.5GHz 802.11g/b RF

ansceive

, PA,

and Rx/Tx/Antenna Diversity Switch

AC ELECTRICAL CHARACTERISTICS—Tx Mode

(MAX2830 EV kit, V

= 2.8V, V

= V

= 3.3V, T

= +25°C, f

= 2.439GHz , f

= 2.437GHz. f

= 40MHz,

SHDN

CC_

CCPA

CCTXPA

REF

RXTX =

= ANTSEL = high, and SCLK = DIN = low, with power matching for the differential RF pins using the typical applications

circuit. 100mV

sine and cosine signal (or 100mV

54Mbps IEEE 802.11g I/Q signals wherever OFDM is mentioned) applied to

RMS

baseband I/Q inputs of transmitter (differential DC-coupled). Registers set to recommend settings and corresponding test mode,

unless otherwise noted. RF inputs/outputs specifications are referenced to device pins and do not include 1dB loss from EV kit PCB,

balun, and SMA connectors.) (Note 1)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

TRANSMIT SECTION: Tx BASEBAND I/Q INPUTS TO RF OUTPUTS

RF Output Frequency Range

2.4

2.5

GHz

Output power adjusted to

meet 5.6%EVM, and

spectral mask

54Mbps 802.11g OFDM

signal

17.1

20.3

Output Power

dBm

Output power adjusted to

meet spectral mask

6Mbits, OFDM, I/Q signals

B6:B1 = 000000 to 111000

Gain Control Range

Unwanted Sideband Suppression

Without I/Q calibration, B6:B1 = 100001

-42

dBc

Carrier Leakage at Center

Without DC offset correction

Frequency of Channel

-30

dBc

1/3 x f

-67

-36

-47

-64

-42

-65

-55

-27

-54

-15

< 1GHz

> 1GHz

2/3 x f

4/3 x f

5/3 x f

8/3 x f

Transmitter Spurious Signal

Emissions

B6:B1 = 111000,

OFDM signal

dBm/

MHz

2 x f

3 x f

RF Output Return Loss

Off-chip balun and single ended

Minimum differential resistance

Maximum differential capacitance

Ω

Tx I/Q Input Load Impedance

(R || C)

0.7

Baseband -3dB Corner

Frequency

D1:D0 = 01, Register 8

(A3:A0 = 1000)

Nominal mode

MHz

Baseband Filter Rejection

At 30MHz, in nominal mode

Minimum Power-Detector Output

Voltage

Short sequence transmitter power = +10dBm

Short sequence transmitter power = +20dBm

0.35

Maximum Power-Detector Output

Voltage

1.2

0.3

RF Power-Detector Response Time

µs

Maxim Integrated

MAX2830

2.4GHz to 2.5GHz 802.11g/b RF

ansceive

, PA,

and Rx/Tx/Antenna Diversity Switch

AC ELECTRICAL CHARACTERISTICS—Tx Mode (continued)

(MAX2830 EV kit, V

= 2.8V, V

= V

= 3.3V, T

= +25°C, f

= 2.439GHz , f

= 2.437GHz. f

= 40MHz,

SHDN

CC_

CCPA

CCTXPA

REF

RXTX =

= ANTSEL = high, and SCLK = DIN = low, with power matching for the differential RF pins using the typical applications

circuit. 100mV

sine and cosine signal (or 100mV

54Mbps IEEE 802.11g I/Q signals wherever OFDM is mentioned) applied to

RMS

baseband I/Q inputs of transmitter (differential DC-coupled). Registers set to recommend settings and corresponding test mode,

unless otherwise noted. RF inputs/outputs specifications are referenced to device pins and do not include 1dB loss from EV kit PCB,

balun, and SMA connectors.) (Note 1)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

TRANSMITTER LO LEAKAGE AND I/Q CALIBRATION USING LO LEAKAGE AND SIDEBAND DETECTOR

(see the

Rx/Tx Calibration Mode

section)

Tx BASEBAND I/Q INPUTS TO RECEIVER OUTPUTS

Output at 1 x f

(for LO

TONE

leakage = -29dBc),

= 2MHz, 100mV

-34

-44

Calibration register,

D12:D11 = 00,

A3:A0 = 0110

TONE

RMS

LO Leakage and Sideband

Detector Output

dBV

RMS

Output at 2 x f

(for LO

TONE

leakage = -240dBc),

= 2MHz, 100mV

TONE

RMS

Amplifier Gain Range

D12:D11 = 00 to D12:D11 = 11, A3:A0 = 0110

MHz

Lower -3dB Corner Frequency

Maxim Integrated

MAX2830

2.4GHz to 2.5GHz 802.11g/b RF

ansceive

, PA,

and Rx/Tx/Antenna Diversity Switch

AC ELECTRICAL CHARACTERISTICS—Frequency Synthesizer

= 40MHz,

SHDN

= high, SCLK =

REF

(MAX2830 EV kit, V

= 2.7V, V

= V

= 3.3V, T

= +25°C, f

= 2.437GHz, f

CC_

CCPA

CCTXPA

DIN = low, PLL loop bandwidth = 150kHz, and T

= +25°C, unless otherwise noted.) (Note 1)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

GHz

FREQUENCY SYNTHESIZER

RF Channel Center Frequency

2.4

2.5

Channel Center Frequency

Programming Minimum Step Size

Charge-Pump Comparison

Frequency

MHz

Reference Frequency Range

Reference Frequency Input

Levels

AC-coupled to XTAL pin

800

P-P

Resistance (XTAL)

Capacitance (XTAL)

Ω

Reference Frequency Input

Impedance (R || C)

= 1kHz

-86

-94

-110

-120

OFFSET

= 10kHz

= 100kHz

= 1MHz

= 10MHz

Closed-Loop Phase Noise

dBc/Hz

Closed-Loop Integrated Phase

Noise

RMS phase jitter; integrate from 10kHz to 10MHz offset

0.9

Degrees

Charge-Pump Output Current

Reference Spurs

-55

20MHz offset

dBc

3µs to 9µs

> 9µs

Measured from Tx-Rx or Rx-Tx

transition

VCO Frequency Error

kHz

VOLTAGE-CONTROLLED OSCILLATOR

Pushing

Referred to 2400MHz LO, V

varies by 0.3V

210

103

kHz

= 0.5V

= 2.2V

TUNE

LO Tuning Gain

MHz/V

Maxim Integrated

MAX2830

2.4GHz to 2.5GHz 802.11g/b RF

ansceive

, PA,

and Rx/Tx/Antenna Diversity Switch

AC ELECTRICAL CHARACTERISTICS—Miscellaneous Blocks

= 40MHz,

SHDN

= high, SCLK = DIN = low,

REF

(MAX2830 EV kit, V

= 2.8V, V

= V

= 3.3V, f

= 2.437GHZ, f

CC_

CCPA

CCTXPA

and T

= +25°C, unless otherwise noted.) (Note 1)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

CRYSTAL OSCILLATOR

Maximum capacitance, A3:A0 = 1110, D6:D0 = 1111111

Minimum capacitance, A3:A0 = 1110, D6:D0 = 0000000

15.4

0.5

On-Chip Tuning Capacitance

Range

On-Chip Tuning Capacitance

Step Size

0.12

ON-CHIP TEMPERATURE SENSOR

= -40°C

= +25°C

= +85°C

0.35

Output Voltage

A3:A0 = 1000, D9:D8 = 01

1.6

AC ELECTRICAL CHARACTERISTICS—Timing

(MAX2830 EV kit, V

= 2.8V, V

= V

= 3.3V, T

=+25°C, f

= 2.437GHz, f

= 40MHz,

SHDN

= high, SCLK =

CC_

CCPA

CCTXPA

REF

DIN = low, PLL loop bandwidth = 150kHz, and T

= +25°C, unless otherwise noted.) (Note 1)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

SYSTEM TIMING (see Figure 3)

From

SHDN

rising edge to LO settled within 1kHz using

external reference frequency input

Turn-On Time

µs

Crystal Oscillator Turn-On Time

Channel Switching Time

90% of final output amplitude level

µs

Loop BW = 150kHz, f

= 2.5GHz to 2.4GHz

Measured from Tx or Rx

Rx to Tx

enable rising edge; signal

settling to within

2dB of

Rx/Tx Turnaround Time

µs

Tx to Rx, RXHP = 1

steady state

Tx Turn-On Time (from Standby

Mode)

From Tx-enable active rising edge; signal settling to

within 2dB

of steady state

1.5

µs

Tx Turn-Off Time (from Standby

Mode)

From Tx-enable inactive rising edge

Rx Turn-On Time (from Standby

Mode)

From Rx-enable active rising edge; signal settling to

within 2dB

of steady state

1.9

0.1

Rx Turn-Off Time (from Standby

Mode)

From Rx-enable inactive rising edge

Maxim Integrated

MAX2830

2.4GHz to 2.5GHz 802.11g/b RF

ansceive

, PA,

and Rx/Tx/Antenna Diversity Switch

AC ELECTRICAL CHARACTERISTICS—Timing (continued)

(MAX2830 EV kit, V

= 2.8V, V

= V

= 3.3V, T

=+25°C, f

= 2.437GHz, f

= 40MHz,

SHDN

= high, SCLK =

CC_

CCPA

CCTXPA

REF

DIN = low, PLL loop bandwidth = 150kHz, and T

= +25°C, unless otherwise noted.) (Note 1)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

3-WIRE SERIAL-INTERFACE TIMING (see Figure 2)

SCLK Rising Edge to

Falling

Edge Wait Time, t

CSO

Falling Edge of

to Rising

Edge of First SCLK Time, t

CSS

DIN to SCLK Setup Time, t

DIN to SCLK Hold Time, t

SCLK Pulse-Width High, t

SCLK Pulse-Width Low, t

Last Rising Edge of SCLK to

Rising Edge of

or Clock to

Load Enable Setup Time, t

CSH

High Pulse Width, t

CSW

Time Between the Rising Edge of

and the Next Rising Edge of

SCLK, t

CS1

Clock Frequency, f

MHz

CLK

Rise Time, t

Fall Time, t

Note 1:

Min and max limits are guaranteed by test above T

= +25°C and guaranteed by design and characterization at T

= -40°C.

The power-on register settings are not production tested. Recommended register setting must be loaded after V

is supplied.

Note 2:

Guaranteed by design and characterization.

Note 3:

The nominal part-to-part variation of the RF gain step is

1dB.

Note 4:

Two tones at +25MHz and +48MHz offset with -35dBm/tone. Measure IM3 at 2MHz.

Note 5:

Tx I/Q inputs = 100mV

RMS

Maxim Integrated

MAX2830

2.4GHz to 2.5GHz 802.11g/b RF

ansceive

, PA,

and Rx/Tx/Antenna Diversity Switch

pical Operating Characteristics

(MAX2830 EV kit, V

= 2.8V, V

= V

= 3.3V, T

= +25°C, f

= 2.437GHz, f

= 40MHz,

SHDN

= high, RXHP =

REF

CC_

CCPA

CCTXPA

SCLK = DIN = low.)

NOISE FIGURE

vs. BASEBAND GAIN SETTINGS

Rx VOLTAGE GAIN

vs. BASEBAND GAIN SETTING

100

Rx I

vs. V

LNA = HIGH GAIN

LNA = LOW GAIN

= +85

LNA = MEDIUM GAIN

LNA = HIGH GAIN

= +25

LNA = MEDIUM GAIN

= -40

LNA = LOW GAIN

2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6

(V)

8 10

12 14 16 18 20 22 24 26 28 30 32

GAIN SETTINGS

8 10

12 14 16 18 20 22 24 26 28 30 32

GAIN SETTINGS

Rx EVM vs. V

OUT

Rx EVM vs. P

Rx IN-BAND OUTPUT P – 1dB vs. GAIN

3.0

2.5

2.0

1.5

1.0

0.5

LNA = LOW GAIN

= -50dBm

LNA = HIGH GAIN

-1

LNA =

MEDIUM GAIN

-2

LNA MEDIUM/HIGH-

GAIN SWITCH POINT

-3

-4

-5

-6

-7

LNA MEDIUM/LOW-

GAIN SWITCH POINT

-29 -27 -25 -23 -21 -19 -17 -15 -13 -11

-9

(dBV

-80 -70 -60 -50 -40 -30 -20 -10

(dBm)

15 25 35 45 55 65 75 85

GAIN (dB)

OUT

)

RMS

LNA INPUT RETURN LOSS

vs. RF FREQUENCY (ANT 1)

OFDM EVM WITH OFDM JAMMER

vs. OFFSET FREQUENCY

Rx EMISSION SPECTRUM, LNA INPUT

MAX2830 toc08

-5

-50

-60

= -62dBm

= 20MHz

OFFSET

-70

-10

-15

-80

HIGH GAIN

-90

= 25MHz

OFFSET

-100

-110

-120

-130

-140

-150

LOW GAIN

-20

-25

MID GAIN

= 40MHz

OFFSET

2300

2400

2500

2600

26.5GHz

-65

-5

-45

-35

-25

RF FREQUENCY (MHz)

(dBm)

JAMMER

Maxim Integrated

MAX2830

2.4GHz to 2.5GHz 802.11g/b RF

ansceive

, PA,

and Rx/Tx/Antenna Diversity Switch

pical Operating Characteristics (continued)

(MAX2830 EV kit, V

= 2.8V, V

= V

= 3.3V, T

= +25°C, f

= 2.437GHz, f

= 40MHz,

SHDN

= high, RXHP =

REF

CC_

CCPA

CCTXPA

SCLK = DIN = low.)

LNA INPUT RETURN LOSS

vs. RF FREQUENCY (ANT 2)

Rx RSSI STEP RESPONSE

Rx RSSI OUTPUT vs. INPUT POWER

(+32dB LNA GAIN STEP)

MAX2830 toc11

-5

3.0

LNA = HIGH GAIN

LOW GAIN

2.5

2.0

1.5

1.0

0.5

-10

-15

LNA = MEDIUM GAIN

1.45V

-20

-25

LNA = LOW GAIN

HIGH GAIN

MID GAIN

0.45

2300 2350 2400 2450 2500 2550 2600

RF FREQUENCY (MHz)

200ns/div

-120 -100

-80 -60 -40 -20

(dBm)

Rx I/Q DC OFFSET SETTLING RESPONSE

Rx RSSI STEP RESPONSE

(+8dB BB VGA GAIN STEP)

(-8dB BB VGA GAIN STEP)

(-32dB LNA GAIN STEP)

MAX2830 toc13

MAX2830 toc14

MAX2830 toc12

2.0V

2.5V

10mV

5mV

0mV

1.5V

5mV

40ns/div

200ns/div

Rx I/Q DC OFFSET SETTLING RESPONSE

I/Q OUTPUT DC ERROR DROOP

(-16dB BB VGA GAIN STEP)

(-32dB BB VGA GAIN STEP)

(RxHP = 1

→

0; 100Hz MODE)

MAX2830 toc15

MAX2830 toc16

MAX2830 toc17

-5mV

10mV

5mV

10mV

5mV

-10mV

400ns/div

20ms/div

Maxim Integrated

MAX2830

2.4GHz to 2.5GHz 802.11g/b RF

ansceive

, PA,

and Rx/Tx/Antenna Diversity Switch

pical Operating Characteristics (continued)

(MAX2830 EV kit, V

= 2.8V, V

= V

= 3.3V, T

= +25°C, f

= 2.437GHz, f

= 40MHz,

SHDN

= high, RXHP =

REF

CC_

CCPA

CCTXPA

SCLK = DIN = low.)

Rx BB VGA SETTLING RESPONSE

(-8 GAIN STEP)

Rx BB VGA SETTLING RESPONSE

(+8 GAIN STEP)

(-16 GAIN STEP)

MAX2830 toc19

MAX2830 toc20

MAX2830 toc18

500mV

-500mV

500mV

-500mV

40ns/div

RF LNA SETTLING RESPONSE

(HIGH TO MEDIUM)

Rx BB VGA SETTLING RESPONSE

(-32 GAIN STEP)

RF LNA SETTLING RESPONSE

(HIGH TO LOW)

MAX2830 toc22

MAX2830 toc21

MAX2830 toc23

500mV

-500mV

100ns/div

40ns/div

100ns/div

Rx BB FREQUENCY RESPONSE

vs. FINE SETTING (COARSE SETTING = 8.5MHz)

Rx BB FREQUENCY RESPONSE

vs. COARSE SETTING (FINE SETTING = 010)

Rx BASEBAND FILTER

GROUP DELAY

MAX2830 toc26

-20

-40

-60

-80

-100

-120

-20

-40

-60

-80

-100

100

FREQUENCY (MHz)

Maxim Integrated

MAX2830

2.4GHz to 2.5GHz 802.11g/b RF

ansceive

, PA,

and Rx/Tx/Antenna Diversity Switch

pical Operating Characteristics (continued)

(MAX2830 EV kit, V

= 2.8V, V

= V

= 3.3V, T

= +25°C, f

= 2.437GHz, f

= 40MHz,

SHDN

= high, RXHP =

REF

CC_

CCPA

CCTXPA

SCLK = DIN = low.)

HISTOGRAM: Rx PHASE IMBALANCE

HISTOGRAM: Rx STATIC DC OFFSET

HISTOGRAM: Rx GAIN IMBALANCE

114

138

MEAN: 0.3

STD: 0.314

SAMPLE SIZE: 1013

MEAN: 0mV

STD: 0.977mV

SAMPLE SIZE: 1006

MEAN: 0dB

STD: 0.064dB

SAMPLE SIZE: 951

115

/div

HISTOGRAM: Tx SIDEBAND

SUPPRESSION

HISTOGRAM: Tx LO LEAKAGE

Tx I

vs. V

MEAN: -33.45dBc

STD: 6.31dB

SAMPLE SIZE: 999

MEAN: -42dBc

STD: 1.9dB

SAMPLE SIZE: 1000

= +85

= +25

= -40

/div

2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6

(V)

Tx BASEBAND FILTER RESPONSE

Tx EVM vs. P

OUT

PA SUPPLY CURRENT vs. P

OUT

360

330

300

270

240

210

180

150

120

-10

-20

-30

-40

-50

-60

-70

-80

-90

= 2.7V

= 3V

= 3.3V

= 4.2V

CCPA

= 4.2V

= 2.7V, 3.0V, 3.3V

CCPA

0.1

100

(dBm)

BASEBAND FREQUENCY (MHz)

OUT

(dBm)

OUT

Maxim Integrated

MAX2830

2.4GHz to 2.5GHz 802.11g/b RF

ansceive

, PA,

and Rx/Tx/Antenna Diversity Switch

pical Operating Characteristics (continued)

(MAX2830 EV kit, V

= 2.8V, V

= V

= 3.3V, T

= +25°C, f

= 2.437GHz, f

= 40MHz,

SHDN

= high, RXHP =

REF

CC_

CCPA

CCTXPA

SCLK = DIN = low.)

Tx GAIN VARIATION vs. FREQUENCY

(B6:B1 = 101001)

Tx OUTPUT POWER vs. FREQUENCY

TRANSMIT EMISSION MASK

18.0

GAIN ADJUSTED TO ACHIEVE 5.6% EVM

P =

+17.1dBm

OUT

EVM = 5.6%

= -40

17.5

17.0

16.5

16.0

15.5

15.0

= +25

= +85

= +25

= -40

= +85

2.40

2.42

2.44

2.46

2.48

2.50

2387

2407

2427

2447

2467

2487

2.4

2.42

2.44

2.46

2.48

2.5

FREQUENCY (GHz)

FREQUENCY/MHz

FREQUENCY (GHz)

802.11g P

(UPPER GAIN CONTROL RANGE)

vs. GAIN SETTING

OUT

POWER DETECTOR OVER SUPP

OLTAGE

POWER DETECTOR OVER FREQUENCY

2.0

1.5

2.5

2.0

1.5

1.0

0.5

= 2.7V, 3.0V

CCPA

= 2.4GHz

1.0

0.5

= 2.5GHz

= 3.3V, 4.2V

CCPA

(dBm)

GAIN SETTINGS

OUT

PA OUTPUT ENVELOPE RESPONSE

POWER DETECTOR OVER TEMPERATURE

POWER-DETECTOR OUTPUT

2.5

PA ENVELOPE

20dB GAIN STEP

50mV

300mV

2.0

1.5

1.0

0.5

-50mV

= +85

TX I/Q INPUT

-300mV

= +25

-40

20dBm

POWER DETECTOR

PA ENVELOPE

-20dBm

s/div

100ns/div

(dBm)

OUT

Maxim Integrated

MAX2830

2.4GHz to 2.5GHz 802.11g/b RF

ansceive

, PA,

and Rx/Tx/Antenna Diversity Switch

pical Operating Characteristics (continued)

(MAX2830 EV kit, V

= 2.8V, V

= V

= 3.3V, T

= +25°C, f

= 2.437GHz, f

= 40MHz,

SHDN

= high, RXHP =

CC_

CCPA

CCTXPA

REF

SCLK = DIN = low.)

PA OUTPUT RETURN LOSS

vs. RF FREQUENCY

LO FREQUENCY vs. V

Tx OUTPUT SPURS

TUNE

MAX2830 toc46

-10

-12

-14

-16

-18

-20

2600

2550

2500

2450

2400

2350

2300

-10

-20

-30

-40

-50

-60

-70

-80

-90

RBW = 1MHz

802.11g SIGNAL

2300 2350 2400 2450 2500 2550 2600

RF FREQUENCY (MHz)

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4

(V)

26.5GHz

TUNE

LO PHASE NOISE

vs. OFFSET FREQUENCY

CHANNEL SWITCHING FREQUENCY

SETTLING (FROM 2500MHz TO 2400MHz)

MAX2830 toc49

-50

-60

50kHz

-70

-80

-90

10kHz/

div

-100

-110

-120

-130

-140

-150

-50kHz

50kHz

250

0.001

0.01

0.1

OFFSET FREQUENCY (MHz)

PLL SETTLING TIME

PLL SETTLING TIME FROM

SHUTDOWN TO STANDBY MODE

FROM STANDBY TO Tx

MAX2830 toc51

MAX2830 toc50

50kHz

10kHz/

div

10kHz/

div

-50kHz

2ms

Maxim Integrated

MAX2830

2.4GHz to 2.5GHz 802.11g/b RF

ansceive

, PA,

and Rx/Tx/Antenna Diversity Switch

pical Operating Characteristics (continued)

(MAX2830 EV kit, V

= 2.8V, V

= V

= 3.3V, T

= +25°C, f

= 2.437GHz, f

= 40MHz,

SHDN

= high, RXHP =

CC_

CCPA

CCTXPA

REF

SCLK = DIN = low.)

Rx-TO-Tx TURNAROUND

PLL SETTLING TIME

Tx-Rx TURNAROUND PLL SETTLING TIME

MAX2830 toc53

MAX2830 toc52

25kHz

5kHz/div

-25kHz

25kHz

5kHz/

div

-25kHz

CRYSTAL-OSCILLATOR OFFSET FREQUENCY

vs. CRYSTAL-OSCILLATOR TUNING BITS

CLOCK OUTPUT

MAX2830 toc54

800

700

600

500

400

300

200

100

KYOCERA

(CX-3225SB)

= 40MHz

= 5pF

CLOCK

LOAD

-100

-200

-300

-400

-500

-600

-700

-800

10ns/div

10 20 30 40 50 60 70 80 90

100110120130

(DIGITAL BITS)

TUNE

Maxim Integrated

MAX2830

2.4GHz to 2.5GHz 802.11g/b RF

ansceive

, PA,

and Rx/Tx/Antenna Diversity Switch

Block Diagram/

pical Operating Circuit

RX BASEBAND HPF

CORNER FREQUENCY

CONTROL

MODE

CONTROL

TX INPUT

RX I OUTPUTS

RXBBQ+

RXBBQ-

CCLNA

RX Q

OUTPUTS

MUX

GNDRXLNA

MAX2830

RSSI

MUX

RX/TX

GAIN CONTROL

RX/TX GAIN

CONTROL

RX INPUT

ANT1+

ANT1-

BYPASS

TUNE

GNDVCO

RX GAIN

CONTROL

IMUX QMUX

CCVCO

CCPA

PLL

DETECTOR

CTUNE

XTAL

RX/TX GAIN

CONTROL

CRYSTAL

OSCILLATOR/

BUFFER

TX OUTPUT

%1,2

ANT2+

TEMP

SENSOR

ANT2-

TO RSSI

MUX

CCXTAL

POWER DETECTOR

GNDCP

RX/TX GAIN

CONTROL

SERIAL

INTERFACE

TEMP

SENSOR

RSSI

MUX

%1,2

SHDN

CCCP

MODE CONTROL

RX/TX GAIN

CONTROL

RX/TX GAIN

CONTROL

REFERENCE

CLOCK BUFFER

OUTPUT

SERIAL INPUTS

NOTE:

ALL GROUND PINS (PINS 2, 26, AND 31) AND BYPASS CAPACITORS’ GROUND REQUIRE THEIR OWN VIAS TO GROUND.

DO NOT CONNECT THEM TO THE EXPOSED PADDLE GROUND.

Maxim Integrated

MAX2830

2.4GHz to 2.5GHz 802.11g/b RF

ansceive

, PA,

and Rx/Tx/Antenna Diversity Switch

Pin Description

NAME

FUNCTION

LNA Supply Voltage

CCLNA

GNDRXLNA LNA

Ground

ANT1+

ANT1-

Receiver and Transmitter Gain-Control Logic-Input Bit 6

Antenna 1. Differential Input to LNA in Rx mode. Input is internally AC-coupled and matched to 100

Ω

differential. Connect directly to a 2:1 balun.

Receiver Gain-Control Logic-Input Bit 7

Supply Voltage for Second Stage of Power Amplifier

Receiver and Transmitter Gain-Control Logic-Input Bit 3

CCPA

ANT2+

ANT2-

Antenna 2. Differential inputs to LNA in diversity Rx mode and to PA differential outputs in Tx mode.

Internally AC-coupled differential outputs and matched to 100

Ω

differential. Connect directly to a 2:1 balun.

Receiver and Transmitter Gain-Control Logic-Input Bit 2

SHDN

Active-Low Shutdown and Standby Logic Input. See Table 32 for operating modes.

Supply Voltage for First-Stage of PA and PA Driver

CCTXPA

Receiver and Transmitter Gain-Control Logic-Input Bit 5

Active-Low Chip-Select Logic Input of 3-Wire Serial Interface (see Figure 3)

RSSI, PA Power Detector or Temperature-Sensor Multiplexed Analog Output

Transmitter Upconverter Supply Voltage

RSSI

CCTXMX

SCLK

DIN

Serial-Clock Logic Input of 3-Wire Serial Interface (see Figure 3)

Data Logic Input of 3-Wire Serial Interface (see Figure 3)

PLL and Registers Supply Voltage. Connect to the supply voltage to retain the register settings.

CCPLL

CLOCKOUT Reference

Clock Buffer Output

Lock-Detect Logic Output of Frequency Synthesizer. Output high indicates that the frequency synthesizer is

locked. Output programmable as CMOS or open-drain output. (See Tables 17 and 21.)

Receiver and Transmitter Gain-Control Logic-Input Bit 1

Charge-Pump Output. Connect the frequency synthesizer’s loop filter between CPOUT and TUNE (see the

Block Diagram/Typical Operating Circuit

CPOUT

PLL Charge-Pump Supply Voltage

CCCP

GNDCP

Charge-Pump Circuit Ground

Crystal Oscillator Supply Voltage

CCXTAL

XTAL

Crystal or Reference Clock Input. AC-couple a crystal or a reference clock to this analog input.

Connection for Crystal Oscillator Off-Chip Capacitors. When using an external reference clock input, leave

CTUNE unconnected.

CTUNE

VCO Supply Voltage

CCVCO

GNDVCO

TUNE

VCO Ground

VCO TUNE Input (see the

Block Diagram/Typical Operating Circuit

)

On-Chip VCO Regulator Output Bypass. Bypass with a 0.1µF to 1µF capacitor to GND. Do not connect

other circuitry to this point.

BYPASS

Receiver and Transmitter Gain-Control Logic-Input Bit 4

Maxim Integrated

MAX2830

2.4GHz to 2.5GHz 802.11g/b RF

ansceive

, PA,

and Rx/Tx/Antenna Diversity Switch

Pin Description (continued)

NAME

RXBBQ-

RXBBQ+

RXBBI-

FUNCTION

Receiver Baseband Q-Channel Differential Outputs. In TX calibration mode, these pins are the LO leakage

and sideband detector outputs.

Receiver Baseband I-Channel Differential Outputs. In TX calibration mode, these pins are the LO leakage

and sideband detector outputs.

RXBBI+

Receiver VGA Supply Voltage

CCRXVGA

RXHP

Receiver Baseband AC-Coupling High-Pass Corner Frequency Control Logic Input

Receiver Baseband Filter Supply Voltage

CCRXFL

TXBBQ-

Transmitter Baseband I-Channel Differential Inputs

Transmitter Baseband Q-Channel Differential Inputs

TXBBQ+

TXBBI-

TXBBI+

Receiver Downconverters Supply Voltage

CCRXMX

ANTSEL

RXTX

Antenna Selection Logic Input. See Table 1 for operation

Rx/Tx Mode Control Logic Input. See Table 32 for operating modes.

Exposed Paddle. Connect to the ground plane with multiple vias for proper operation and heat dissipation.

Do not share with any other pin grounds and bypass capacitors’ ground.

—

Detailed Description

The MAX2830 single-chip, low-power, direct conversion,

zero-IF transceiver is designed to support 802.11g/b

applications operating in the 2.4GHz to 2.5GHz band.

The fully integrated transceivers include a receive path,

transmit path, VCO, sigma-delta fractional-N synthesizer,

crystal oscillator, RSSI, PA power detector, temperature

sensor, Rx and Tx I/Q error-detection circuitry, baseband-

control interface, linear power amplifier, and an Rx/Tx

antenna diversity switch. The only additional components

required to implement a complete radio front-end solution

are a crystal, a pair of baluns, a BPF, and a small number

of passive components (RCs, no inductors required).

MAX2830

LNA

ANT1

ANT2

Rx/Tx and Antenna Diversity Switches

The MAX2830 integrates an Rx/Tx switch and an anten-

na diversity switch before the receiver and after the

power amplifier. See Figure 1 for a block diagram of the

switches. The receiver and transmitter enable pin

(RXTX) and the antenna selection pin (ANTSEL) deter-

mine which ports (ANT1 or ANT2) the receiver or trans-

mitter is connected to. See Table 1 for the Rx/Tx and

antenna diversity switches truth table. When RXTX = 0

Figure 1. Simplified Rx/Tx and Antenna Diversity Switch Structure

(receive mode) and ANTSEL = 0, the switch provides a

low-insertion loss path (main) between the ANT1 port

(pins 4 and 5) and the receiver. When RXTX = 0

(receive mode) and ANTSEL = 1, the switch provides

Table 1. Rx/Tx and Antenna Diversity Switches Operation

RXTX

ANTSEL

MODE

Rx (main)

Rx (diversity)

ANTENNA

Ant1_

Ant2_

Maxim Integrated

MAX2830

2.4GHz to 2.5GHz 802.11g/b RF

ansceive

, PA,

and Rx/Tx/Antenna Diversity Switch

an antenna diversity path between the ANT2 port (pins

9 and 10) and the receiver. When RXTX = 1, the PA

and transmit path are automatically connected to the

ANT2 port, regardless of the logic state of ANTSEL. For

solutions not requiring antenna diversity, set ANTSEL

logic-level high, enabling only the ANT2 port for both

receive and transmit modes.

interface by programming bits D6:D5 in Register 11

(A3:A0 = 1011) or programmed in parallel through the

digital logic gain-control pins, B7 (pin 6) and B6 (pin 3).

Set bit D12 = 1 in Register 8 (A3:A0 = 1000) to enable

programming through the SPI interface, or set bit D12 =

0 to enable parallel programming. See Table 2 for LNA

gain-control settings.

The ANT1 and ANT2 differential ports are internally AC-

coupled and internally matched to 100

Ω

. Directly con-

nect 2:1 baluns or balanced bandpass filters (BPFs) to

these ports for applications requiring antenna diversity.

For applications not requiring antenna diversity, only a

single balun or balanced BPF is required on the ANT2

port, and the ANT1 port can be left open. Provide elec-

trically symmetrical input traces to the baluns to main-

tain IP2 and RF common-mode noise rejection for the

receiver, and to maintain a balanced load for the PA.

Baseband Variable-Gain Amplifier

The receiver baseband variable-gain amplifiers provide

62dB of gain control range programmable in 2dB steps.

The VGA gain can be serially programmed through the

SPI interface by setting bits D4:D0 in Register 11 (A3:A0

= 1011) or programmed in parallel through the digital

logic gain-control pins, B5 (pin 14), B4 (pin 34), B3 (pin

8), B2 (pin 11), and B1 (pin 23). Set bit D12 = 1 in

through the serial interface or set bit D12 = 0 to enable

parallel programming through the external logic pins.

See Table 3 for the gain-step value and Table 4 for

baseband VGA gain-control settings.

Receiver

After the switch, the receiver integrates an LNA and VGA

with a 95dB digitally programmable gain control range,

direct-conversion downconverters, I/Q baseband low-

pass filters with programmable LPF corner frequencies,

analog RSSI and integrated DC-offset correction circuitry.

A logic-low on the RXTX input (pin 48) and a logic-high on

the

SHDN

input (pin 12) enable the receiver.

Receiver Baseband Lowpass Filter

The receiver integrates lowpass filters that provide an

upper -3dB corner frequency of 8.5MHz (nominal mode)

with 50dB of attenuation at 20MHz, and 45ns of group

delay ripple in the passband (10kHz to 8.5MHz). The

upper -3dB corner frequency is tightly controlled on-chip

and does not require user adjustment. However, provi-

sions are made to allow fine tuning of the upper -3dB

LNA Gain Control

The LNA has three gain modes: max gain, max gain

-16dB, and max gain -33dB. The three LNA gain

modes can be serially programmed through the SPI™

Table 4. Baseband VGA Gain-Control

Settings in Receiver Gain-Control Register

(Pin B5:B1 or Register D4:D0, A3:A0 = 1011)

Table 2. LNA Gain-Control Settings (Pins

B7:B6 or Register A3:A0 = 1011, D6:D5)

B5:B1 OR D4:D0

GAIN

Max

B7 OR D6

B6 OR D5

NAME

High

DESCRIPTION

Max gain

11111

11110

11101

Max – 2dB

Max – 4dB

Medium

Low

Max gain – 16dB (typ)

Max gain – 33dB (typ)

00000

Min

Table 3. Receiver Baseband VGA Gain-

Step Value (Pins B5:B1 or Register D4:D0,

A3:A0 = 1011)

Table 5. Receiver LPF Coarse -3dB

Corner Frequency Settings in Register

(A3:A0 = 1000)

PIN/BIT

B1/D0

B2/D1

B3/D2

B4/D3

B5/

GAIN STEP (dB)

-3dB CORNER

FREQUENCY (MHz)

BITS (D1:D0)

MODE

7.5

8.5

11b

11g

Turbo 1

Turbo 2

SPI is a trademark of Motorola, Inc.

Maxim Integrated

MAX2830

2.4GHz to 2.5GHz 802.11g/b RF

ansceive

, PA,

and Rx/Tx/Antenna Diversity Switch

corner frequency. In addition, coarse frequency tuning

allows the -3dB corner frequency to be set to 7.5MHz

(11b mode), 8.5MHz (11g mode), 15MHz (turbo 1 mode),

and 18MHz (turbo 2 mode) by programming bits D1:D0

in Register 8 (A3:A0 = 1000). See Table 3. The coarse

corner frequency can be fine-tuned approximately

10%

in 5% steps by programming bits D2:D0 in Register 7

(A3:A0 = 0111). See Table 6 for receiver LPF fine -3dB

corner frequency adjustment.

Receiver I/Q Baseband Outputs

The differential outputs (RXBBI+, RXBBI-, RXBBQ+,

RXBBQ-) of the baseband amplifiers have a differential

output impedance of ~300

Ω

, and are capable of dri-

ving differential loads up to 10k

Ω

|| 10pF. The outputs

are internally biased to a common-mode voltage of

1.2V and are intended to be DC-coupled to the in-

phase (I) and quadrature (Q) analog-to-digital data

converter inputs of the accompanying baseband IC.

Additionally, the common-mode output voltage can be

adjusted from 1.2V to 1.5V through programming bits

D11:D10 in Register 15 (A3:A0 = 1111).

Baseband Highpass Filter

and DC Offset Correction

The receiver implements programmable AC and near-

DC coupling of I/Q baseband signals. Temporary AC-

coupling is used to quickly remove LO leakage and

other DC offsets that could saturate the receiver out-

puts. When DC offsets have settled, near DC-coupling

is enabled to avoid attenuation of the received signal.

AC-coupling is set (-3dB highpass corner frequency of

600kHz) when a logic-high is applied to RXHP (pin 40).

Near DC-coupling is set (-3dB highpass corner fre-

quency of 100Hz nominal) when a logic-low is applied

to RXHP. Bits D13:D12 in Register 7 (A3:A0 = 0111)

allow the near DC-coupling -3B highpass corner fre-

quency to be set to 100Hz (D13:D12 = 00), 4kHz

(D13:D12 = X1), or 30kHz (D13:D12 = 10). See Table 7.

Received Signal-Strength Indicator (RSSI)

The RSSI output (pin 16) can be programmed to multi-

plex an analog output voltage proportional to the

received signal strength, the PA output power, or the

die temperature. Set bits D9:D8 = 00 in Register 8

(A3:A0 = 1000) to enable the RSSI output in receive

mode (off in transmit mode). Set bit D10 = 1 to enable

the RSSI output when RXHP = 1, and disable the RSSI

output when RXHP = 0. Set bit D10 = 0 to enable the

RSSI output independent of RXHP. See Table 8 for a

summary of the RSSI output vs. register programming

and RXHP.

The RSSI provides an analog voltage proportional to

the log of the sum of the squares of the I and Q chan-

nels, measured after the receive baseband filters and

before the variable-gain amplifiers. The RSSI analog

output voltage is proportional to the RF input signal

level and LNA gain state over a 60dB range, and is not

dependent upon VGA gain. See the Rx RSSI Output vs.

Input Power graph in the

Typical Operating

Characteristics

for further details.

Table 6. Receiver LPF Fine -3dB Corner

Frequency Adjustment in Register

(A3:A0 = 0111)

% ADJUSTMENT RELATIVE TO

BITS (D2:D0)

COARSE SETTING

000

001

010

011

100

Table 8. RSSI Pin Truth Table

100

105

110

INPUT CONDITIONS

RSSI OUTPUT

A3:A0 = 1000,

RXHP

D9:D8

D10

No signal

RSSI

Table 7. Receiver Highpass Filter -3dB

Corner Frequency Programming

Temperature

sensor

A3:A0 = 0111,

D13:D12

-3dB HIGHPASS CORNER

FREQUENCY (Hz)

RXHP

Power detector

RSSI

600k

100 (recommended)

Temperature

sensor

Power detector

30k

X = Don’t care.

Maxim Integrated

MAX2830

2.4GHz to 2.5GHz 802.11g/b RF

ansceive

, PA,

and Rx/Tx/Antenna Diversity Switch

(A3:A0 = 0111). The -3dB corner frequency is tightly

controlled on-chip and does not require user adjust-

ment. Additionally, provisions are made to fine tune the

-3dB corner frequency through bits D5:D3 in the Filter

Programming register (A3:A0 = 0111). See Tables 9

and 10.

Transmitter

The transmitter integrates baseband lowpass filters,

direct-upconversion mixers, a VGA, a PA driver, and a lin-

ear RF PA with a power detector. A logic-high on the

RXTX input (pin 48) and a logic-high on the

SHDN

input

(pin 12) enable the transmitter. The PA outputs are routed

to ANT2, regardless of the state at ANTSEL.

Transmitter Variable-Gain Amplifier

The variable-gain amplifier of the transmitter provides

31dB of gain control range programmable in 0.5dB

steps over the top 8dB of the gain control range and in

1dB steps below that. The transmitter gain can be pro-

grammed serially through the SPI interface by setting

bits D5:D0 in Register 12 (A3:A0 = 1100) or in parallel

through the digital logic gain-control pins B6:B1 (pins

3, 6, 8, 11, 14, 23, and 34, respectively). Set bit D10 =

0 in Register 9 (A3:A0 = 1001) to enable parallel pro-

gramming, and set bit D10 = 1 to enable programming

through the 3-wire serial interface. See Table 11 for the

transmitter VGA gain-control settings.

Transmitter I/Q Baseband Inputs

The differential analog inputs of the transmitter baseband

amplifier I/Q inputs (TXBBI+, TXBBI-, TXBBQ+, TXBBQ-)

have a differential impedance of 20k

Ω

|| 1pF. The inputs

require an input common-mode voltage of 0.9V to 1.3V,

which is provided by the DC-coupled I and Q DAC out-

puts of the accompanying baseband IC.

Transmitter Baseband Lowpass Filtering

The transmitter integrates lowpass filters that can be

tuned to -3dB corner frequencies of 8MHz (11b),

11MHz (11g), 16.5MHz (turbo 1 mode), and 22.5MHz

(turbo 2 mode) through programming bits D1:D0 in

Table 9. Transmitter LPF Coarse -3dB

Corner Frequency Settings in Register

(A3:A0 = 1000)

Table 11. Transmitter VGA Gain-Control

Settings

-3dB CORNER

D5:D0 OR

BITS (D1:D0)

MODE

NO.

OUTPUT SIGNAL POWER

FREQUENCY (MHz)

B6:B1

11b

11g

111111

111110

111101

Max

Max – 0.5dB

Max – 1.0dB

16.5

22.5

Turbo 1

Turbo 2

110001

110000

101111

101110

101101

101100

Max – 7dB

Max – 7.5dB

Max – 8dB

Max – 9dB

Table 10. Transmitter LPF Fine -3dB

Corner Frequency Adjustment in

% ADJUSTMENT RELATIVE TO

BITS (D5:D3)

COARSE SETTING

000

001

000101

000100

000011

000010

000001

000000

Max – 29dB

Max – 30dB

Max – 31dB

010

100

011

105

100

110 (11g)

115

101

101–111

Not used

Maxim Integrated

MAX2830

2.4GHz to 2.5GHz 802.11g/b RF

ansceive

, PA,

and Rx/Tx/Antenna Diversity Switch

Power-Amplifier Bias and Enable Delay

The MAX2830 integrates a 2-stage PA, providing

+17.1dBm of output power at 5.6% error vector magni-

tude (EVM) (54Mbps OFDM signal) in 802.11g mode

while exceeding the 802.11g spectral mask require-

ments. The first and second stage PA bias currents are

set through programming bits D2:D0 and bits D6:D3 in

PA enable delay, relative to the transmitter enable (RXTX

low-to-high transition), can be set from 200ns to 7µs

through programming bits D13:D10 in Register 10 (A3:A0

= 1010).

1 or a divide-by-2 reference frequency divider, an 8-bit

integer portion main divider with a divisor range pro-

grammable from 64 to 255, and a 20-bit fractional por-

tion main-divider. Bit D2 in Register 5

(A3:A0 = 0101)

sets the reference oscillator divider ratio to 1 or 2. Bits

D7:D0 in Register 3 (A3:A0 = 0011) set the integer por-

tion of the main divider. The 20-bit fractional portion of

the main-divider is split between two registers. The 14

MSBs of the fractional portion are set in Register 4

(A3:A0 = 0100), and the 6 LSBs of the fractional portion

of the main divider are set in Register 3 (A3:A0 = 0011).

See Tables 12 and 13.

Power Detector

The MAX2830 integrates a voltage-peak detector at the

PA output and before the switch to provide an analog

voltage proportional to PA output power. See the Power

Detector over Frequency and Power Detector over

Supply Voltage graphs in the

Typical Operating

Characteristics

. Set bits D9:D8 = 10 in Register 8 (A3:A0

= 1000) to multiplex the power-detector analog output

voltage to the RSSI output (pin 16).

Calculating Integer and Fractional Divider Ratios

The desired integer and fractional divider ratios can be

calculated by dividing the RF frequency (f

) by f

COMP

For nominal 802.11g/b operation, a 40MHz reference

oscillator is divided by 2 to generate a 20MHz compari-

son frequency (f

COMP

). The following method can be

used when calculating divider ratios supporting various

reference and comparison frequencies:

LO Frequency Divider = f

/ f

COMP

= 2437MHz /

20MHz = 121.85

Synthesizer Programming

The MAX2830 integrates a 20-bit sigma-delta fractional-

N synthesizer, allowing the device to achieve excellent

phase-noise performance (0.9° RMS from 10kHz to

10MHz), fast PLL settling times, and an RF frequency

step-size of 20Hz. The synthesizer includes a divide-by-

Integer Divider = 121 (d) = 0111 1001 (binary)

Fractional Divider = 0.85 x (2

– 1) = 891289 (decimal)

= 1101 1001 1001 1001 1001

See Table 14 for integer and fractional divider ratios for

802.11g/b systems using a 20MHz comparison frequency.

Table 12. Integer Divider Register (A3:A0 = 0011)

BIT

RECOMMENDED

000000

DESCRIPTION

6 LSBs of 20-Bit Fractional Portion of Main Divider

8-Bit Integer Portion of Main Divider. Programmable from 64 to 255.

D13:D8

D7:D0

01111001

Table 13. Fractional Divider Register (A3:A0 = 0100)

BIT

RECOMMENDED

DESCRIPTION

D13:D0

11011001100110

14 MSBs of 20-Bit Fractional Portion of Main Divider

Maxim Integrated

MAX2830

2.4GHz to 2.5GHz 802.11g/b RF

ansceive

, PA,

and Rx/Tx/Antenna Diversity Switch

Table 14. IEEE 802.11g/b Divider-Ratio Programming Words

INTEGER DIVIDER

A3:A0 = 0011, D7:D0

0111 1000b

0111 1001b

0111 1010b

0111 1011b

0111 1100b

FRACTIONAL DIVIDER

(f /

)

RF COMP

(MHz)

A3:A0 = 0100, D13:D0

A3:A0 = 0011, D13:D8

2412

2417

2422

2427

2432

2437

2442

2447

2452

2457

2462

2467

2472

2484

120.6

120.85

121.1

2666h

3666h

0666h

1666h

2666h

3666h

0666h

1666h

2666h

3666h

0666h

1666h

2666h

0CCCh

1Ah

33h

121.35

121.6

121.85

122.1

122.35

122.6

122.85

123.1

123.35

123.6

124.2

Crystal Oscillator

Reference Clock Output Divider/Buffer

The crystal oscillator has been optimized to work with

low-cost crystals (e.g., Kyocera CX-3225SB). See

Figure 2. The crystal oscillator frequency can be fine

tuned through bits D6:D0 in Register 14 (A3:A0 = 1110),

which control the value of C

TUNE

from 0.5pF to 15.4pF in

0.12pF steps. See the Crystal-Oscillator Offset

Frequency vs. Crystal-Oscillator Tuning Bits graph in the

Typical Operating Characteristics

. The crystal oscillator

can be used as a buffer for an external reference fre-

quency source. In this case, the reference signal is AC-

coupled to the XTAL pin, and capacitors C1 and C2 are

not connected. When used as a buffer, the XTAL input

pin has to be AC-coupled. The XTAL pin has an input

impedance of 5k

Ω

|| 4pF, (set D6:D0 = 0000000 in

The reference oscillator of the MAX2830 has a divider

and a buffered output for routing the reference clock to

the accompanying baseband IC. Bit D10 in Register 14

(A3:A0 = 1110) sets the buffer divider to divide by 1 or

2, independent of the divide ratio for the reference fre-

quency provided to the PLL. Bit B9 in the same register

enables or disables the reference buffer output. See

the Clock Output waveform in the

Typical Operating

Characteristics

Loop Filter

The PLL charge-pump output, CPOUT (pin 24), con-

nects to an external third-order, lowpass RC loop-filter,

which in turn connects to the voltage tuning input,

TUNE (pin 32), of the VCO, completing the PLL loop.

The charge-pump output sink and source current is

1mA, and the VCO tuning gain is 103MHz/V at 0.5V

tune voltage and 86MHz/V at 2.2V tune voltage. The RC

loop-filter values have been optimized for a loop band-

width of 150kHz, to achieve the desired Rx/Tx turn-

around settling time, while maintaining loop stability

and good phase noise. Refer to the MAX2830 EV kit

schematic for the recommended loop-filter component

values. Keep the line from this pin to the tune input as

short as possible to prevent spurious pickup.

MAX2830

XTAL

CTUNE

1.35k

Ω

5.9k

Ω

TUNE

Lock-Detector Output

The PLL features a logic lock-detect output. A logic-high

indicates the PLL is locked, and a logic-low indicates

the PLL is not locked. Bit D5 in Register 5 (A3:A0 =

0101) enables or disables the lock-detect output. Bit

FOR EXTERNAL

REFER

ENCE CLOCK SE

1 = C2 = OPEN

Figure 2. Crystal Oscillator Schematic

Maxim Integrated

MAX2830

2.4GHz to 2.5GHz 802.11g/b RF

ansceive

, PA,

and Rx/Tx/Antenna Diversity Switch

D12 in Register 1 (A3:A0 = 0001) configures the lock-

detect output as a CMOS or open-drain output. In open-

drain output mode, bit D9 in Register 5 (A3:A0 = 0101)

enables or disables an internal 30k

Ω

pullup resistor

from the open-drain output.

MICROWIRE™-compatible serial interface. Data is

shifted in MSB first and is framed by

. When

low, the clock is active, and data is shifted with the ris-

ing edge of the clock. When

transitions high, the

shift register is latched into the register selected by the

contents of the address bits. See Figure 3. Only the last

18 bits shifted into the device are retained in the shift

pulses. For programming data words less than 14 bits

long, only the required data bits and the address bits

need to be shifted, resulting in faster Rx and Tx gain

control where only the LSBs need to be programmed.

Programmable Registers and

3-Wire SPI-Interface

The MAX2830 includes 16 programmable, 18-bit reg-

isters. The 14 most significant bits (MSBs) are used

for register data. The 4 least significant bits (LSBs) of

each register contain the register address. See Table

15 for a summary of the registers and recommended

Table 15. Recommended Register Settings*

DATA

ADDRESS

TABLE

D13 D12 D11 D10

(A3:A0)

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

The power-on register settings are not production tested. Recommended register settings must be loaded after V

is supplied.

BIT 1

BIT 2

BIT 15

BIT 16

BIT 23

BIT 24

DIN

SCLK

CSW

CSS

CSH

CSO

Figure 3. 3-Wire SPI Serial-Interface Timing Diagram

MICROWIRE is a trademark of National Semiconductor Corp.

Maxim Integrated

MAX2830

2.4GHz to 2.5GHz 802.11g/b RF

ansceive

, PA,

and Rx/Tx/Antenna Diversity Switch

Table 16. Register 0 (A3:A0 = 0000)

DATA BITS

RECOMMENDED

DESCRIPTION

D13:D11

000

Set to recommended value.

Fractional-N PLL Mode Enable. Set 1 to enable the fractional-N PLL or set 0 to enable the

integer-N PLL.

D10

D9:D0

1101000000

Set to recommended value.

Table 17. Register 1 (A3:A0 = 0001)

DATA BITS

RECOMMENDED

DESCRIPTION

D13

Set to recommended value.

Lock-Detector Output Select. Set to 1 for CMOS Output. Set to 0 for open-drain output. Bit D9

in register (A3:A0 = 0101) enables or disables an internal 30k

Ω

pullup resistor in open-drain

output mode.

D12

D11:D0

000110011010

Set to recommended value.

Table 18. Register 2 (A3:A0 = 0010)

DATA BITS

RECOMMENDED

DESCRIPTION

D13:D0

01000000000011 Set

to recommended value.

This register contains the 8-bit integer portion and 6 LSBs of the fractional portion of the divider ratio of the synthesizer.

Table 19. Register 3 (A3:A0 = 0011)

BIT

RECOMMENDED

00000

DESCRIPTION

D13:D8

D7:D0

6 LSBs of 20-Bit Fractional Portion of Main Divider

8-Bit Integer Portion of Main Divider. Programmable from 64 to 255.

01111001

Table 20. Register 4 (A3:A0 = 0100)

BIT

RECOMMENDED

DESCRIPTION

D13:D0

11011001100110 14

MSBs of 20-Bit Fractional Portion of Main Divider

Table 21. Register 5 (A3:A0 = 0101)

BIT

RECOMMENDED

DESCRIPTION

D13:D10

0000

Set to recommended value.

Lock-Detect Output Internal Pullup Resistor Enable. Set to 1 to enable internal 30k

Ω

pullup

resistor or set to 0 to disable the resistor. Only available when lock-detect, open-drain output

is selected (A3:A0 = 0001, D12 = 1).

D8:D6

010

Set to recommended value.

Lock-Detect Output Enable. Set to 1 to enable the lock-detect output or set to 0 to disable the

output. The output is high impedance when disabled.

D4:D3

Set to recommended value.

Reference Frequency Divider Ratio to PLL. Set to 0 to divide by 1. Set to 1 to divide by 2.

Set to recommended value.

D1:D0

Maxim Integrated

MAX2830

2.4GHz to 2.5GHz 802.11g/b RF

ansceive

, PA,

and Rx/Tx/Antenna Diversity Switch

Table 22. Register 6 (A3:A0 = 0110)

DATA BIT

RECOMMENDED

DESCRIPTION

D13

Set to recommended value.

Tx I/Q Calibration LO Leakage and Sideband Detector Gain-Control Bits. D12:D11 = 00: 9dB;

01 19dB; 10: 29dB; 11: 39dB.

D12:D11

D10:D7

0000

Set to recommended value.

Power-Detector Enable in Tx Mode. Set to 1 to enable the power detector or set to 0 to

disable the detector.

D5:D2

1000

Set to recommended value.

Tx Calibration Mode. Set to 1 to place the device in Tx calibration mode or 0 to place the

device in normal Tx mode when RXTX is set to 1 (see Table 32).

Rx Calibration Mode. Set to 1 to place the device in Rx calibration mode or 0 to place the

device in normal Rx mode when RXTX is set to 0 (see Table 32).

Table 23. Register 7 (A3:A0 = 0111)

BIT

RECOMMENDED

DESCRIPTION

Receiver Highpass Corner Frequency Setting for RXHP = 0. Set to 00 for 100Hz, X1 for 4kHz,

and 10 for 30kHz.

D13:D12

D11:D6

D5:D3

000000

100

Set to recommended value.

Transmitter Lowpass Filter Corner Frequency Fine Adjustment (Relative to Coarse Setting).

See Table 9. Bits D1:D0 in A3:A0 = 1000 provide the lowpass filter corner coarse adjustment.

Receiver Lowpass Filter Corner Frequency Fine Adjustment (Relative to Coarse Setting). See

Table 6. Bits D1:D0 in A3:A0 = 1000 provide the lowpass filter corner coarse adjustment.

D2:D0

010

Table 24. Register 8 (A3:A0 = 1000)

BIT

RECOMMENDED

DESCRIPTION

D13

Set to recommended value.

Enable Receiver Gain Programming Through the Serial Interface. Set to 1 to enable

programming through the 3-wire serial interface (D6:D0 in Register A3:A0 = 1011). Set to 0 to

enable programming in parallel through external digital pins (B7:B1).

D12

D11

D10

Set to recommended value.

RSSI Operating Mode. Set to 1 to enable RSSI output independent of RXHP. Set to 0 to

disable RSSI output if RXHP = 0, and enable the RSSI output if RXHP = 1.

RSSI, Power Detector, or Temperature Sensor Output Select. Set to 00 to enable the RSSI

output in receive mode. Set to 01 to enable the temperature sensor output in receive and

transmit modes. Set to 10 to enable the power-detector output in transmit mode. See Table 7.

D9:D8

D7:D2

D1:D0

001000

Set to recommended value.

Receiver and Transmitter Lowpass Filter Corner Frequency Coarse Adjustment. See Tables 4

and 7.

Maxim Integrated

MAX2830

2.4GHz to 2.5GHz 802.11g/b RF

ansceive

, PA,

and Rx/Tx/Antenna Diversity Switch

Table 25. Register 9 (A3:A0 = 1001)

BIT

RECOMMENDED

DESCRIPTION

D13:D11

000

Set to recommended value.

Enable Transmitter Gain Programming Through the Serial or Parallel Interface. Set to 1 to

enable programming through the 3-wire serial interface (D5:D0 in Register A3:A0 = 1011).

Set to 0 to enable programming in parallel through external digital pins (B6:B1).

D10

D9:D0

1110110101

Set to recommended value.

Table 26. Register 10 (A3:A0 = 1010)

BIT

RECOMMENDED

DESCRIPTION

Power-Amplifier Enable Delay. Sets a delay between RXTX low-to-high transition and internal PA

enable. Programmable in 0.5µs steps. D13:D10 = 0001 (0.2µs) and D13:D10 = 1111 (7µs).

D13:D10

0111

D9:D7

D6:D3

D2:D0

011

0100

100

Set to recommended value.

Second-Stage Power-Amplifier Bias Current Adjustment. Set to XXXX for 802.11g/b.

First-Stage Power-Amplifier Bias Current Adjustment. Set to XXX for 802.11g/b.

Table 27. Register 11 (A3:A0 = 1011)

BIT

RECOMMENDED

DESCRIPTION

D13:D7

0000000

Set to recommended value.

LNA Gain Control. Set to 11 for high-gain mode. Set to 10 for medium-gain mode, reducing

LNA gain by 16dB. Set to 0X for low-gain mode, reducing LNA gain by 33dB.

D6:D5

D4:D0

Receiver VGA Control. Set D4:D0 = 00000 for minimum gain and D4:D0 = 11111 for

maximum gain.

11111

Table 28. Register 12 (A3:A0 = 1100)

BIT

RECOMMENDED

DESCRIPTION

D13:D6

00000101

Set to recommended value.

Transmitter VGA Gain Control. Set D5:D0 = 000000 for minimum gain, and set D5:D0 =

111111 for maximum gain.

D5:D0

000000

Table 29. Register 13 (A3:A0 = 1101)

BIT

RECOMMENDED

0011

DESCRIPTION

D13:D10

D9:D6

D5:D0

Set to recommended value.

1010

010010

Maxim Integrated

MAX2830

2.4GHz to 2.5GHz 802.11g/b RF

ansceive

, PA,

and Rx/Tx/Antenna Diversity Switch

Table 30. Register 14 (A3:A0 = 1110)

BIT

D13:D11

D10

RECOMMENDED

DESCRIPTION

000

Set to recommended value.

Reference Clock Output Divider Ratio. Set 1 to divide by 2 or set 0 to divide by 1.

Reference Clock Output Enable. Set 1 to enable the reference clock output or set 0 to disable.

Set to recommended value.

D8:D7

D6:D0

XXXXXXX

Crystal-Oscillator Fine Tune. Tunes crystal oscillator over

20ppm to within

1ppm.

X = Don’t care.

Table 31. Register 15 (A3:A0 = 1111)

BIT

RECOMMENDED

DESCRIPTION

D13:D12

Set to recommended value.

Receiver I/Q Output Common-Mode Voltage Adjustment. Set D11:D10 = 00: 1.1V,

01: 1.2V, 10: 1.3V, 11: 1.45V.

D11:D10

D9:D0

0101000101

Set to recommended value.

Table 32. Operating Mode Table

SETTINGS

LOGIC PINS

CIRCUIT BLOCK STATES

PLL, VCO,

MODE

D1:D0

(A3:A0 = 0110)

CALIBRATION

SECTIONS ON

SHDN

RXTX

Rx PATH

Tx PATH

LO GEN,

AUTOTUNER

Shutdown

Standby

Off

None

Cal tone, RF phase

shift, Tx filter

Rx Calibration

Upconverters

(except LNA)

On (except PA

driver and PA)

AM detector,

Rx I/Q buffers

Tx Calibration

X = Don’t care.

Off

Note:

See Table 1 for Rx/Tx and antenna diversity operating mode.

loaded and values maintained, as long as V

applied. Set

SHDN

and RXTX logic-low to place the

device in shutdown mode. After a supply voltage ramp

up, supply current in shutdown mode could be high.

Program the default value to SPI register 0 to eliminate

high shutdown current.

Modes of Operation

The modes of operation for the MAX2830 are shutdown,

standby, transmit, receive, transmitter calibration, and

receiver calibration. See Table 32 for a summary of the

modes of operation. The logic-input pins,

SHDN

(pin 12)

and RXTX (pin 48), control the various modes.

Standby Mode

The standby mode is used to enable the frequency syn-

thesizer block while the rest of the device is powered

down. In this mode, the PLL, VCO, and LO generators

Shutdown Mode

The MAX2830 features a low-power shutdown mode

that disable

s a

ll circuit blocks, except the serial-inter-

face and internal registers, allowing the registers to be

Maxim Integrated

MAX2830

2.4GHz to 2.5GHz 802.11g/b RF

ansceive

, PA,

and Rx/Tx/Antenna Diversity Switch

are on, so that Tx or Rx modes can be quickly enabled

from this mode. Set

SHDN

to a logic-low and RXTX to a

logic-high to place the device in standby mode.

calibrate the Tx path, first set the power-detector gain

to 9dB using D12:D11 in Register 6 (see Table 22).

Adjust the DC offset of the baseband inputs to mini-

mize the signal at f

TONE

(LO leakage). Then, adjust the

baseband input relative magnitude and phase offsets

Receive (Rx) Mode

The complete receive signal path is enabled in this

mode. Set

SHDN

to logic-high and RXTX to logic-low to

place the device in Rx mode.

to reduce the signal at 2 x f

TONE

In Rx calibration mode, the calibrated Tx RF signal is

internally routed to the Rx inputs. In this mode, the

VCO/LO generator/PLL blocks are powered on and

active except for the low-noise amplifier (LNA).

Transmit (Tx) Mode

The complete transmitter signal path is enabled in this

mode. Set

SHDN

and RXTX to logic-high to place the

device in Tx mode.

Applications Information

Layout Issues

The MAX2830 EV kit can be used as a starting point for

layout. For best performance, take into consideration

grounding and RF, baseband, and power-supply routing.

Make connections from vias to the ground plane as short

as possible. Do not connect the device ground pin to the

exposed paddle ground. Keep the buffered clock output

trace as short as possible. Do not share the trace with the

RF input layer, especially on or interlayer or back side of

the board. On the high-impedance ports, keep traces

short to minimize shunt capacitance. EV kit Gerber files

can be requested at www.maxim-ic.com.

Rx/Tx Calibration Mode

The MAX2830 features Rx/Tx calibration modes to detect

I/Q imbalances and transmit LO leakage. In the Tx cali-

bration mode, all Tx circuit blocks, except the PA driver

and external PA, are powered on and active. The AM

detector and receiver I and Q channel buffers are also

on, along with multiplexers in the receiver side to route

this AM detector’s signal. In this mode, the LO leakage

calibration is done only for the LO leakage signal that is

present at the center frequency of the channel (i.e., in the

middle of the OFDM or QPSK spectrum). The LO leakage

calibration includes the effect of all DC offsets in the

entire baseband paths of the I/Q modulator and direct

leakage of the LO to the I/Q modulator output.

Power-Supply Layout

To minimize coupling between different sections of the

IC, a star power-supply routing configuration with a

The LO leakage and sideband detector output are

taken at the receiver I and Q channel outputs during

this calibration phase.

large decoupling capacitor at a central V

node is

recommended. The V

traces branch out from this

node, each going to a separate V

node in the circuit.

During Tx LO leakage and I/Q imbalance calibration, a

sine and cosine signal (f = f

TONE

) is input to the base-

band I/Q Tx pins from the baseband IC. At the LO leak-

age and sideband-detector output, the LO leakage

corresponds to the signal at f

TONE

and the sideband

suppression corresponds to the signal at 2 x f

TONE

. The

output power of these signals vary 1dB for 1dB of vari-

ation in the LO leakage and sideband suppression. To

Place a bypass capacitor as close as possible to each

supply pin. This arrangement provides local decoupling

at each V

pin. Use at least one via per bypass

capacitor for a low-inductance ground connection. Do

not share the capacitor ground vias with any other

branch and the exposed paddle ground.

Maxim Integrated

MAX2830

2.4GHz to 2.5GHz 802.11g/b RF

ansceive

, PA,

and Rx/Tx/Antenna Diversity Switch

POWER SUPP

POWER

3-WIRE SERIAL INTERFACE AVAILABLE

REF

SHDN

RXTX

SHUTDOWN

CS (SELECT)

SCLK (CLOCK)

DIN (DATA)

SCLK

DIN

SPI:

CHANNEL FREQUENC

, PA BIAS, TRANSMITTER LINEARIT

RECEIVER RSSI OPERATION, CALIBRATION MODE, ETC.

INTERNAL PA

ENABLED

0 TO 7

PA ENABLE

(DRIVES POWER RAMP CONTROL)

SHUTDOWN

MODE

STANDBY

MODE

RECEIVE

MODE

TRANSMIT

MODE

Figure 4. Timing Diagram

Pin Configuration

Chip Information

PROCESS: BiCMOS

TOP VIEW

Package Information

48 47 46 45 44 43 42 41 40 39 38 37

For the latest package outline information and land patterns

(footprints), go to

www.maxim-ic.com/packages

. Note that a

“+”, “#”, or “-” in the package code indicates RoHS status only.

Package drawings may show a different suffix character, but

the drawing pertains to the package regardless of RoHS status.

RXBBQ+

CCLNA

GNDRXLNA

35 RXBBQ-

ANT1+

ANT1-

BYPASS

TUNE

LAND

PACKAGE

OUTLINE NO.

21-0144

GNDVCO

MAX2830

PATTERN NO.

TYPE

CODE

CCVCO

CCPA

90-0130

48 TQFN-EP

T4877+4

CTUNE

XTAL

ANT2+

ANT2-

CCXTAL

GNDCP

EP*

13 14 15 16 17 18 19 20 21 22 23 24

SHDN 12

CCCP

*EXPOSED PADDLE

THIN QFN

Maxim Integrated

MAX2830

2.4GHz to 2.5GHz 802.11g/b RF

ansceive

, PA,

and Rx/Tx/Antenna Diversity Switch

Revision History

REVISION REVISION

PAGES

CHANGED

DESCRIPTION

NUMBER

DATE

3/07

7/09

Initial release

—

Corrected Table 12

Corrected conditions for Rx I/Q Output Common-Mode Voltage Variation in the

Electrical Characteristics

; corrected Tables 15 and 31; added text to

Shutdown Mode

section

3/11

2, 26, 30

Maxim canno

t ass

ume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.

Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical

Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc.

Maxim Integrated

160 Rio Robles, San Jose, CA 95134 USA

1-408-601-1000

2011

Maxim Integrated

Analog-Devices-Inc–Maxim-Integrated-MAX2830ETM-T

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