Analog-Devices-LTC6240HS5-TRMPBF
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LTC6240/LTC6241/LTC6242
Single/Dual/Quad 18MHz,
Low Noise, Rail-to-Rail Output,
CMOS Op Amps
FEATURES
DESCRIPTION
The
L
T
C
®
6240/6241/
L
T
C6242 are single, dual and quad
low noise, low offset, rail-to-rail output, unity gain stable
CMO
S
o
p
a
mp
s
t
ha
t
f
eatur
e
1
p
A
o
f
i
npu
t
b
ia
s
c
urrent
.
I
nput
bias current is guaranteed to be 1pA max on the single
n
0.1Hz to 10Hz Noise: 550nV
P-P
n
Input Bias Current:
0.2pA (Typ at 25°C)
1pA Max (
L
T
C6240)
n
Low Offset Voltage: 125μV Max
L
T
C6240. Th
e
0
.1H
z
t
o
1
0H
z
n
ois
e
o
f
o
nl
y
5
50nV
, along
P-P
n
n
n
n
Low Offset Drift: 2.5μV/°C Max
Gain Bandwidth Product: 18MHz
Output Swings Rail-to-Rail
Supply Operation:
with an offset of just 125μV are significant improvements
over traditional CMOS op amps. Additionally, noise is
guaranteed to be less than 10nV/√
Hz
at 1kHz. An 18MHz
gain bandwidth, and 10V/μs slew rate, along with the wide
suppl
y
r
ang
e
a
n
d
l
o
w
i
npu
t
c
apacitance
,
m
ak
e
t
he
m
p
erfect
for use as fast signal processing amplifiers.
2.8V to 6V
L
T
C6240/
L
T
C6241/
L
T
C6242
2.8V to
5.5V
L
T
C6240HV/
L
T
C6241HV/
L
T
C6242HV
Low Input Capacitance
H-Grade Temperature Range: –40°C to 125°C
Single
L
T
C6240 in 5-Pin Low Profile (1mm)
ThinSOT™ Package and 8-Pin SO for PCB Guard Ring
Dual
L
T
C6241 in 8-Pin SO and Tiny DFN Packages
Quad
L
T
C6242 in 16-Pin SSOP and 5mm
×
3mm
DFN Packages
n
n
n
These op amps have an output stage that swings within
30mV of either supply rail to maximize the signal dynamic
rang
e
i
n
l
o
w
s
uppl
y
a
pplications
.
T
h
e
i
npu
t
c
ommo
n
m
ode
range extends to the negative supply. They are fully speci-
fied on 3V and 5
V
,
a
nd an HV version guarantees operation
on supplies up to
5
V
.
n
n
Th
e
L
T
C624
0
i
s
a
vailabl
e
i
n
t
h
e
8
-pi
n
S
O
a
n
d
t
h
e
5
-pi
n
S
O
T
–
23 packages. The
L
T
C6241 is available in the 8-pin SO, and
for compact designs it is packaged in a tiny dual fine pitch
leadless (DFN) package. The
L
T
C6242 is available in the
16-pin SSOP as well as the 5mm
×
3mm DFN package.
APPLICATIONS
n
Photo Diode Amplifiers
n
Charge Coupled Amplifiers
n
Low Noise Signal Processing
L
,
L
T, L
T
C,
L
T
M, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. ThinSOT is a trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
n
Medical Instrumentation
n
High Impedance
T
r
ansducer Amplifier
TYPICAL APPLICATION
Low Noise Single-Ended Input to Differential Output Amplifier
Noise Voltage vs Frequency
C3
60
T
V
V
= 25°C
A
S
10pF
=
2.5V
= 0V
C4
10pF
50
40
30
20
10
0
CM
R4
4.99k
C1
10pF
+2.5V
1/2
R1
200k
R3
4.99k
V
–
IN
+
–
V
V
OUT
OUT
L
T
C6241
+
–
–2.5V
1/2
L
T
C6241
+
R2
200k
1
10
100
1k
10k
100k
FREQUENCY (Hz)
6241 TA01a
C2
10pF
6241 TA01b
624012fe
1
LTC6240/LTC6241/LTC6242
(Note 1)
ABSOLUTE MAXIMUM RATINGS
Total Supply Voltage (V
to V )
+
–
Specified Temperature Range (Note 3)
LTC6240/LTC6241/LTC6242 ……………………………..7V
LTC6240HV/LTC6241HV/LTC6242HV……………….
.
1
2V
Input Voltage…………………….. (V
+ 0.3V) to (V
– 0.3V)
Input Current………………………………………………..
10mA
Output Short-Circuit Duration (Note 2
)
.
……….. Indefinite
Operating Temperature Range
LTC6240C/LTC6241C/LTC6242C………….. 0°C to 70°C
LTC6240I/LTC6241I/LTC6242I …………
.
–40°C to 85°C
LTC6240H/LTC6241H/LTC6242
H
.
…… –40°C to 125°C
Junction Temperature ……………………………………. 150°C
DHC, DD Package ……………………………………… 125°C
Storage Temperature Range ……………… –65°C to 150°C
DHC, DD Package ………………………… –65°C to 125°C
Lead Temperature (Soldering, 10 sec)………………
.
3
00°C
+
–
LTC6240C/LTC6241C/LTC6242C………
.
–40°C to 85°C
LTC6240I/LTC6241I/LTC6242I …………
.
–40°C to 85°C
LTC6240H/LTC6241H/LTC6242
H
.
…… –40°C to 125°C
PIN CONFIGURATION
L
T
C6240
L
T
C6240
TOP VIEW
TOP VIEW
+
NC
–IN
+IN
1
2
3
4
8
7
6
5
NC
–
+
OUT 1
–
5 V
+
V
V
2
OUT
NC
+IN 3
4 –IN
–
V
S5 PACKAGE
5-LEAD PLASTIC TSOT-23
S8 PACKAGE
8-LEAD PLASTIC SO
T
= 150°C,
θ
= 250°C/W
JMAX
JA
T
= 150°C,
θ
= 190°C/W
JMAX
JA
L
T
C6241
L
T
C6241
TOP VIEW
TOP VIEW
+
OUT A
–IN A
+IN A
1
2
3
4
8
7
6
5
V
+
OUT A
–IN A
+IN A
1
2
3
4
8
7
6
5
V
OUT B
–IN B
+IN B
A
OUT B
–IN B
+IN B
A
B
–
V
B
–
V
DD PACKAGE
8-LEAD (3mm
s
3mm) PLASTIC DFN
S8 PACKAGE
8-LEAD PLASTIC SO
T
= 125°C,
θ
= 43°C/W
JA
JMAX
T
= 150°C,
θ
= 190°C/W
JMAX
JA
–
UNDERSIDE METAL CONNECTED TO V
(PCB CONNECTION OPTIONAL)
L
T
C6242
L
T
C6242
TOP VIEW
TOP VIEW
OUT A
–IN A
+IN A
1
2
3
4
5
6
7
8
16 OUT
D
15 –IN
D
OUT A
–IN A
+IN A
1
2
3
4
5
6
7
8
16
15
14
13
OUT D
A
B
–IN D
+IN D
D
C
A
B
D
C
14 +IN
D
–
+
V
13 V
+
–
V
V
17
+IN B
–IN B
OUT B
NC
12 +IN
C
11 –IN
C
10 OUT
C
+IN B
–IN B
OUT B
NC
12 +IN
C
11
10
9
–IN C
OUT C
NC
9
NC
DHC PACKAGE
16-LEAD (5mm
s
3mm) PLASTIC DFN
GN PACKAGE
16-LEAD PLASTIC SSOP
T
= 125°C,
θ
= 43°C/W
JMAX
JA
T
= 150°C,
θ
= 135°C/W
JA
JMAX
–
UNDERSIDE METAL CONNECTED TO V
(PCB CONNECTION OPTIONAL)
624012fe
2
LTC6240/LTC6241/LTC6242
ORDER INFORMATION
LEAD FREE FINISH
L
T
C6240CS5#PBF
L
T
C6240HVCS5#PBF
L
T
C6240IS5#PBF
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
SPECIFIED TEMPER
A
T
URE RANGE
0°C to 70°C
L
T
C6240CS5#TRPBF
L
T
C6240HVCS5#TRPBF
L
T
C6240IS5#TRPBF
L
T
C6240HVIS5 #TRPBF
L
T
C6240HS5#TRPBF
L
T
C6240HVHS5#TRPBF
L
T
C6240CS8#TRPBF
L
T
C6240HVCS8#TRPBF
L
T
C6240IS8#TRPBF
L
T
C6240HVIS8#TRPBF
L
T
C6240HS8#TRPBF
L
T
C6240HVHS8#TRPBF
L
T
C6241CDD#TRPBF
L
T
CRR
L
T
CRS
L
T
CRR
L
T
CRS
L
T
CRR
L
T
CRS
6240
5-Lead Plastic TSO
T
–
23
5-Lead Plastic TSO
T
–
23
5-Lead Plastic TSO
T
–
23
5-Lead Plastic TSO
T
–
23
5-Lead Plastic TSO
T
–
23
5-Lead Plastic TSO
T
–
23
8-Lead Plastic SO
0°C to 70°C
–40°C to 85°C
–40°C to 85°C
–40°C to 125°C
–40°C to 125°C
0°C to 70°C
L
T
C6240HVIS5#PBF
L
T
C6240HS5#PBF
L
T
C6240HVHS5#PBF
L
T
C6240CS8#PBF
L
T
C6240HVCS8#PBF
L
T
C6240IS8#PBF
6240HV
6240I
8-Lead Plastic SO
0°C to 70°C
8-Lead Plastic SO
–40°C to 85°C
–40°C to 85°C
–40°C to 125°C
–40°C to 125°C
0°C to 70°C
L
T
C6240HVIS8#PBF
L
T
C6240HS8#PBF
L
T
C6240HVHS8#PBF
L
T
C6241CDD#PBF
L
T
C6241HVCDD#PBF
L
T
C6241IDD#PBF
240HVI
6240H
240HVH
LBPD
8-Lead Plastic SO
8-Lead Plastic SO
8-Lead Plastic SO
8-Lead (3mm
×
3mm) Plastic DFN
8-Lead (3mm
×
3mm) Plastic DFN
8-Lead (3mm
×
3mm) Plastic DFN
8-Lead (3mm
×
3mm) Plastic DFN
8-Lead Plastic SO
L
T
C6241HVCDD#TRPBF LBRR
0°C to 70°C
L
T
C6241IDD#TRPBF
L
T
C6241HVIDD#TRPBF
L
T
C6241CS8#TRPBF
L
T
C6241HVCS8#TRPBF
L
T
C6241IS8#TRPBF
LBPD
–40°C to 85°C
–40°C to 85°C
0°C to 70°C
L
T
C6241HVIDD#PBF
L
T
C6241CS8#PBF
L
T
C6241HVCS8#PBF
L
T
C6241IS8#PBF
LBRR
6241
6241HV
6241I
8-Lead Plastic SO
0°C to 70°C
8-Lead Plastic SO
–40°C to 85°C
–40°C to 85°C
–40°C to 125°C
–40°C to 125°C
0°C to 70°C
L
T
C6241HVIS8#PBF
L
T
C6241HS8#PBF
L
T
C6241HVHS8#PBF
L
T
C6242CDHC#PBF
L
T
C6242HVCDHC#PBF
L
T
C6242IDHC#PBF
L
T
C6242HVIDHC#PBF
L
T
C6242CGN#PBF
L
T
C6242HVCGN#PBF
L
T
C6242IGN#PBF
L
T
C6241HVIS8#TRPBF
L
T
C6241HS8#TRPBF
L
T
C6241HVHS8#TRPBF
L
T
C6242CDHC#TRPBF
241HVI
6241H
241HVH
6242
8-Lead Plastic SO
8-Lead Plastic SO
8-Lead Plastic SO
16-Lead (5mm
×
3mm) Plastic DFN
16-Lead (5mm
×
3mm) Plastic DFN
16-Lead (5mm
×
3mm) Plastic DFN
16-Lead (5mm
×
3mm) Plastic DFN
16-Lead Plastic SSOP
16-Lead Plastic SSOP
16-Lead Plastic SSOP
16-Lead Plastic SSOP
16-Lead Plastic SSOP
16-Lead Plastic SSOP
L
T
C6242HVCDHC#TRPBF 6242HV
L
T
C6242IDHC#TRPBF 6242
L
T
C6242HVIDHC#TRPBF 6242HV
L
T
C6242CGN#TRPBF 6242
L
T
C6242HVCGN#TRPBF 6242HV
0°C to 70°C
–40°C to 85°C
–40°C to 85°C
0°C to 70°C
0°C to 70°C
L
T
C6242IGN#TRPBF
L
T
C6242HVIGN#TRPBF
L
T
C6242HGN#TRPBF
6242I
–40°C to 85°C
–40°C to 85°C
–40°C to 125°C
–40°C to 125°C
L
T
C6242HVIGN#PBF
L
T
C6242HGN#PBF
L
T
C6242HVHGN#PBF
242HVI
6242H
L
T
C6242HVHGN#TRPBF 242HVH
Consult
L
T
C Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is identified by a label on the shipping containe
r
.
Consult
L
T
C Marketing for information on non-standard lead based finish parts.
624012fe
3
LTC6240/LTC6241/LTC6242
AVAILABLE OPTIONS
PART NUMBER
AMPS/PACKAGE
SPECIFIED TEMP RANGE
0°C to 70°C
SPECIFIED SUPP
L
Y
V
O
L
T
A
GE
3
V
,
5
V
PACKAGE
SO
T
–
23
SO-8
SO
T
–
23
SO-8
SO
T
–
23
SO-8
SO
T
–
23
SO-8
SO
T
–
23
SO-8
SO
T
–
23
SO-8
SO-8
DD
PART MARKING
L
T
CRR
6240
L
T
C6240CS5
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
4
4
4
4
4
4
4
4
4
4
L
T
C6240CS8
0°C to 70°C
3
V
,
5
V
L
T
C6240HVCS5
L
T
C6240HVCS8
L
T
C6240IS5
0°C to 70°C
3
V
,
5
V
,
5
V
3
V
,
5
V
,
5
V
3
V
,
5
V
L
T
CRS
6240HV
L
T
CRR
6240I
0°C to 70°C
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
0°C to 70°C
L
T
C6240IS8
3
V
,
5
V
L
T
C6240HVIS5
L
T
C6240HVIS8
L
T
C6240HS5
3
V
,
5
V
,
5
V
3
V
,
5
V
,
5
V
3
V
,
5
V
L
T
CRS
240HVI
L
T
CRR
6240H
L
T
CRS
240HVH
6241
L
T
C6240HS8
3
V
,
5
V
L
T
C6240HVHS5
L
T
C6240HVHS8
L
T
C6241CS8
3
V
,
5
V
,
5
V
3
V
,
5
V
,
5
V
3
V
,
5
V
L
T
C6241CDD
L
T
C6241HVCS8
L
T
C6241HVCDD
L
T
C6241IS8
0°C to 70°C
3
V
,
5
V
LBPD
0°C to 70°C
3
V
,
5
V
,
5
V
3
V
,
5
V
,
5
V
3
V
,
5
V
SO-8
DD
6241HV
LBRR
0°C to 70°C
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
–40°C to 125°C
–40°C to 125°C
0°C to 70°C
SO-8
DD
6241I
L
T
C6241IDD
3
V
,
5
V
LBPD
L
T
C6241HVIS8
L
T
C6241HVIDD
L
T
C6241HS8
3
V
,
5
V
,
5
V
3
V
,
5
V
,
5
V
3
V
,
5
V
SO-8
DD
241HVI
LBRR
SO-8
SO-8
GN
6241H
241HVH
6242
L
T
C6241HVHS8
L
T
C6242CGN
L
T
C6242CDHC
L
T
C6242HVCGN
L
T
C6242HVCDHC
L
T
C6242IGN
3
V
,
5
V
,
5
V
3
V
,
5
V
0°C to 70°C
3
V
,
5
V
DHC
GN
6242
0°C to 70°C
3
V
,
5
V
,
5
V
3
V
,
5
V
,
5
V
3
V
,
5
V
6242HV
6242HV
6242I
0°C to 70°C
DHC
GN
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
–40°C to 125°C
–40°C to 125°C
L
T
C6242IDHC
L
T
C6242HVIGN
L
T
C6242HVIDHC
L
T
C6242HGN
L
T
C6242HVHGN
3
V
,
5
V
DHC
GN
6242
3
V
,
5
V
,
5
V
3
V
,
5
V
,
5
V
3
V
,
5
V
242HVI
6242HV
6242H
242HVH
DHC
GN
3
V
,
5
V
,
5
V
GN
624012fe
4
LTC6240/LTC6241/LTC6242
ELECTRICAL CHARACTERISTICS
(
L
T
C6240C/I,
L
T
C6240HVC/I,
L
T
C6241C/I,
L
T
C6241HVC/I,
L
T
C6242C/I,
L
T
C6242HVC/I) The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at
T
A
= 25°C. V
S
= 5
V
,
0
V
,
V
CM
= 2.5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Input Offset Voltage (Note 4)
L
T
C6241 S8
0°C to 70°C
–40°C to 85°C
40
125
250
300
μV
μV
μV
OS
l
l
L
T
C6242 GN
0°C to 70°C
–40°C to 85°C
50
50
150
275
300
μV
μV
μV
l
l
L
T
C6240
0°C to 70°C
–40°C to 85°C
175
300
350
μV
μV
μV
l
l
L
T
C6241 DD,
L
T
C6242 DHC
0°C to 70°C
100
40
550
650
725
μV
μV
μV
l
l
–40°C to 85°C
V
OS
Match Channel-to-Channel (Note 5)
L
T
C6241 S8
160
300
375
μV
μV
μV
l
l
0°C to 70°C
–40°C to 85°C
L
T
C6242 GN
0°C to 70°C
–40°C to 85°C
50
185
325
400
μV
μV
μV
l
l
L
T
C6241 DD,
L
T
C6242 DHC
0°C to 70°C
–40°C to 85°C
150
650
700
750
μV
μV
μV
l
l
l
l
l
l
l
TC V
Input Offset Voltage Drift (Note 6)
Input Bias Current (Notes 4, 7)
0.7
0.2
2.5
μV/°C
OS
I
B
L
T
C6241,
L
T
C6242
L
T
C6240
pA
pA
75
0.2
0.2
0.2
1
75
pA
pA
I
OS
Input Offset Current (Notes 4, 7)
L
T
C6241,
L
T
C6242
L
T
C6240
pA
pA
75
1
75
pA
pA
Input Noise Voltage
0.1Hz to 10Hz
f = 1kHz
550
7
nV
P-P
e
n
Input Noise Voltage Density
Input Noise Current Density (Note 8)
Input Resistance
10
nV/√
Hz
fA/√
Hz
Ω
i
n
0.56
12
R
IN
Common Mode
f = 100kHz
10
C
IN
Input Capacitance
Differential Mode
Common Mode
3.5
3
pF
pF
l
l
V
Input Voltage Range
Guaranteed by CMRR
0
3.5
V
CM
CMRR
Common Mode Rejection
0V ≤ V
≤ 3.5V
80
105
95
dB
CM
CMRR Match
Channel-to-Channel (Note 5)
l
76
dB
624012fe
5
LTC6240/LTC6241/LTC6242
ELECTRICAL CHARACTERISTICS
(
L
T
C6240C/I,
L
T
C6240HVC/I,
L
T
C6241C/I,
L
T
C6241HVC/I,
L
T
C6242C/I,
L
T
C6242HVC/I) The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at
T
A
= 25°C. V
S
= 5
V
,
0
V
,
V
CM
= 2.5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
A
VOL
Large Signal Voltage Gain
V =
1V to 4V
O
R =
10k to V
/2
425
300
200
1600
V/mV
V/mV
V/mV
L
S
l
l
0°C to 70°C
–40°C to 85°C
V =
1.5V to 3.5V
O
R =
1k to V
/2
90
60
50
215
V/mV
V/mV
V/mV
L
S
l
l
0°C to 70°C
–40°C to 85°C
l
l
l
V
V
Output Voltage Swing Low (Note 9)
Output Voltage Swing High (Note 9)
Power Supply Rejection
No Load
SINK
SINK
7
30
75
mV
mV
mV
OL
I
I
= 1mA
= 5mA
40
190
325
l
l
l
No Load
SOURCE
SOURCE
11
45
190
30
75
325
mV
mV
mV
OH
I
I
= 1mA
= 5mA
l
PSRR
V =
2.8V to 6
V
, V
=
0
.2V
S
80
104
100
dB
CM
PSRR Match
Channel-to-Channel (Note 5)
l
l
l
74
2.8
15
dB
V
Minimum Supply Voltage (Note 10)
Short-Circuit Current
I
I
30
mA
SC
Supply Current per Amplifier
L
T
C6241,
L
T
C6242
0°C to 70°C
–40°C to 85°C
1.8
2.2
2.3
2.4
mA
mA
mA
S
l
l
L
T
C6240
0°C to 70°C
–40°C to 85°C
2
2.4
2.5
2.6
mA
mA
mA
l
l
l
l
l
GBW
SR
Gain Bandwidth Product
Slew Rate (Note 11)
Frequency = 20kHz, R
= 1kΩ
13
5
18
10
MHz
V/μs
MHz
ns
L
A =
–2, R
= 1kΩ
V
L
FPBW
Full Power Bandwidth (Note 12)
Settling Time
V
OUT
= 3V
, R
= 1kΩ
0.53
1.06
1100
P-P
L
t
s
V =
2
V
, A
=
–
1, R
= 1kΩ, 0.1%
STEP V
L
624012fe
6
LTC6240/LTC6241/LTC6242
ELECTRICAL CHARACTERISTICS
(
L
T
C6240C/I,
L
T
C6240HVC/I,
L
T
C6241C/I,
L
T
C6241HVC/I,
L
T
C6242C/I,
L
T
C6242HVC/I) The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at
T
A
= 25°C. V
S
= 3
V
,
0
V
,
V
CM
= 1.5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Input Offset Voltage (Note 4)
L
T
C6241 S8
0°C to 70°C
–40°C to 85°C
40
175
275
325
μV
μV
μV
OS
l
l
L
T
C6242 GN
0°C to 70°C
–40°C to 85°C
60
50
200
275
325
μV
μV
μV
l
l
L
T
C6240
0°C to 70°C
–40°C to 85°C
200
325
375
μV
μV
μV
l
l
L
T
C6241 DD,
L
T
C6242 DHC
0°C to 70°C
100
40
550
650
725
μV
μV
μV
l
l
–40°C to 85°C
V
OS
Match Channel-to-Channel (Note 5)
L
T
C6241 S8
200
325
400
μV
μV
μV
l
l
0°C to 70°C
–40°C to 85°C
L
T
C6242 GN
0°C to 70°C
–40°C to 85°C
60
225
325
400
μV
μV
μV
l
l
L
T
C6241 DD,
L
T
C6242 DHC
0°C to 70°C
–40°C to 85°C
150
650
700
750
μV
μV
μV
l
l
l
l
l
l
TC V
Input Offset Voltage Drift (Note 6)
Input Bias Current (Notes 4, 7)
0.7
0.2
2.5
μV/°C
OS
I
B
L
T
C6241,
L
T
C6242
L
T
C6240
pA
pA
75
0.2
0.2
0.2
1
75
pA
pA
I
OS
Input Offset Current (Notes 4, 7)
L
T
C6241,
L
T
C6242
L
T
C6240
pA
pA
75
1
75
pA
pA
l
l
l
V
CM
Input Voltage Range
Guaranteed by CMRR
0
1.5
V
CMRR
Common Mode Rejection
0V ≤ V
≤ 1.5V
78
100
95
dB
CM
CMRR Match
Channel-to-Channel (Note 5)
l
76
dB
A
VOL
Large Signal Voltage Gain
V =
1V to 2V
O
R =
10k to V
/2
140
100
75
600
V/mV
V/mV
V/mV
L
S
l
l
0°C to 70°C
–40°C to 85°C
l
l
V
V
Output Voltage Swing Low (Note 9)
Output Voltage Swing High (Note 9)
Power Supply Rejection
No Load
SINK
3
30
mV
mV
OL
I
= 1mA
65
110
l
l
No Load
= 1mA
4
70
30
120
mV
mV
OH
I
SOURCE
l
PSRR
V =
2.8V to 6
V
, V
=
0
.2V
S
80
104
100
dB
CM
PSRR Match
Channel-to-Channel (Note 5)
l
l
l
74
2.8
3
dB
V
Minimum Supply Voltage (Note 10)
Short-Circuit Current
I
6
mA
SC
624012fe
7
LTC6240/LTC6241/LTC6242
ELECTRICAL CHARACTERISTICS
(
L
T
C6240C/I,
L
T
C6240HVC/I,
L
T
C6241C/I,
L
T
C6241HVC/I,
L
T
C6242C/I,
L
T
C6242HVC/I) The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at
T
A
= 25°C. V
S
= 3
V
,
0
V
,
V
CM
= 1.5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
Supply Current per Amplifier
L
T
C6241,
L
T
C6242
0°C to 70°C
–40°C to 85°C
1.4
1.7
1.8
1.9
mA
mA
mA
S
l
l
L
T
C6240
1.5
17
1.9
2
2.1
mA
mA
mA
l
l
0°C to 70°C
–40°C to 85°C
l
GBW
Gain Bandwidth Product
Frequency = 20kHz, R
= 1kΩ
12
MHz
L
(
L
T
C6240HVC/I,
L
T
C6241HVC/I,
L
T
C6242HVC/I) The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. V
S
= 5
V
,
0
V
,
V
CM
= 0V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Input Offset Voltage (Note 4)
L
T
C6241 S8
0°C to 70°C
–40°C to 85°C
50
175
275
325
μV
μV
μV
OS
l
l
L
T
C6242 GN
0°C to 70°C
–40°C to 85°C
60
60
200
275
325
μV
μV
μV
l
l
L
T
C6240
0°C to 70°C
–40°C to 85°C
250
350
400
μV
μV
μV
l
l
L
T
C6241 DD,
L
T
C6242 DHC
0°C to 70°C
100
50
550
650
725
μV
μV
μV
l
l
–40°C to 85°C
V
OS
Match Channel-to-Channel (Note 5)
L
T
C6241 S8
200
325
400
μV
μV
μV
l
l
0°C to 70°C
–40°C to 85°C
L
T
C6242 GN
0°C to 70°C
–40°C to 85°C
60
225
325
400
μV
μV
μV
l
l
L
T
C6241 DD,
L
T
C6242 DHC
0°C to 70°C
–40°C to 85°C
150
650
700
750
μV
μV
μV
l
l
l
l
l
l
l
TC V
Input Offset Voltage Drift (Note 6)
Input Bias Current (Notes 4, 7)
0.7
0.5
2.5
μV/°C
OS
I
B
L
T
C6241,
L
T
C6242
L
T
C6240
pA
pA
75
0.5
0.2
0.2
550
1
75
pA
pA
I
OS
Input Offset Current (Notes 4, 7)
Input Noise Voltage
L
T
C6241,
L
T
C6242
L
T
C6240
pA
pA
75
1
75
pA
pA
0.1Hz to 10Hz
nV
P-P
624012fe
8
LTC6240/LTC6241/LTC6242
ELECTRICAL CHARACTERISTICS
(
L
T
C6240HVC/I,
L
T
C6241HVC/I,
L
T
C6242HVC/I) The
l
denotes the
specifications which apply over the full operating temperature range, otherwise specifications are at T
A
= 25°C. V
S
= 5
V
,
0
V
,
V
CM
= 0V
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
7
MAX
UNITS
nV/√
Hz
fA/√
Hz
Ω
e
n
Input Noise Voltage Density
Input Noise Current Density (Note 8)
Input Resistance
f = 1kHz
10
i
0.56
n
12
R
Common Mode
f = 100kHz
10
IN
IN
C
Input Capacitance
Differential Mode
Common Mode
3.5
3
pF
pF
l
l
V
Input Voltage Range
Guaranteed by CMRR
–5
83
3.5
V
CM
CMRR
Common Mode Rejection
–5V ≤ V
≤ 3.5V
105
95
dB
CM
CMRR Match
Channel-to-Channel (Note 5)
76
dB
l
A
VOL
Large Signal Voltage Gain
V =
–3.5V to 3.5V
O
R =
10k
775
600
500
2700
V/mV
V/mV
V/mV
L
l
l
0°C to 70°C
–40°C to 85°C
R =
1k
150
90
75
360
V/mV
V/mV
V/mV
L
l
l
0°C to 70°C
–40°C to 85°C
l
l
l
V
V
Output Voltage Swing Low (Note 9)
Output Voltage Swing High (Note 9)
Power Supply Rejection
No Load
15
45
30
75
mV
mV
mV
OL
I
I
= 1mA
SINK
SINK
= 10mA
360
550
l
l
l
No Load
15
45
360
30
75
550
mV
mV
mV
OH
I
I
= 1mA
SOURCE
= 10mA
SOURCE
l
PSRR
V =
2.8V to 11
V
, V
=
0
.2V
S
85
110
106
dB
CM
PSRR Match
Channel-to-Channel (Note 5)
l
l
l
82
2.8
15
dB
V
Minimum Supply Voltage (Note 10)
Short-Circuit Current
I
I
35
mA
SC
Supply Current per Amplifier
L
T
C6241,
L
T
C6242
0°C to 70°C
–40°C to 85°C
2.5
3.2
3.3
3.7
mA
mA
mA
S
l
l
L
T
C6240
0°C to 70°C
–40°C to 85°C
2.7
3.3
3.4
3.8
mA
mA
mA
l
l
l
l
l
GBW
SR
Gain Bandwidth Product
Slew Rate (Note 11)
Frequency = 20kHz, R
= 1kΩ
13
5.5
18
10
MHz
V/μs
MHz
ns
L
A =
–2, R
= 1kΩ
V
L
FPBW
Full Power Bandwidth (Note 12)
Settling Time
V
OUT
= 3V
, R
= 1kΩ
0.58
1.06
900
P-P
L
t
s
V =
2
V
, A
=
–
1, R
= 1kΩ, 0.1%
STEP V
L
624012fe
9
LTC6240/LTC6241/LTC6242
ELECTRICAL CHARACTERISTICS
(
L
T
C6240H/
L
T
C6240HVH,
L
T
C6241H/
L
T
C6241HVH,
L
T
C6242H/
L
T
C6242HVH)
The
l
denotes the specifications which apply from –40°C to 125°C, otherwise specifications are at T
A
= 25°C. V
S
= 5
V
,
0
V
,
V
CM
= 2.5V
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Input Offset Voltage (Note 4)
L
T
C6241 S8
40
125
400
μV
μV
OS
l
l
l
l
L
T
C6242 GN
L
T
C6240
50
50
40
50
150
400
μV
μV
175
450
μV
μV
V
Match Channel-to-Channel (Note 5)
L
T
C6241 S8
160
400
μV
μV
OS
L
T
C6242 GN
185
400
μV
μV
l
l
TC V
Input Offset Voltage Drift (Note 6)
Input Bias Current (Notes 4, 7)
0.7
0.2
2.5
μV/°C
OS
I
B
L
T
C6241,
L
T
C6242
L
T
C6240
pA
nA
l
l
l
1.5
0.2
0.2
0.2
1
2.5
pA
nA
I
OS
Input Offset Current (Notes 4, 7)
L
T
C6241,
L
T
C6242
L
T
C6240
pA
pA
150
1
750
pA
pA
l
l
l
V
Input Voltage Range
Guaranteed by CMRR
0
3.5
V
CM
CMRR
Common Mode Rejection
0V ≤ V
≤ 3.5V
78
dB
CM
CMRR Match
l
l
l
Channel-to-Channel (Note 5)
74
dB
A
VOL
Large Signal Voltage Gain
V =
1V to 4V
O
R =
10k to V
/2
425
200
1600
215
V/mV
V/mV
L
S
V =
1.5V to 3.5V
O
R =
1k to V
/2
90
40
V/mV
V/mV
L
S
l
l
l
V
V
Output Voltage Swing Low (Note 9)
Output Voltage Swing High (Note 9)
Power Supply Rejection
No Load
SINK
SINK
30
85
mV
mV
mV
OL
I
I
= 1mA
= 5mA
325
l
l
l
No Load
SOURCE
SOURCE
30
85
325
mV
mV
mV
OH
I
I
= 1mA
= 5mA
l
PSRR
V =
2.8V to 6
V
, V
=
0
.2V
S
78
dB
CM
PSRR Match
l
l
l
Channel-to-Channel (Note 5)
74
2.8
15
dB
V
Minimum Supply Voltage (Note 10)
Short-Circuit Current
I
I
mA
SC
Supply Current per Amplifier
L
T
C6241,
L
T
C6242
L
T
C6240
1.8
2
2.2
2.4
mA
mA
S
l
2.4
2.8
mA
mA
l
l
l
l
GBW
SR
Gain Bandwidth Product
Slew Rate (Note 11)
Frequency = 20kHz, R
= 1kΩ
12
4.5
MHz
V/μs
MHz
L
A =
–2, R
= 1kΩ
V
L
FPBW
Full Power Bandwidth (Note 12)
V
OUT
= 3V
, R
= 1kΩ
0.48
P-P
L
624012fe
10
LTC6240/LTC6241/LTC6242
ELECTRICAL CHARACTERISTICS
(
L
T
C6240H/
L
T
C6240HVH,
L
T
C6241H/
L
T
C6241HVH,
L
T
C6242H/
L
T
C6242HVH)
The
l
denotes the specifications which apply from –40°C to 125°C, otherwise specifications are at T
A
= 25°C. V
S
= 3
V
,
0
V
,
V
CM
= 1.5V
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Input Offset Voltage (Note 4)
L
T
C6241 S8
40
175
400
μV
μV
OS
l
l
l
l
L
T
C6242 GN
L
T
C6240
60
50
40
60
200
400
μV
μV
200
450
μV
μV
V
Match Channel-to-Channel (Note 5)
L
T
C6241 S8
200
400
μV
μV
OS
L
T
C6242 GN
225
400
μV
μV
l
l
TC V
Input Offset Voltage Drift (Note 6)
Input Bias Current (Notes 4, 7)
0.7
0.2
2.5
μV/°C
OS
I
B
L
T
C6241,
L
T
C6242
L
T
C6240
pA
nA
l
l
l
1.5
0.2
0.2
0.2
1
2.5
pA
nA
I
Input Offset Current (Notes 4, 7)
L
T
C6241,
L
T
C6242
L
T
C6240
pA
pA
OS
150
1
750
pA
pA
l
l
l
V
Input Voltage Range
Guaranteed by CMRR
0
1.5
V
CM
CMRR
Common Mode Rejection
0V ≤ V
≤ 1.5V
75
dB
CM
CMRR Match
Channel-to-Channel (Note 5)
l
74
dB
A
VOL
Large Signal Voltage Gain
V =
1V to 2V
O
R =
10k to V
/2
140
65
600
V/mV
V/mV
L
S
l
l
l
V
V
Output Voltage Swing Low (Note 9)
Output Voltage Swing High (Note 9)
Power Supply Rejection
No Load
SINK
30
mV
mV
OL
I
= 1mA
130
l
l
No Load
SOURCE
30
130
mV
mV
OH
I
= 1mA
l
PSRR
V =
2.8V to 6
V
, V
=
0
.2V
S
78
dB
CM
PSRR Match Channel-to-Channel
(Note 5)
l
l
l
74
2.8
2.5
dB
V
Minimum Supply Voltage (Note 10)
Short-Circuit Current
I
I
mA
SC
S
Supply Current per Amplifier
L
T
C6241,
L
T
C6242
L
T
C6240
1.4
1.5
1.7
1.9
mA
mA
l
1.9
2.1
mA
mA
l
l
GBW
Gain Bandwidth Product
Frequency = 20kHz, R
= 1kΩ
10
MHz
L
624012fe
11
LTC6240/LTC6241/LTC6242
ELECTRICAL CHARACTERISTICS
(
L
T
C6240HVH/
L
T
C6241HVH/
L
T
C6242HVH) The
l
denotes the specifications
which apply from –40°C to 125°C, otherwise specifications are at T
A
= 25°C. V
S
= 5
V
,
V
CM
= 0V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Input Offset Voltage (Note 4)
L
T
C6241 S8
50
175
400
μV
μV
OS
l
l
l
l
L
T
C6242 GN
L
T
C6240
60
60
50
60
200
400
μV
μV
250
450
μV
μV
V
Match Channel-to-Channel (Note 5)
L
T
C6241 S8
200
400
μV
μV
OS
L
T
C6242 GN
225
400
μV
μV
l
l
TC V
Input Offset Voltage Drift (Note 6)
Input Bias Current (Notes 4, 7)
0.7
0.5
2.5
μV/°C
OS
I
L
T
C6241,
L
T
C6242
L
T
C6240
pA
nA
B
l
l
l
1.5
0.5
0.2
0.2
1
2.5
pA
nA
I
OS
Input Offset Current (Notes 4, 7)
L
T
C6241,
L
T
C6242
L
T
C6240
pA
pA
150
1
750
pA
pA
l
l
l
V
Input Voltage Range
Guaranteed by CMRR
–5
80
3.5
V
CM
CMRR
Common Mode Rejection
–5V ≤ V
≤ 3.5V
dB
CM
CMRR Match
Channel-to-Channel (Note 5)
l
76
dB
A
VOL
Large Signal Voltage Gain
V =
–3.5V to 3.5V
O
L
R =
10k
775
350
2700
360
V/mV
V/mV
l
l
R =
1k
L
150
60
V/mV
V/mV
l
l
l
V
V
Output Voltage Swing Low (Note 9)
Output Voltage Swing High (Note 9)
Power Supply Rejection
No Load
30
85
mV
mV
mV
OL
I
I
= 1mA
SINK
SINK
= 10mA
600
l
l
l
No Load
30
85
600
mV
mV
mV
OH
I
I
= 1mA
SOURCE
SOURCE
= 10mA
l
PSRR
V =
2.8V to 11
V
, V
=
0
.2V
S
83
dB
CM
PSRR Match
l
l
l
Channel-to-Channel (Note 5)
82
2.8
15
dB
V
Minimum Supply Voltage (Note 10)
Short-Circuit Current
I
I
mA
SC
Supply Current per Amplifier
L
T
C6241,
L
T
C6242
L
T
C6240
2.5
2.7
3.2
3.7
mA
mA
S
l
3.3
3.8
mA
mA
l
l
l
l
GBW
SR
Gain Bandwidth Product
Slew Rate (Note 11)
Frequency = 20kHz, R
= 1kΩ
12
5
MHz
V/μs
MHz
L
A =
–2, R
= 1kΩ
V
L
FPBW
Full Power Bandwidth (Note 12)
V
OUT
= 3V
, R
= 1kΩ
0.53
P-P
L
624012fe
12
LTC6240/LTC6241/LTC6242
ELECTRICAL CHARACTERISTICS
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 6:
This parameter is not 100% tested.
Note 7:
Bias current at T
= 25°C is 100% tested and guaranteed for the
A
L
T
C6240 in the S8 package. The
L
T
C6240S5,
L
T
C6241 and
L
T
C6242 are
expected to achieve the same performance as the
L
T
C6240S8. All parts are
guaranteed to meet specifications over temperature.
1/2
Note 2:
A heat sink may be required to keep the junction temperature
below the absolute maximum rating when the output is shorted
indefinitely.
Note 8:
Current noise is calculated from the formula: i
= (2qI
) where
n
B
–19
q = 1.6
×
10 coulomb.
The noise of source resistors up to 50GΩ
dominates the contribution of current noise. See also Typical Performance
Characteristics curve Noise Current vs Frequency.
Note 3:
The
L
T
C6240C/
L
T
C6240HVC/
L
T
C6241C/
L
T
C6241HVC,
L
T
C6242C/
L
T
C6242HVC are guaranteed to meet specified performance from 0°C to
70°C. They are designed, characterized and expected to meet specified
performance from –40°C to 85°C, but are not tested or QA sampled at
these temperatures. The
L
T
C6240I/
L
T
C6240HVI,
L
T
C6241I/
L
T
C6241HVI,
L
T
C6242I/
L
T
C6242HVI are guaranteed to meet specified performance
from –40°C to 85°C. All versions of the
L
T
C6240H/
L
T
C6241H/
L
T
C6242H
are guaranteed to meet specified performance from –40°C to 125°C.
Note 4:
ESD (Electrostatic Discharge) sensitive device. ESD protection
devices are used extensively internal to the
L
T
C6240/
L
T
C6241/
L
T
C6242;
howeve
r
,
h
igh electrostatic discharge can damage or degrade the device.
Use proper ESD handling precautions.
Note 5:
Matching parameters are the difference between the two amplifiers
A and D and between B and C of the
L
T
C6242; between the two amplifiers
of the
L
T
C6241. CMRR and PSRR match are defined as follows: CMRR
and PSRR are measured in μV/V on the matched amplifiers. The difference
is calculated between the matching sides in μV/
V
.
T
he result is converted
to dB.
Note 9:
Output voltage swings are measured between the output and
power supply rails.
Note 10:
Minimum supply voltage is guaranteed by the power supply
rejection ratio test.
Note 11:
Slew rate is measured in a gain of –2 with R
= 1k and R
=
500Ω. On the
L
T
C6240/
L
T
C6241/
L
T
C6242, V
= 2.5
V
,
V
i
s
1V and
F
G
S
IN
V
OUT
slew rate is measured between –1V and +1
V
.
O
n the
L
T
C6240HV/
L
T
C6241HV/
L
T
C6242H
V
, V
i
s 2V
and V
slew rate is measured
IN
OUT
between –2V and +2
V
.
Note 12:
Full-power bandwidth is calculated from the slew rate:
FPBW = SR/πV
.
P-P
624012fe
13
LTC6240/LTC6241/LTC6242
TYPICAL PERFORMANCE CHARACTERISTICS
V
OS
Temperature Coefficient
V
OS
Distribution
L
T
C6241
V
OS
Distribution
L
T
C6241
Distribution
L
T
C6241
90
80
70
60
50
40
30
20
10
16
14
12
10
8
120
100
80
60
40
20
0
V
=
2.5V
V = 2.5V
S
V
= 2.5V
S
S
SO-8 PACKAGE
2 LOTS
DD PACKAGE
–55°C TO 125°C
6
4
2
0
0
–70 –50 –30 –10
10
30
50
70
–1.0 –0.6 –0.2
0.2 0.6 1.0 1.4 1.8
DISTRIBUTION (μV/°C)
–350 –250 –150
–50 50 150
250 350
INPUT OFFSET VOLTAGE (μV)
INPUT OFFSET VOLTAGE (μV)
6241 G01
6241 G03
6241 G02
V
OS
Temperature Coefficient
Distribution
L
T
C6240
V
OS
Distribution
L
T
C6240
Supply Current vs Supply Voltage
35
30
25
20
15
10
5
18
16
14
12
10
8
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
=
2.5V
V
V
= 5V, 0
= 2.5V
S
S
CM
2 LOTS
T
= 25°C
A
–40°C TO 125°C
SO-8 AND SOT23
PACKAGES
T
= –55°C
A
T
= 125°C
A
6
4
2
0
0
8
12
0
2
4
6
10
–110 –90
–70 –50 –30 –10
10 30 50 70
–0.6 –0.2
0.2
0.6
1.0
1.4
1.8
TOTAL SUPPLY VOLTAGE (V)
INPUT OFFSET VOLTAGE (μV)
DISTRIBUTION (μV/°C)
6241 G04
6241 G05
6241 G06
Offset Voltage
vs Input Common Mode Voltage
Input Bias Current
vs Common Mode Voltage
Input Bias Current
vs Common Mode Voltage
1000
100
10
700
600
500
400
300
200
100
0
300
250
200
150
100
50
V
= 5V, 0V
V =
5V, 0V
S
V
= 5V, 0V
S
S
T
= 125°C
A
T
= 125°C
= 25°C
A
T
= 25°C
A
T
= 125°C
T
A
A
0
–50
–100
–150
–200
–250
–300
T
= 85°C
T
= –55°C
A
A
–100
–200
–300
–400
1
T
= 85°C
A
T
= 25°C
A
0.1
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
–0.8 –0.6 –0.4 –0.2
0
0.2 0.4 0.6 0.8 1.0
–0.5
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
COMMON MODE VOLTAGE (V)
COMMON MODE VOLTAGE (V)
INPUT COMMON MODE VOLTAGE (V)
6241 G08
6241 G09
6241 G07
624012fe
14
LTC6240/LTC6241/LTC6242
TYPICAL PERFORMANCE CHARACTERISTICS
Output Saturation Voltage
vs Load Current (Output High)
Output Saturation Voltage
vs Load Current (Output Low)
Input Bias Current vs Temperature
1000
100
10
10
1
10
1
V
= V
/2
S
V
= 5V, 0V
V
= 5V, 0V
CM
S
S
T
= 25°C
A
T
= 25°C
A
V
= 10V
S
T
= 125°C
A
T
= 125°C
A
V
= 5V
S
0.1
T
= –55°C
A
T
= –55°C
A
0.1
0.01
1
0.01
0.001
0.1
25 35 45 55 65 75 85 95
105 115 125
0.1
1
10
100
0.1
1
10
100
TEMPERATURE (°C)
LOAD CURRENT (mA)
LOAD CURRENT (mA)
6241 G10
6241 G11
6241 G12
Gain Bandwidth and Phase
Margin vs Temperature
Gain Bandwidth and Phase
Margin vs Supply Voltage
Open Loop Gain vs Frequency
70
60
50
40
30
80
70
60
50
40
30
20
10
0
120
100
80
70
60
50
40
C
= 5pF
= 1k
C
R
V
= 5pF
T
= 25°C
= 5pF
= 1k
L
L
L
L
A
L
L
PHASE
V
=
5V
R
= 1k
C
S
= V
/2
R
CM
S
PHASE MARGIN
60
PHASE MARGIN
V
= 5V
V
=
1.5V
S
GAIN
40
S
V
=
1.5V
5V
S
40
30
20
10
0
20
30
20
10
0
0
V
=
S
V
=
5V
–20
–40
–60
–80
S
GAIN BANDWIDTH
V
= 1.5V
S
GAIN BANDWIDTH
V
=
1.5V
S
–10
–20
–55 –35 –15
5
25 45 65 85
105 125
10k
100k
1M
FREQUENCY (Hz)
10M
100M
0
2
4
6
8
10
12
TEMPERATURE (°C)
TOTAL SUPPLY VOLTAGE (V)
6241 G13
6241 G14
6241 G15
Common Mode Rejection Ratio
vs Frequency
Slew Rate vs Temperature
Output Impedance vs Frequency
20
18
16
14
12
10
8
100
90
80
70
60
50
40
30
20
10
0
10k
1k
T
= 25°C
= 2.5V
A
= –2
T =
25°C
A
V = 2.5V
S
A
S
V
F
V
R
= 1k, R
= 500ꢀ
G
CONDITIONS: SEE NOTE 12
100
10
V
=
S
5V FALLING
5V RISING
S
A
= 10
V
A =
2
V
V
=
=
2.5V FALLING
2.5V RISING
S
V
=
1
A
= 1
V
V
S
0.10
0.01
6
4
–10
–55 –35 –15
5
25 45 65 85
105 125
10k
100k
1M
10M
100M
10k
100k
1M
10M
TEMPERATURE (°C)
FREQUENCY (Hz)
FREQUENCY (Hz)
6241 G16
6241 G18
6241 G17
624012fe
15
LTC6240/LTC6241/LTC6242
TYPICAL PERFORMANCE CHARACTERISTICS
Power Supply Rejection Ratio
Channel Separation vs Frequency
vs Frequency
Input Capacitance vs Frequency
0
–10
90
80
70
60
50
40
30
20
10
0
16
14
12
10
8
T
V
A
= 25°C
T
= 25°C
= 2.5V
V
= 1.5V
A
S
V
A
S
S
=
2.5V
V
= 1
–20
C
–30
CM
–40
–50
–60
POSITIVE SUPPLY
–70
6
–80
–90
4
NEGATIVE SUPPLY
–100
–110
–120
2
0
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
6241 G19
6241 G20
6241 G21
Output Short-Circuit Current
vs Power Supply Voltage
Minimum Supply Voltage
Open Loop Gain
120
100
80
60
40
20
0
100
80
50
40
T
= 25°C
= 3V, 0V
V
= V
/2
S
A
S
CM
V
T
= –55°C
A
60
SINKING
30
T
T
= 125°C
= 125°C
A
A
40
20
T
A
= 25°C
A
20
10
R
= 100k
= 10k
L
0
T
= 25°C
0
A
–20
–40
–60
–80
–100
R
–10
–20
–30
–40
–50
L
T
= –55°C
T
= 125°C
A
SOURCING
T
= –55°C
A
0
0.5
1.0
1.5
2.0
2.5
3.0
0
1
2
3
4
5
6
7
8
9
10
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT VOLTAGE (V)
TOTAL SUPPLY VOLTAGE (V)
POWER SUPPLY VOLTAGE (
V)
6241 G24
6241 G22
6241 G23
Open Loop Gain
Open Loop Gain
Offset Voltage vs Output Current
120
100
80
500
400
100
80
T
= 25°C
= 5V, 0V
V
= 5V
T
= 25°C
= 5V
A
S
S
A
S
V
V
300
T
= 125°C
A
60
200
40
T
= 25°C
100
A
60
R
= 10k
= 1k
L
R
= 10k
= 1k
L
0
20
40
T
= –55°C
A
–100
–200
–300
–400
–500
R
L
0
R
L
20
–20
–40
–60
0
–20
0
1
2
3
4
5
–50 –40 –30 –20 –10
0
10 20 30 40 50
–5 –4 –3 –2 –1
0
1
2
3
4
5
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
OUTPUT VOLTAGE (V)
6241 G25
6241 G27
6241 G26
624012fe
16
LTC6240/LTC6241/LTC6242
TYPICAL PERFORMANCE CHARACTERISTICS
Warm-Up Drift vs Time
0.1Hz to 10Hz Voltage Noise
V =
5V, 0V
S
Noise Voltage vs Frequency
25
20
15
10
5
60
50
40
30
20
10
0
T
= 25°C
T
A
= 25°C
2.5V
= 0V
A
V
V
=
S
CM
V
S
=
5V
S
V
=
2.5V
V
=
1.5V
0
S
–5
0
5
10 15 20 25 30 35 40 45 50 55 60
1
10
100
1k
10k
100k
TIME (1s/DIV)
TIME AFTER POWER UP (s)
FREQUENCY (Hz)
6241 G30
6241 G28
6241 G29
Series Output Resistance and
Overshoot vs Capacitive Load
Minimum Output Series
Resistance vs Capacitive Load
Noise Current vs Frequency
1000
100
10
1000
100
10
60
50
40
30
20
10
0
T
V
V
= 25°C
V
=
2.5V
75pF
A
S
S
=
2.5V
= 0V
<30% OVERSHOOT
CM
1k
1k
R
–
+
S
C
L
R
= 10ꢀ
S
R
= 50ꢀ
S
1
1
V
A
=
= –1
2.5V
S
V
0.1
0.1
10
100
CAPACITIVE LOAD (pF)
1000
100
1k
10k
100k
10μF
10pF 100pF
1000pF 0.01μF
0.1μF 1μF
FREQUENCY (Hz)
CAPACITIVE LOAD
6241 G31
6241 G33
6241 G32
Settling Time vs Output Step
(Non-Inverting)
Settling Time vs Output Step
(Inverting)
Series Output Resistance and
Overshoot vs Capacitive Load
3.0
2.5
2.0
1.5
1.0
0.5
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
60
50
40
30
20
10
0
T
V
A
= 25°C
A
T
V
A
= 25°C
75pF
A
S
V
=
5V
=
5V
S
V
1k
= –1
= 1
1k
V
–
+
–
+
V
OUT
500ꢀ
1k
IN
R
–
+
S
V
V
OUT
1k
IN
1k
C
L
1mV
1mV
1mV
R
= 10ꢀ
S
10mV
R
= 50ꢀ
1mV
10mV
–4 –3 –2 –1
S
10mV
10mV
3
V
A
=
= –2
2.5V
S
V
–4 –3 –2 –1
0
1
2
3
4
0
1
2
4
10
100
CAPACITIVE LOAD (pF)
1000
OUTPUT STEP (V)
OUTPUT STEP (V)
6241 G36
6241 G35
6241 G34
624012fe
17
LTC6240/LTC6241/LTC6242
TYPICAL PERFORMANCE CHARACTERISTICS
Maximum Undistorted Output
Signal vs Frequency
Distortion vs Frequency
Distortion vs Frequency
10
9
8
7
6
5
4
3
2
1
–30
–40
–50
–60
–70
–80
–90
–100
–30
–40
–50
–60
–70
–80
–90
–100
V
A
V
=
2.5V
V
A
V
=
5V
S
V
S
V
= 1
= 1
= 2V
= 2V
OUT
P-P
OUT
P-P
A
= –1
V
A
= +2
V
R
= 1k, 2ND
L
R
= 1k, 2ND
L
R
= 1k, 3RD
L
R
= 1k, 3RD
L
T
= 25°C
A
S
V
=
5V
HD ,
HD <
–40dBc
2
3
10k
100k
1M
10M
10k
100k
1M
10M
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
6241 G37
6241 G38
6241 G39
Distortion vs Frequency
Distortion vs Frequency
Small Signal Response
–30
–40
–50
–60
–70
–80
–90
–100
–30
–40
–50
–60
–70
–80
–90
–100
V
A
V
=
2.5V
V
A
V
=
5V
S
V
S
V
= 2
= 2
= 2V
= 2V
OUT
P-P
OUT
P-P
R
= 1k, 2ND
0V
L
R
L
= 1k, 2ND
R
= 1k, 3RD
L
R
= 1k, 3RD
1M
L
6241 G42
V
A
=
2.5V
S
V
= 1
R
= ∞
L
10k
100k
10M
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
6241 G40
6241 G41
Large Signal Response
Large Signal Response
Output Overdrive Recovery
0V
V
IN
0V
0V
(1V/DIV)
0V
V
OUT
(2V/DIV)
6241 G43
6241 G44
6241 G45
V
A
=
5V
V
A
=
= –1
= 1k
2.5V
V
A
=
2.5V
500ns/DIV
S
V
L
S
V
L
S
V
L
= 1
= 3
R
= ∞
R
R
= ∞
624012fe
18
LTC6240/LTC6241/LTC6242
APPLICATIONS INFORMATION
Amplifier Characteristics
The amplifier input bias current is the leakage current of
thes
e
E
S
D
d
iodes
.
T
hi
s
l
eakag
e
i
s
a
f
unctio
n
o
f
t
h
e
t
empera-
ture and common mode voltage of the amplifie
r
,
a
s shown
in the Typical Performance Characteristics curves.
Figure 1 is a simplified schematic of the amplifie
r
,
w
hich
has a pair of low noise input transistors M1 and M2. A
simple folded cascode Q1, Q2 and R1, R2 allow the input
stage to swing to the negative rail, while performing level
shift to the differential drive generato
r
.
L
ow offset voltage
is accomplished by laser trimming the input stage.
Noise
The
L
T
C6240/
L
T
C6241/
L
T
C6242 exhibit exceptionally
low 1/f noise in the 0.1Hz to 10Hz region. This 550nV
P-P
Capacitor C1 reduces the unity cross frequency and im-
proves the frequency stability without degrading the gain
bandwidth of the amplifie
r
.
C
apacitor CM sets the overall
amplifier gain bandwidth. The differential drive generator
supplies signals to transistors M3 and M4 that swing the
output from rail-to-rail.
noise allows these op amps to be used in a wide variety
of high impedance low frequency applications, where
zero-drift amplifiers might be inappropriate due to their
charge injection.
I
n
t
h
e
f
requenc
y
r
egio
n
a
bov
e
1
kH
z
t
h
e
L
T
C6240/
L
T
C6241/
L
T
C6242 also show good noise voltage performance. In
this frequency region, noise can easily be dominated by
the total source resistance of the particular application.
Specifically, these amplifiers exhibit the noise of a 3.1kΩ
resisto
r
,
m
eaning it is desirable to keep the source and
The photo of Figure 2 shows the output response to an
input overdrive with the amplifier connected as a voltage
followe
r
.
I
f the negative going input signal is less than
–
a diode drop below V , no phase inversion occurs. For
–
input signals greater than a diode drop below V
, limit the
feedbac
k
r
esistanc
e
a
t
o
r
b
elo
w
t
hi
s
v
alue
,
i
.e
.
R +R
|
|R
S
G
FB
current to 3mA with a series resistor R
to avoid phase
S
≤ 3.1kΩ. Above this total source impedance, the noise
inversion.
voltage is not dominated by the amplifie
r
.
ESD
Noise current can be estimated from the expression i
=
n
–19
√
2qI
, where q = 1.6 • 10
coulombs. Equating √
4kTR
Δ
f
B
Th
e
L
T
C6240/
L
T
C6241/
L
T
C624
2
h
av
e
r
everse-biase
d
E
SD
protection diodes on all input and outputs as shown in
Figure 1. If these pins are forced beyond either supply,
unlimited current will flow through these diodes. If the
current is transient and limited to one hundred milliamps
or less, no damage to the device will occu
r
.
an
d
R
√
2qI
Δ
f
show
s
t
ha
t
f
o
r
s
ourc
e
r
esistor
s
b
elo
w
5
0GΩ
B
the amplifier noise is dominated by the source resistance.
See the Typical Performance Characteristics curve Noise
Current vs Frequency.
V
=
DD
+2.5V
+
V
I
TAIL
M3
CM
–
+
V
V
+
V
V
=
SS
–2.5V
DESD1
+
DESD2
DESD5
DIFFERENTIAL
DRIVE
GENERATOR
V
O
V
M1
M2
IN
V
AND V
OF FOLLOWER WITH LARGE INPUT OVERDRIVE
IN
OUT
DESD6
CLAMP
C1
–
–
V
V
–
+2.5V
V
IN
Q1
Q2
R
S
BIAS
M4
+
DESD3
DESD4
V
OUT
LTC6240
V
IN
–
+
V
V
–
R1
R2
–
V
–2.5V
6241 F01
6241 F02
Figure 1. Simplified Schematic
Figure 2. Unity Gain Follower Test Circuit
624012fe
19
LTC6240/LTC6241/LTC6242
APPLICATIONS INFORMATION
Proprietary design techniques are used to obtain simulta-
neous low 1/f noise and low input capacitance. Low input
capacitance is important when the amplifier is used with
high value source and feedback resistors. High frequency
Half the Noise
The circuit shown in Figure 3 can be used to achieve even
lower noise voltage. By paralleling 4 amplifiers the noise
voltage can be lowered by √
4
, or half as much noise. The
–
noise from the amplifier tail current source, I
in Fig-
TAIL
√ comes
about from an RMS summing of uncorrelated
ure 1, couples through the input capacitance and appears
across these large source and feedback resistors. As an
example, the photodiode amplifier of Figure 15 on the last
page of this data sheet shows the noise results from the
L
T
C6241 and the results of a competitive CMOS amplifie
r
.
The
L
T
C6241 output is the ideal noise of a 1MΩ resistor
at room temperature, 130nV√
Hz
.
noise sources. This circuit maintains extremely high input
resistance, and has a 250Ω output resistance. For lower
output resistance, a buffer amplifier can be added without
influencing the noise.
Stability
The good noise performance of these op amps can be at-
tribute
d
t
o
l
arg
e
i
npu
t
d
evice
s
i
n
t
h
e
d
ifferentia
l
p
ai
r
.
A
bove
several hundred kilohertz, the input capacitance rises and
can cause amplifier stability problems if left unchecked.
+2.5
+
1k
1/4
LTC6242
–
When the feedback around the op amp is resistive (R ), a
F
–2.5
pole will be created with R
, the source resistance, source
F
capacitance (R
, C
), and the amplifier input capacitance.
S
S
1k
10ꢀ
In low gain configurations and with R
and R
in even
F
S
the kilohm range (Figure 4), this pole can create excess
phase shift and possibly oscillation. A small capacitor C
F
+
1k
1/4
in parallel with R
eliminates this problem.
F
LTC6242
–
Low Noise Single-Ended Input to Differential Output
Amplifier
V
V
O
IN
1k
10ꢀ
10ꢀ
10ꢀ
The circuit on the first page of the data sheet is a low noise
single-ended input to differential output amplifie
r
,
w
ith a
200k input impedance. The very low input bias current
of the
L
T
C6241 allows for these large input and feedback
resistors
.
T
h
e
2
00
k
r
esistors
,
R
1
a
n
d
R
2
,
a
lon
g
w
it
h
C
1
a
nd
C2 set the –3dB bandwidth to 80kHz. Capacitor C3 is used
to cancel effects of input capacitance, while C4 adds phase
lead to compensate the phase lag of the second amplifie
r
.
+
1k
1/4
LTC6242
–
1k
C
F
+
1k
1/4
LTC6242
R
F
–
–
+
C
IN
OUTPUT
R
C
S
S
1k
6241 F04
6241 F03
Figure 3. Parallel Amplifier Lowers Noise by 2x
Figure 4. Compensating Input Capacitance
624012fe
20
LTC6240/LTC6241/LTC6242
APPLICATIONS INFORMATION
The op amp’s good input offset voltage match and low
inpu
t
b
ia
s
c
urren
t
m
ean
s
t
ha
t
t
h
e
t
ypica
l
d
ifferentia
l
o
utput
offset voltage is less than 40μ
V
. A
n
oise spectrum plot of
the differential output is shown in Figure 5.
The guard ring should extend as far as necessary to shield
the high impedance signal from any and all leakage paths.
Figure 6 shows the use of a guard ring on the
L
T
C6241 in
a unity gain configuration. In this case the guard ring is
connecte
d
t
o
t
h
e
o
utpu
t
a
n
d
i
s
s
hieldin
g
t
h
e
h
ig
h
i
mpedance
–
noninverting input from V
. Figure 7 shows the inverting
140
V
=
2.5V
S
A
gain configuration.
T
= 25°C
120
100
80
60
40
20
0
–3dB BW = 80kHz
A Digitally Programmable AC Difference Amplifier
The
L
T
C6241 configured as a difference amplifie
r
,
c
an be
combined with a programmable gain amplifier (PGA) to
obtain a low noise high speed programmable difference
amplifie
r
.
F
igure 8 shows the
L
T
C6241 based as a single-
supply AC amplifie
r
.
O
ne
L
T
C6241 op amp is used at the
circuit’
s
i
npu
t
a
s
a
s
tandar
d
f
ou
r
r
esisto
r
d
ifferenc
e
a
mplifie
r
.
0
10 20 30 40 50 60 70 80 90
100
FREQUENCY (kHz)
LTC6241 S8
6241 F05
+
OUT
Figure 5. Differential Output Noise
NO SOLDER MASK
NO LEAKAGE
CURRENT
OVER THE GUARD RING
–
+
IN
IN
R
Achieving Low Input Bias Current
The DD package is leadless and makes contact to the PCB
beneath the package. Solder flux used during the attach-
ment of the part to the PCB can create leakage current
paths and can degrade the input bias current performance
o
f
t
h
e
p
art. Al
l
i
nput
s
a
r
e
s
usceptibl
e
b
ecaus
e
t
h
e
b
ackside
LEAKAGE
CURRENT
–
GUARD
RING
V
LTC6241 F06
–
paddle is connected to V
internally. As the input voltage
–
Figure 6. Sample Layout. Unity Gain Configuration, Using Guard
Ring to Shield High Impedance Input from Board Leakage
changes or if V
changes, a leakage path can be formed
and alter the observed input bias current. For lowest bias
current
,
u
s
e
t
h
e
L
T
C6240/
L
T
C624
1
i
n
t
h
e
S
O-
8
a
n
d
p
rovide
a guard ring around the inputs that are tied to a potential
near the input voltage.
LTC6241 S8
+
OUT
R
Layout Considerations and a PCB Guard Ring
R
–
IN
I
n
h
ig
h
s
ourc
e
i
mpedanc
e
a
pplication
s
s
uc
h
a
s
p
H
p
robes,
photodiodes, strain gauges, et cetera, the low input bias
current of these parts requires a clean board layout to
minimiz
e
a
dditiona
l
l
eakag
e
c
urren
t
i
nt
o
a
h
ig
h
i
mpedance
signal node. A mere 100GΩ of PC board resistance
between a 5V supply trace and an input trace adds 50pA
of leakage current, far greater then the input bias current
of the operational amplifie
r
. A
g
uard ring around the high
impedance input traces driven by a low impedance source
equa
l
t
o
t
h
e
i
npu
t
v
oltag
e
p
revent
s
s
uc
h
l
eakag
e
p
roblems.
V
IN
+
IN
GND
–
V
LTC6241 F07
Figure 7. Sample Layout. Inverting Gain Configuration, Using
Guard Ring to Shield High Impedance Input from Board Leakage
624012fe
21
LTC6240/LTC6241/LTC6242
APPLICATIONS INFORMATION
+
R3
contribute any significant error to the
L
T
6650 reference
voltage. The
L
T
6650 V
voltage has a maximum error
V
G2 G1 G0
0.1μF
REF
C1
8
7
6
5
R1
of 2%
with 1% resistors. The upper –3dB frequency of
the amplifier is set by resistor R3 and capacitor C1 and
is limited by the bandwidth of the PGA when operated at
a gain of 64. Capacitor C2 is equal to C1 and is added to
maintain good common mode rejection at high frequency.
The lower –3dB frequency is set by the integrator resistor
R7, capacitor C3, and the gain setting of the
L
T
C6910-2
PGA. This lower –3dB zero frequency is multiplied by the
PGA gain. The rail-to-rail output of the
L
T
C6910-2 PGA
allows for a maximum output peak-to-peak voltage equal
V1
LTC6910-2
OUT AGND
IN
–
V
4
+
1
2
3
1/2
LTC6241
V
OUT
–
100ꢀ
R7
R2
R4
C3
V2
C2
+
V
R1 = R2 = R3 = R4
R5
0.1μF
–
+
1/2
LTC6241
1000pF
to twice the V
voltage. At
the maximum gain setting of
REF
R6
64, the maximum peak-to-peak difference between inputs
20k
1
5
4
LT6650
V1 and V2 is equal to twice V
divided by 64.
REF
V
2
REF
1μF
1μF
Example Design:
Design a programmable gain AC differ-
enc
e
a
mplifie
r
,
w
it
h
a
b
andwidt
h
o
f
a
t
l
eas
t
1
0H
z
t
o
1
00kHz,
an input impedance equal to or greater than 100kΩ, and
an output DC reference equal to 1
V
.
1k
3
+
V
DIGITAL INPUTS
GAIN
G2 G1 GO
V
= (V1 – V2) GAIN + V
REF
OUT
a. Select input resistors R1, R2, R3 and R4 equal to
100k.
R5
R6
¥
´
¶
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
V
=
0.
4
•
+
1
µ
REF
¦
§
–1
–2
R5
=
10k •
5
• V
– 2
R
6
=
20k
ꢀ
ꢁ
REF
b. If the upper –3dB frequency is 100kHz then C1 = 1/(2π
• R2 • f3dB) = 1/(6.28 • 100kΩ • 100kHz) = 15pF (to
the nearest 5% value) and C2 = C1 = 15p
F
.
–4
–3d BANDWIDTH
=
1
f
– f
LOW
ꢀ
ꢁ
HIGH
–8
–16
–32
–64
GAIN
f
=
f
=
HIGH
LOW
2•
P
•
R
3
•
C
1
2 •
P
•
R
7
•
C
3
6241 F08
c. Select R7 equal to one 1M and set the lower –3dB
frequency to 10Hz at the highest PGA gain of 64, then
C3 = Gain/(2π • R7 • f3dB) = 64/(6.28 • 100kΩ • 10Hz)
= 1μ
F
.
L
ower gains settings will give a lower f3dB.
Figure 8. Wideband Difference Amplifier with High
Input Impedance and Digitally Programmable Gain
The low bias current and current noise of the
L
T
C6241
allow the use of high valued input resistors, 100k or
greater. Resistors R1, R2, R3 and R4 are equal and the
gain of the difference amplifier is one. An
L
T
C6910-2 PGA
amplifies the difference amplifier output with inverting
gains of –1, –2, –4, –8, –16, –32 and –64. The second
L
T
C6241 op amp is used as an integrator to set the DC
d. Calculate the value of R5 to set the
L
T
6650 reference
equal to 1V;
V
= 0.4(R5/R6 + 1), so R5 = R6(2.5V
– 1). For
REF
REF
R6 = 20kΩ, R5 = 30kΩ
With V
= 1V the maximum input difference voltage
REF
is equal to 2V/64 = 31.2m
V
.
output voltage equal to the
L
T
6650 reference voltage V
.
REF
The integrator drives the PGA analog ground to provide
a feedback loop, in addition to blocking any DC voltage
through the PGA. The reference voltage of the
L
T
6650
40nVpp Noise, 0.05μV/°C Drift, Chopped FET
Amplifier
+
can be set to a voltage from 400mV to V
– 350mV with
Figur
e
9
’
s
c
ircui
t
c
ombine
s
t
he 5
V
r
ail-to-rai
l
p
erformance
of the
L
T
C6241HV with a pair of extremely low noise JFETs
configured in a chopper based carrier modulation scheme
resistors R5 and R6. If R6 is 20k or less, the error due
to the
L
T
6650 op amp bias current is negligible. The low
voltage offset and drift of the
L
T
C6241 integrator will not
624012fe
22
LTC6240/LTC6241/LTC6242
APPLICATIONS INFORMATION
to achieve an extraordinarily low noise and low DC drift.
The performance of this circuit is suited for the demand-
ing transducer signal conditioning situations such as high
resolution scales and magnetic search coils.
with the input choppe
r
,
p
roper amplitude and polarity
information is presented to A2, the DC output amplifie
r
.
This stage integrates the square wave into a DC voltage,
providing the output. The output is divided down (R2 and
R1) and fed back to the input chopper where it serves as
a zero signal reference. Gain, in this case 1000, is set by
the R1-R2 ratio. Because A1 is AC coupled, its DC offset
and drift do not affect the overall circuit offset, resulting
in the extremely low offset and drift noted. The JFETs
have an input RC damper that minimizes offset voltage
contribution due to parasitic switch behavio
r
,
r
esulting in
the 1μV offset specification.
The
L
T
C1799’s output is divided down to form a 2-phase
925Hz square wave clock. This frequency, harmonically
unrelate
d
t
o
6
0Hz
,
p
rovide
s
e
xcellen
t
i
mmunit
y
t
o
h
armonic
beating or mixing effects which could cause instabilities.
S1 and S2 receive complementary drive, causing A1 to
see a chopped version of the input voltage. A1’s square
wave output is synchronously demodulated by S3 and
S4. Because these switches are synchronously driven
5V
–5V
+
–
TO LTC201 V
PIN
TO
L
T
C201 V
PIN
1μF
1μF
+
5V
5V
18.5kHz
+
V
74C90 ÷ 10
74C74 ÷ 2
DIV
OUT
5V
L
T
C1799
R
SET
Q
Q
925Hz
54.2k*
TO
Ø1
TO
Ø2
5V
Ø1
POINTS POINTS
8
898ꢀ**
898ꢀ**
30.1ꢀ
0.01μF
6
7
INPUT
Ø2
S1
S2
1μF
1
–
LSK389
1μF
11
10
A1
3
2
9
L
T
C6241HV
S3
S4
240k
499ꢀ**
–5V
Ø2
–
+
10M
A2
OUTPUT
L
T
C6241HV
14
15
16
Ø1
+
10k
1μF
R2
10k
* =
0.1% METAL FILM RESISTOR
** =
1% METAL FILM RESISTOR
NOISE = 40nV
0.1Hz TO 10Hz
P-P
R1
OFFSET = 1μV
DRIFT = 0.05μV/°C
R2
10ꢀ
=
L
T
C201 QUAD
=
+1
GAIN
10
= LSK389
= LINEAR INTEGRATED SYSTEMS
FREMON
T
,
C
A
9
OPEN-LOOP GAIN = 10
= 500pA
I
6241 F09
BIAS
Figure 9. Ultralow Noise Chopper Amplifier
624012fe
23
LTC6240/LTC6241/LTC6242
APPLICATIONS INFORMATION
Th
e
n
ois
e
m
easure
d
o
ve
r
a
5
0
s
econ
d
i
nterval
,
i
n
F
igur
e
1
0,
is 40nV in a 0.1Hz to 10Hz bandwidth.This low noise is at-
tributed to the input JFET’s die size and current density.
by the sensor is forced across the feedback capacitor
by the op amp action. Because the feedback capacitor
is 100 times smaller than the senso
r
,
i
t will be forced to
100 times what would have been the sensor’s open circuit
voltage. So the circuit gain is 100. The benefit of this ap-
proach is that the signal gain of the circuit is independent
of any cable capacitance introduced between the sensor
and the amplifie
r
.
H
ence this circuit is favored for remote
accelerometer
s
w
her
e
t
h
e
c
abl
e
l
engt
h
m
a
y
v
ary
.
D
ifficulties
with the circuit are inaccuracy of the gain setting with the
small capacito
r
,
a
nd low frequency cutoff due to the bias
resistor working into the small feedback capacito
r
.
20nV/DIV
6241 F10
5s/DIV
Figure 12 shows a noninverting amplifier approach. This
approach has many advantages. First of all, the gain is set
accurately with resistors rather than with a small capaci-
to
r
.
S
econd, the low frequency cutoff is dictated by the
bias resistor working into the large 770pF senso
r
,
r
ather
than into a small feedback capacito
r
,
f
or lower frequency
response. Third, the noninverting topology can be paral-
leled and summed (as shown) for scalable reductions in
voltage noise. The only drawback to this circuit is that the
parasiti
c
c
apacitanc
e
a
t
t
h
e
i
npu
t
r
educe
s
t
h
e
g
ai
n
s
lightly.
This circuit is favored in cases where parasitic input
capacitances such as traces and cables will be relatively
small and invariant.
Figure 10. Noise in a 0.1Hz to 10Hz Bandwidth
Low Noise Shock Sensor Amplifiers
Figures 11 and 12 show the amplifiers realizing two dif-
ferent approaches to amplifying signals from a capacitive
senso
r
.
T
he sensor in both cases is a 770pF piezoelectric
shoc
k
s
enso
r
a
cceleromete
r
,
w
hic
h
g
enerate
s
c
harg
e
u
nder
physical acceleration.
Figur
e
1
1
s
how
s
t
h
e
c
lassica
l
“
charg
e
a
mplifier
”
a
pproach.
Th
e
L
T
C624
0
i
s
i
n
t
h
e
i
nvertin
g
c
onfiguratio
n
s
o
t
h
e
s
ensor
looks into a virtual ground. All of the charge generated
+
V
S
+
1/2
L
T
C6241HV
SHOCK SENSOR
MURATA-ERIE
PKGS-00LD
770pF
–
+
1k
1k
L
T
C6240
SHOCK SENSOR
100ꢀ
10k
V
OUT
MURATA-ERIE
–
PKGS-00LD
770pF
C
V
= 110mV/g
OUT
f
1G
7.7pF
+
BIAS RESISTOR
1/2
MAIN
VISHAY-TECHNO
CRHV2512AF1007G
(OR EQUIVALENT)
L
T
C6241HV
R
GAIN-SETTING
ELEMENT IS A
CAPACITOR
f
–
CABLE HAS
UNKNOWN C
1G
V
V
= 110mV/g
OUT
=
S
1.4V to
5.5V
–
V
S
BIAS RESISTOR
VISHAY-TECHNO
CRHV2512AF1007G
(OR EQUIVALENT)
BW = 0.2Hz to 10kHz
100ꢀ
10k
6241 F11
6241 F12
Figure 11. Classical Inverting Charge Amplifier
Figure 12. Low Noise Noninverting Shock Sensor Amplifier
624012fe
24
LTC6240/LTC6241/LTC6242
APPLICATIONS INFORMATION
1M
T
r
ansimpedance Amplifier with 43nV/√Hz
By achieving an output swing of 50V before attenuation,
the circuit provides an output swing to 5V after attenu-
ation. The 10M resistor sets the gain of the TIA stage
and has a noise density of 400nV/√
Hz
. After attenuation,
the effective TIA gain drops to 1M while the noise floor
drops to 40nV/√
Hz
, which clearly dominates the observed
43nV/√
Hz
.
N
ot
e
t
h
e
a
dditiona
l
b
enefi
t
t
ha
t
t
h
e
o
ffse
t
v
oltage
of the op amp is divided by 10. Worst-case output offset
for this circuit is 150μV over temperature.
Output Noise
In a normal 1M transimpedance amplifie
r
,
l
ike that shown
o
n
t
h
e
b
ac
k
p
ag
e
o
f
t
hi
s
d
at
a
s
heet
,
t
h
e
o
utpu
t
n
ois
e
d
ensity
must be at least 130nV/√
Hz
at room temperature. This is
tru
e
e
ve
n
s
houl
d
t
h
e
o
p
a
m
p
b
e
p
erfectl
y
n
oiseless
,
b
ecause
the 1M resistor provides 130nV/√
Hz
of voltage noise at
room temperature independently of the op amp.
Th
e
c
ircui
t
o
f
F
igur
e
1
3
p
rovide
s
a
n
o
veral
l
t
ransimpedance
gain of 1MΩ, but it has an output noise density of only
43nV/√
Hz
,
a
bou
t
1
/
3
o
f
t
h
e
n
orma
l
t
ransimpedanc
e
a
mpli-
fie
r
.
I
t does this by taking a higher initial transimpedance
gain of 10M and then attenuating by a factor of 10. The
transistor section provides voltage gain and works on a
54V supply voltage to guarantee adequate output swing.
Reference Buffer
Figure 14 shows the
L
T
C6240 being utilized as a buffer
in conjunction with the
L
T
1019 reference. The passive
R-C filter attenuates the reference noise and the
L
T
C6240
provides a low noise buffe
r
,
r
esulting in an output noise
of 8nV/√
Hz
.
54V
33k
0.3pF
MPSA06
10M
1%
5V
10M GAIN
(10V/μA)
+
10k
3pF
PHOTODIODE
MPSA06
9.09k
L
T
C6240HV
1%
–
1/4W
–1.5V
V
OUT
100pF
1M GAIN
(1V/μA)
10k
2.4k 43k
–5V
1k
1%
1k
–5V
6241 F13
Figure 13. 1M
T
r
ansimpedance Amplifier with 43nV/√
Hz
Output Noise
5V
1M
180nV/√
Hz
L
T
1019-2.5
+
0.2ꢀ
8nV/√
Hz
1μF
L
T
C6240HV
V
OUT
10μF
CERAMIC
OR FILM
–
–5V
6241 F14
Figure 14. Low Noise Reference Buffer
624012fe
25
LTC6240/LTC6241/LTC6242
PACKAGE DESCRIPTION
DD Package
8-Lead Plastic DFN (3mm
×
3mm)
(Reference
L
T
C DWG # 05-08-1698)
0.70
p
0.05
3.5
p
0.05
2.10
p
0.05 (2
SIDES)
1.65
p
0.05
PACKAGE
OUTLINE
0.25
p
0.05
0.50
BSC
2.38
p
0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
R = 0.125
0.40
p
0.10
TYP
5
8
3.00
p
0.10
(4 SIDES)
1.65
p
0.10
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
(DD8) DFN 0509 REV C
4
1
0.25
p
0.05
0.75
p
0.05
0.200 REF
0.50 BSC
2.38
p
0.10
BOTTOM VIEW—EXPOSED PAD
0.00 – 0.05
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
624012fe
26
LTC6240/LTC6241/LTC6242
PACKAGE DESCRIPTION
DHC Package
16-Lead Plastic DFN (5mm
×
3mm)
(Reference
L
T
C DWG # 05-08-1706)
0.65 0.05
3.50 0.05
1.65 0.05
2.20 0.05
(2 SIDES)
PACKAGE
OUTLINE
0.25 0.05
0.50 BSC
4.40 0.05
(2 SIDES)
RECOMMENDED
SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
TYP
0.40 0.10
5.00 0.10
(2 SIDES)
9
16
R = 0.20
TYP
3.00 0.10
1.65 0.10
(2 SIDES)
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
PIN 1
NOTCH
(DHC16) DFN 1103
8
1
0.25 0.05
0.50 BSC
0.75 0.05
0.200 REF
4.40 0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
624012fe
27
LTC6240/LTC6241/LTC6242
PACKAGE DESCRIPTION
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference
L
T
C DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 .005
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 .0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
5
6
7
8
.015
.004
(0.38
0.10)
×
45
°
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0
°
– 8
°
TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
GN16 (SSOP) 0204
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006″ (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010″ (0.254mm) PER SIDE
624012fe
28
LTC6240/LTC6241/LTC6242
PACKAGE DESCRIPTION
S5 Package
5-Lead Plastic TSO
T
–
23
(Reference
L
T
C DWG # 05-08-1635 Rev B)
0.62
MAX
0.95
REF
2.90 BSC
(NOTE 4)
1.22 REF
1.50 – 1.75
(NOTE 4)
2.80 BSC
1.4 MIN
3.85 MAX
2.62 REF
PIN ONE
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.30 – 0.45 TYP
5 PLCS (NOTE 3)
0.95 BSC
0.80 – 0.90
0.20 BSC
DATUM ‘A’
0.01 – 0.10
1.00 MAX
0.30 – 0.50 REF
1.90 BSC
0.09 – 0.20
(NOTE 3)
NOTE:
S5 TSOT-23 0302 REV B
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
624012fe
29
LTC6240/LTC6241/LTC6242
PACKAGE DESCRIPTION
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference
L
T
C DWG # 05-08-1610)
.189 – .197
(4.801 – 5.004)
.045 .005
.160
.005
NOTE 3
.050 BSC
7
5
8
6
.245
MIN
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
.030 .005
TYP
1
3
4
2
RECOMMENDED SOLDER PAD LAYOUT
.010 – .020
(0.254 – 0.508)
×
45
°
.053 – .069
(1.346 – 1.752)
.004 – .010
(0.101 – 0.254)
.008 – .010
(0.203 – 0.254)
0
°
– 8
°
TYP
.016 – .050
(0.406 – 1.270)
.050
(1.270)
BSC
.014 – .019
(0.355 – 0.483)
TYP
NOTE:
INCHES
1. DIMENSIONS IN
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006″ (0.15mm)
SO8 0303
624012fe
30
LTC6240/LTC6241/LTC6242
REVISION HISTORY
(Revision history begins at Rev E)
REV
D
A
T
E
DESCRIPTION
PAGE NUMBER
E
07/10 Update
to Simplified Schematic (Figure 1)
19
624012fe
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
Howeve
r
,
n
o responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LTC6240/LTC6241/LTC6242
TYPICAL APPLICATION
1Mꢀ TIA
150kHz 3RD ORDER BUTTERWORTH FI
L
T
ER
+1.5V
R1
866ꢀ
R2
R3
2k
C2
+
1.69k
1500pF
1/2
L
T
C6241
+
1/2
C1
C3
180pF
–
L
T
C6241
R
F
1M
1500pF
–
SFH213FA
OR EQUIVALENT
(≤4pF)
–1.5V
6241 TA02a
C
F
–1.5V
1pF
Figure 15. Ultralow Noise 1MΩ 150kHz Photodiode Amplifier
L
T
C6241 Output Noise Spectrum. 1MΩ Resistor Noise
Dominates; Ideal Performance
Competition Output Noise Spectrum. Op Amp Noise Dominates;
Performance Compromised
0V
0V
1kHz
10kHz/DIV
101kHz
1kHz
10kHz/DIV
101kHz
6241 TA02b
6241 TA02c
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
L
T
C1151
15V ꢁero-Drift Op Amp
Dual High Voltage Operation
18V
6nV/√
Hz
Noise, 15V
Operation
2.7 Volt Operation, SO
T
–
23
L
T
1792
Low Noise Precision JFET Op Amp
ꢁero-Drift Op Amp
L
T
C2050
L
T
C2051/
L
T
C2052
L
T
C2054/
L
T
C2055
L
T
C6244
Dual/Quad ꢁero-Drift Op Amp
Single/Dual ꢁero-Drift Op Amp
Dual 50MHz Rail-to-Rail Op Amp
Dual/Quad Version of
L
T
C2050 in MS8/GN16 Packages
Micropower Version of the
L
T
C2050/
L
T
C2051 in SO
T
–
23 and DD Packages
100μV V
, 1pA I
, 40V/μ
V
,
S
lew Rate
OS(MAX)
BIAS
624012fe
LT 0710 REV E • PRINTED IN USA
Linea
r
T
e
chnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
32
●
●
©
LINEAR TECHNOLOGY CORPOR
A
T
ION 2005
