Analog-Devices-PN4118-TO-92-3L-ROHS
| Part # | Analog-Devices-PN4118-TO-92-3L-ROHS |
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2N/PN/SST 4117,
4118, 4119
ULTRA-HIGH INPUT IMPEDANCE
N-CHANNEL JFET AMPLIFIER
FEATURES
LOW POWER
I
DSS
<600 µA (2N4117A)
MINIMUM CIRCUIT LOADING
I
GSS
<1 pA (2N4117A Series)
ABSOLUTE MAXIMUM RATINGS (NOTE 3)
@ 25°C (unless otherwise noted)
PN SERIES
SST SERIES
2N SERIES
TO-92
SOT-23
TO-72
TOP VIEW
TOP VIEW
TOP VIEW
Gate-Source or Gate-Drain Voltage
Gate-Current
-40V
50mA
1
3
2
D
S
Total Device Dissipation
(Derate 2mW/ºC above 25ºC)
G
1
2
3
300mW
G
D
S
Storage Temperature Range
Lead Temperature
-55ºC to+150ºC
(1/16” from case for 10 seconds)
300ºC
ELECTRICAL CHARACTERISTICS @ 25ºC (unless otherwise noted)
4117 4118
MAX MAX
4119
MIN
-40
MIN
-40
-1
MIN
-40
-2
MAX
—
SYMBOL
CHARACTERISTIC
UNITS
CONDITIONS
Gate-Source Breakdown
Voltage
BV
GSS
—
—
-3
I
G
=-1µA V
DS
=0
V
DS
=10V I
D
=1nA
V
DS
=10V V
GS
=0
V
V
GS(off)
I
DSS
Gate-Source Cutoff Voltage
-0.6
0.03
-1.8
0.60
-6
Saturation Drain Current
(NOTE 2)
0.08
0.60
0.20
0.80
mA
—
—
-1
-2.5
-10
-25
450
3
—
—
-1
-2.5
-10
-25
650
5
—
—
-1
-2.5
-10
-25
700
10
pA
nA
pA
nA
Gate Reverse Current
2N4117A, 2N4118A, 2N4119A
V
GS
=-20V V
DS
=0
V
GS
=-10V V
DS
=0
150ºC
I
GSS
—
—
—
PN4117, PN4118, PN4119
SST4117, SST4118, SST4119
—
—
—
150ºC
Common-Source Forward
Transconductance
Common-Source Output
Conductance
Common-Source Input
Capacitance
(NOTE 4)
Common-Source Reverse
Transfer Capacitance
(NOTE 4)
g
fs
70
—
80
—
100
—
µS
pF
f=1kHz
g
os
C
iss
C
rss
V
DS
=10V V
GS
=0
—
3
—
3
—
3
f=1MHz
—
1.5
—
1.5
—
1.5
Linear Integrated Systems
• 4042
Clipper Court
• Fremont,
CA 94538
• Tel:
510 490-9160
• Fax:
510 353-0261
Doc 201135
07/25/2019 Rev#A11 ECN#
2N & SST 4117 4118 4119
STANDARD PACKAGE DIMENSIONS:
2N4117A, 2N4118A,
2N4119A
PN4117, PN4118,
PN4119
SST4117, SST4118,
SST4119
TO-72
Four Lead
TO-92
SOT-23
0.89
1.03
0.37
0.51
1
2
1.78
2.05
2.80
3.04
3
1.20
1.40
0.89
1.12
2.10
2.64
0.085
0.180
0.013
0.100
0.55
DIMENSIONS IN
MILLIMETERS
*Dimensions in inches
NOTES:
1. Due
to symmetrical geometry, these units may be operated with source and drain leads interchanged.
2. This
parameter is measured during a 2 ms interval 100 ms after power is applied.
(Not a JEDEC condition.)
3. Absolute
maximum ratings are limiting values above which serviceability may be impaired.
4. Not
production tested, guaranteed by design.
Information furnished by Linear Integrated Systems is believed to be accurate and reliable.
However, no responsibility is assumed for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
No license is granted by implication or otherwise
under any patent rights of Linear Integrated Systems.
Linear Integrated Systems develops and produces the highest performance semiconductors of their kind in the industry. Linear
Systems, founded in 1987, uses patented and proprietary processes and designs to create its high performance discrete
semiconductors. Expertise brought to the company is based on processes and products developed at Amelco, Union Carbide,
Intersil and Micro Power Systems by company founder John H. Hall.
Linear Integrated Systems
• 4042
Clipper Court
• Fremont,
CA 94538
• Tel:
510 490-9160
• Fax:
510 353-0261
Doc 201135
07/25/2019 Rev#A11 ECN#
2N & SST 4117 4118 4119
