Analog-Devices-SSM2220P
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Audio Dual Matched PNP Transistor
Data Sheet
FEATURES
PIN CONNECTION DIAGRAM
SSM2220
Low voltage noise at 100 Hz, 1 nV/√Hz maximum
High gain bandwidth: 190 MHz typical
Gain at I
C
= 1 mA, 165 typical
Tight gain matching: 3% maximum
Outstanding logarithmic conformance: r
BE
= 0.3 Ω typical
Low offset voltage: 200 μV maximum
TOP VIEW
(Not to Scale)
C
B
E
1
2
3
4
8
7
6
5
C
B
E
1
1
1
2
2
2
NC
NC
NOTES
APPLICATIONS
1. NC = NO CONNECT. THIS PIN IS
NOT CONNECTED INTERNALLY.
Microphone preamplifiers
Tape head preamplifiers
Figure 1.
Current sources and mirrors
Low noise precision instrumentation
Voltage controlled amplifiers/multipliers
GENERAL DESCRIPTION
has been optimized for use in audio applications.
across the base to emitter junction were used to clamp any reverse
base to emitter junction potential. This prevents a base to emitter
breakdown condition, which can result in degradation of gain and
matching performance due to excessive breakdown current.
0.7 nV/√Hz over the entire audio bandwidth of 20 Hz to 20 kHz.
The low noise, high bandwidth (190 MHz), and offset voltage of
ing, low noise preamplifier applications.
of 0.3 Ω typical, which assures accurate logarithmic conformance.
8-lead standard small outline (SOIC), and its performance and
characteristics are guaranteed over the extended industrial temper-
ature range of −40°C to +85°C.
(Δh
FE
) to about 0.5%, which helps to reduce the high order ampli-
fier harmonic distortion. In addition, to ensure the long-term
stability of the matching parameters, internal protection diodes
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
SSM2220
Data Sheet
TABLE OF CONTENTS
REVISION HISTORY
4/13—Rev. B to Rev. C
11/03—Rev. A to Rev. B
Updated Format…………………………………………………………Universal
Changes to Features Section and Figure 1………………………………. 1
Change to Endnote 2 and Endnote 4,
T
able 1…………………………. 3
Changed Breakdown
V
o
ltage Parameter, Table 2
Changes to Ordering Guid
e
.
……………………………………………………1
Updated Outline Dimension
s
………………………………………………….9
to Breakdown Voltage (Collector to Emitter),
T
a
ble 2 ……………. 3
Changes to
T
able 3…………………………………………………………………. 4
Changes to Figure 8 Caption, Figure 9 Caption,
and Figure 12…………………………………………………………………………. 6
Change to Figure 15 ………………………………………………………………. 7
Changes to Super Low Noise Amplifier Section, Figure 16, and
Figure 17 Caption ………………………………………………………………….. 8
Change to Figure 18 ………………………………………………………………. 9
Changes to Figure 19 and Noise Measurement Sectio
n
.
……….. 10
Changes to Current Sources and Current
Matching Sections ……………………………………………………………….. 11
Updated Outline Dimensions ………………………………………………. 12
Changes to Ordering Guide …………………………………………………. 12
Rev. C | Page 2 of 12
Data Sheet
SSM2220
SPECIFICATIONS
T
A
= 25°C, unless otherwise noted.
Table 1.
Parameter
CURRENT GAIN
1
Symbol
Min
Typ
Max Unit
Test Conditions/Comments
h
FE
V
CB
= 0 V to 36 V
I
C
= 1 mA
I
C
= 100 μA
I
C
= 10 μA
I
C
= 100 μA, V
CB
= 0 V
I
C
= 1 mA, V
CB
= 0 V
80
70
60
165
150
120
0.5
Δh
FE
e
n
6
%
0.8
0.7
0.7
0.7
40
11
12
6
2
1
1
1
nV/√Hz f
O
= 10 Hz
nV/√Hz f
O
= 100 Hz
nV/√Hz f
O
= 1 kHz
nV/√Hz f
O
= 10 kHz
V
OS
200
200
75
45
400
0.75
μV
μV
μV
nA
pA
Ω
V
CB
= 0 V, I
C
= 100 μA
Offset Voltage Change vs. Collector Voltage
Offset Voltage Change vs. Collector Current
OFFSET CURRENT
ΔV
OS
/ΔV
CB
ΔV
OS
/ΔI
C
I
OS
I
C
= 100 μA, V
CB1
= 0 V, V
CB2
= −36 V
V
CB
= 0 V, I
C1
= 10 μA, I
C2
= 1 mA
I
C
= 100 μA, V
CB
= 0 V
COLLECTOR TO BASE LEAKAGE CURRENT
BULK RESISTANCE
I
CBO
50
0.3
V
CB
= −36 V = V
MAX
r
BE
V
CB
= 0 V, 10 μA ≤ I
C
≤ 1 mA
I
C
= 1 mA, I
B
= 100 μA
COLLECTOR SATURATION VOLTAGE
V
CE(SAT)
0.026 0.1
V
1
Current gain is measured at collector to base voltages (V
CB
) swept from 0 V to V
MAX
at indicated collector current. Typicals are measured at V
CB
= 0 V.
2
Current gain matching (
Δh
FE
) is defined as follows:
100(
∆
I
B
)(
h
FE
)
min
Δ
h
FE
=
I
C
3
Sample tested. Noise tested and specified as equivalent input voltage for each transistor.
4
Offset voltage is defined as follows:
C1
I
I
C2
KT
q
V
OS
=
V
BE1
–
V
BE2
=
ln
where
V
OS
is the differential voltage for
I
C1
=
I
C2
.
ELECTRICAL CHARACTERISTICS
−40°C ≤ T
A
≤ +85°C, unless otherwise noted.
Table 2.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
V
CB
= 0 V to 36 V
I
C
= 1 mA
I
C
= 100 μA
I
C
= 10 μA
CURRENT GAIN
h
FE
60
50
40
125
105
90
OFFSET VOLTAGE
V
OS
TCV
OS
I
OS
30
0.3
10
265
1.0
μV
μV/°C
nA
I
C
= 100 μA, V
CB
= 0 V
I
C
= 100 μA, V
CB
= 0 V
I
C
= 100 μA, V
CB
= 0 V
OFFSET CURRENT
200
BREAKDOWN VOLTAGE (COLLECTOR TO EMITTER)
BV
CEO
36
V
1
Guaranteed by V
OS
test (TCV
OS
= V
OS
/
T for V
OS
<< V
BE
), where T = 298K for T
A
= 25°C.
Rev. C | Page 3 of 12
SSM2220
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
THERMAL RESISTANCE
Parameter
Rating
Table 4.
Breakdown Voltage of
Collector to Base Voltage (BV
CBO
Collector to Emitter Voltage (BV
CEO
Collector to Collector Voltage (BV
CC
)
Emitter to Emitter Voltage (BV
EE
)
Current
Package Type
8-Lead PDIP
8-Lead SOIC
θ
JA
θ
JC
43
43
Unit
°C/W
°C/W
)
36 V
36 V
36 V
36 V
103
158
)
1
θ
JA
is specified for worst-case mounting conditions; that is, θ
JA
is specified for a
device in a socket for the PDIP package, and a device soldered to a printed
circuit board for SOIC packages.
Collector (I
C
)
Emitter (I
E
)
20 mA
20 mA
Temperature Range
Operating
Storage
ESD CAUTION
–40°C to +85°C
–65°C to +150°C
–65°C to +150°C
+300°C
Junction
Lead Temperature (Soldering, 60 sec)
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. C | Page 4 of 12
Data Sheet
SSM2220
TYPICAL PERFORMANCE CHARACTERISTICS
250
200
V
I
= 5V
= 1mA
= 25°C
T
V
= 25°C
= 0V
CE
A
1s
R
R
S
S
C
CB
T
A
f = 1kHz
40nV
0V
150
100
50
R
= 100kΩ
S
–40nV
R
= 10kΩ
S
R
= 1kΩ
S
VERTICAL = 40nV/DIV
HORIZONTAL = 1s/DIV
20mV
0
1
10
100
1000
COLLECTOR CURRENT (µA)
Figure 2. Low Frequency Noise
Figure 5. Total Noise vs. Collector Current
14
12
10
8
6
V
= 5V
T
V
= 25°C
CE
f = 1kHz
A
= 0V
CB
5
4
3
2
1
0
R
= 1kΩ
S
10Hz
R
= 100kΩ
S
6
4
R
= 10kΩ
S
2
100Hz
0
0.001
0.01
0.1
1
0
3
6
9
12
COLLECTOR CURRENT (mA)
COLLECTOR CURRENT (mA)
Figure 3. Noise Figure vs. Collector Current
Figure 6. Noise Voltage Density vs. Collector Current
1k
0.5
T
V
= 25°C
= 0V
T
V
= 25°C
A
A
= 0V
0.4
0.3
CB
CB
100
10
1
0.2
0.1
0
I
= 10µA
C
–0.1
–0.2
–0.3
–0.4
–0.5
I
= 100µA
C
I
= 1mA
C
0.1
0.1
–8
–7
–6
–5
–4
–3
10
1
10
100
1k
10k
100k
10
10
10
10
10
FREQUENCY (Hz)
COLLECTOR CURRENT (A)
Figure 4. Emitter to Base Log Conformity
Figure 7. Noise Voltage Density vs. Frequency
Rev. C | Page 5 of 12
SSM2220
Data Sheet
300
10
V
CB
= 0V
250
200
150
100
50
+125°C
1
+25°C
–55°C
+125°C
+25°C
0.1
–55°C
0
0.01
10
100
COLLECTOR CURRENT (µA)
1000
0.01
0.1
1
10
COLLECTOR CURRENT (mA)
Figure 8. Current Gain (h
FE
) vs. Collector Current
Figure 11. Saturation Voltage vs. Collector Current
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
700
600
500
400
300
200
100
0
T
= 25°C
A
I
= 1mA
C
V
= –36V
CB
V
= 0V
CB
1
10
100
1000
10000
–55
–35
–15
5
25
45
65
85
105
125
COLLECTOR CURRENT (µA)
TEMPERATURE (°C)
Figure 12. Base to Emitter Voltage (V
BE
) vs. Collector Current
Figure 9. Current Gain (h
FE
) vs. Temperature
50
40
30
20
10
0
1k
100
10
T
V
= 25°C
T =
25°C
A
A
= 0V
CB
1
0.1
0.001
0
–5
–10
–15
–20
–25
–30
–35
0.01
0.1
1
10
100
COLLECTOR-BASE VOLTAGE (V)
COLLECTOR CURRENT (mA)
Figure 13. Collector to Base Capacitance vs. V
CB
Figure 10. Gain Bandwidth vs. Collector Current
Rev. C | Page 6 of 12
Data Sheet
SSM2220
1M
100
10
T
= 25°C
T
= 25°C
A
A
100k
10k
1
0.1
0.01
1k
1
10
100
1000
1
10
100
1000
COLLECTOR CURRENT (µA)
COLLECTOR CURRENT (µA)
Figure 14. Small Signal Input Resistance (h
ie
) vs. Collector Current
Figure 15. Small Signal Output Conductance (h
oe
) vs. Collector Current
Rev. C | Page 7 of 12
SSM2220
Data Sheet
APPLICATIONS INFORMATION
PULSE RESPONSE
A
C
= 10
= 30pF
V
F
–15V
+15V
7
0.01µF
6
10µF
0.001µF
1.5kΩ
0.01%
1.5kΩ
0.01%
+
2
3
AD8671
V
OUT
0.01µF
4
150Ω
0.01µF
5V
20µs
Q5 Q3 Q1
Q2 Q4 Q6
–15V
–
+
LOW FREQUENCY NOISE
SSM2220 PAIRS:
Q1 – Q2
A
= 1000
= 1nV/DIV
V
–15V
27kΩ
V
ERT
Q3 – Q4
Q5 – Q6
Q7
RED
LED
83Ω
10µF
0.001µF
+
+15V
Figure 16. Super Low Noise Amplifier
0.1
SUPER LOW NOISE AMPLIFIER
matched pairs, a reduction of the base spreading resistance by a
factor of 3 results in a further reduction of amplifier noise by a fac-
tor of √3. Additionally, the shot noise contribution is reduced by
maintaining a high collector current (2 mA/device), which reduces
the dynamic emitter resistance and decreases voltage noise. The
voltage noise is inversely proportional to the square root of the
stage current, whereas current noise increases proportionally.
Accordingly, this amplifier capitalizes on voltage noise reduction
techniques at the expense of increasing the current noise. However,
high current noise is not usually important when dealing with
low impedance sources.
600Ω LOAD
0.01
NO LOAD
0.001
10
100
1k
FREQUENCY (Hz)
10k
100k
This amplifier exhibits excellent full power ac performance,
0.08% THD into a 600 Ω load, making it suitable for exacting
Rev. C | Page 8 of 12
Data Sheet
SSM2220
0.01µF
+15V
R1
LED
10µF
+
250
Ω
Q2
2N29007A
6
3
1
R6
100
Ω
2
7
Q1
SSM2220
V
IN
R5
100
Ω
C1
50pF
8
8
2
3
1
V
AD8671
4
OUT
10µF
R2
27k
Ω
R3
5k
Ω
R4
5k
Ω
+
0.01µF
THD < 0.005% 20Hz TO 20kHz
0.5nV/ Hz
–15V
1/f CORNER < 1Hz
Figure 18. Low Noise Microphone Preamplifier
input stage emitter current of 4 mA is provided by Q2. The con-
stant current in Q2 is set by using the forward voltage of a GaAsP
LED as a reference. The difference between this voltage and the
LOW NOISE MICROPHONE PREAMPLIFIER
Figure 18 sh
ows a microphone preamplifier that consists of an
relatively high quiescent current of 2 mA per side, which reduces
1 Hz.
T
o
tal harmonic distortion is under 0.005% for a 10 V p-p
signal from 20 Hz to 20 kHz. The preamp gain is 100, but can be
modified by varying R5 or R6 (V
OUT
/V
IN
= R5/R6 + 1). A total
V
BE
of a silicon transistor is predictable and constant (to a few
percent) over a wide temperature range. The voltage difference,
approximately 1
V
,
i
s dropped across the 250 Ω resistor, which
produces a temperature stabilized emitter current.
Rev. C | Page 9 of 12
SSM2220
Data Sheet
+5V
+
0.1µF
10µF
3
6
SSM2220
2
7
1
3
8
6
SSM2220
2
7
1
8
+15V
2mA
0.01µF
3
6
1kΩ
ADJUST POT
FOR 2mA
(2V ACROSS
1k
Ω
RES)
2
7
SSM2220
DUT
500Ω
+15V
7
1
8
0.01µF
6
2.2pF
7
2
6
3
2
AD8671
4
e
n
1kΩ
3
SPOT NOISE FOR
EACH TRANSISTOR =
e
n
AD8671
10Ω
5kΩ
1%
5kΩ
10,000 ×
2
0.01µF
1%
4
10kΩ
100Ω
5kΩ
–15V
10µF
0.1µF
0.01µF
+
–15V
–15V
Figure 19. Voltage Noise Measurement Circuit
+V
NOISE MEASUREMENT
All resistive components and semiconductor junctions contribute
to the system input noise. Resistive components produce Johnson
noise (e
n
2
= 4kTBR, or e
n
= 0.13√R nV/√Hz, where R is in kΩ). At
semiconductor junctions, shot noise is caused by current flowing
through a junction, producing voltage noise in series impedances
such as transistor collector load resistors (I
n
= 0.556√I pA/√Hz,
where I is in μA).
SSM2220
Q4
Q3
Q2
SSM2220
Q1
I
= I
OUT
Figure 19
illustrates a technique for measuring the equivalent
used to bias each side of the differential pair. The 5 kΩ collector
resistors noise contribution is insignificant compared to the voltage
back to the input, this voltage noise is attenuated by the gain of the
circuit. Consequently, the noise contribution of the collector load
resistors is only 0.048 nV/√Hz. This is considerably less than the
+V – 2V
BE
I =
R
R
Figure 20. Cascode Current Source
CURRENT SOURCES
A fundamental requirement for accurate current mirrors and active
load stages is matched transistor components. Due to the excellent
BE
matching (the voltage difference between one V
BE
and another,
which is required to equalize collector current) and gain matching,
rent mirrors that can source current into a load such as an amplifier
stage. The advantages of current loads in amplifiers vs. resistors
are an increase of voltage gain due to higher impedances, larger
signal range, and in many applications, a wider signal bandwidth.
V
due to the gain in the signal path. The op amp stages amplify the
input referred noise of the transistors, increasing the signal strength
to allow the noise spectral density,
(
e
n
input
× 10,000, to be meas-
)
ured with a spectrum analyzer. Because equal noise contributions
divided by √2 to determine the input noise of a single transistor.
Figure 20
illustrates a cascode current mirror consisting of two
SSM2220
transistor pairs.
Air currents cause small temperature changes that can appear as
low frequency noise.
T
o
e
liminate this noise source, the measure-
ment circuit must be thermally isolated. Effects of extraneous noise
sources must also be eliminated by totally shielding the circuit.
The cascode current source has a common base transistor in series
with the output, which causes an increase in output impedance of
the current source because V
CE
stays relatively constant. High fre-
quency characteristics are improved due to a reduction of Miller
capacitance. The small signal output impedance can be determined
Rev. C | Page 10 of 12
Data Sheet
SSM2220
the performance of a perfect current source.
If the resistors and transistors are equal and the collector
voltages are the same, then the collector currents match precisely.
Investigating the current matching errors resulting from a nonzero
V
OS
, ΔI
C
is defined as the current error between the two transistors.
1
(
r
o
)
Q3
=
=
1
M
Ω
1.
0
μ
Mho
Figure 22
describes the relationship of current matching errors
vs. offset voltage for a specified average current, I
C
. Note that
because the relative error between the currents is exponentially
proportional to the offset voltage, tight matching is required to
design high accuracy current sources. For example, if the offset
voltage were 5 mV at 100 μA collector current, the current match-
ing error would be 20%. Additionally, temperature effects, such
as offset drift (3 μV/°C per mV of V
OS
), degrade performance if
Q1 and Q2 are not well matched.
Q2 and Q3 are in series and operate at the same current level;
therefore, the total output impedance is as follows:
R
O
=
h
FE
× (
r
o
)
Q3
≈ (160)(1 MΩ) = 160 MΩ
Current Matching
The objective of current source or mirror design is generation
of currents that either are matched or must maintain a constant
ratio. However, mismatch of base emitter voltages causes output
ΔI
2
ΔI
2
C
C
I
+
I –
C
C
A CLOSELY MATCHED
TRANSISTOR PAIR
–
V
B
R1
R2
+
R1 = R2 = R
Figure 21. Current Matching Circuit
1.2
1.0
0.8
0.6
0.4
0.2
I
= 10µA
I =
100µA
C
C
SSM2220 V
OS
PERFORMANCE
R = 3kΩ
= 200
h
FE
I
+ I
2
C1
C2
I
=
C
I
= 1mA
C
Δ
I = I
– I
C1
C2
0
0.001
0.01
0.1
(mV)
1
10
V
OS
Figure 22. Current Matching Accuracy vs. Offset Voltage
Rev. C | Page 11 of 12
SSM2220
Data Sheet
OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
8
1
5
4
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 23. 8-Lead Plastic Dual In-Line Package [PDIP]
(N-8)
Dimensions shown in inches and (millimeters)
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ON
L
Y
A
ND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 24. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Temperature Range
Package Description
Package Option
SSM2220PZ
SSM2220S
SSM2220SZ
SSM2220SZ-REEL
–40°C to +85°C
8-Lead Plastic Dual In-Line Package [PDIP]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
N-8
R-8
R-8
R-8
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
1
Z = RoHS Compliant Part.
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