ASDsemi-ASDM20N90Q-R
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ASDM
2
0N
90
Q
2
0V N-C
HA
NNE
L
MOSFET
Feature
Product Summary
•
100% EAS Guaranteed
V
DS
2
0
1.5
V
m
Ω
m
Ω
•
Green Device Available
R
DS(on),TYP
@
V
GS
=10V
R
DS(on),TYP
@
V
GS
=4.5V
•
Super Low Gate Charge
1.8
•
Excellent CdV/dt effect decline
•
Advanced high cell density Trench technology
I
D
A
9
0
Application
•
Power Management in Inverter System
top view
P
DFN
5
*
6
-8
Maximum ratings, at
T
A
=25 °C, unless otherwise specified
Symbol
Parameter
Rating
Unit
Drain-Source breakdown voltage
20
V
A
V
DS
I
S
Diode continuous forward current
T
C
=
25°C
90
=25°C
T
90
75
A
A
c
①
I
D
Continuous drain current @V
GS
=10V
=100°C
T
c
=25°C
=25°C
I
DM
T
A
360
105
40
A
mJ
W
V
Pulse drain current tested
Avalanche energy, single pulsed
②
Maximum power dissipation
Gate-Source voltage
EAS
P
D
T
c
V
GS
±20
MSL
Level 3
,
T
J
T
STG
Storage and junction temperature range
-55 to 150
°C
Thermal Characteristics
Symbol
Parameter
Typical
1.9
Unit
°C/W
R
θJꢀ
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
°C/W
35
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Ascend Semicondutor
ASDM
2
0N
90
Q
2
0V N-C
HA
NNE
L
MOSFET
Typical Electrical Characteristics
Symbol
Parameter
Condition
Min.
Typ. Max.
Unit
Static Electrical Characteristics @ T
J
= 25°C (unless otherwise stated)
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current(Tj=25
℃
)
Zero Gate Voltage Drain Current(Tj=125
℃
)
Gate-Body Leakage Current
V
GS
=0V, I
D
=250μA
V
DS
=20V,V
GS
=0V
V
DS
=20V,V
GS
=0V
V
GS
=±12
V
,
V
DS
=0V
V
DS
=V
GS
,I
D
=250μA
V
GS
=10V, I
D
=30A
20
—
—
—
1
V
V
(BR)DSS
—
μA
μA
nA
V
I
DSS
—
—
100
±100
1.
1
2.
5
—
—
I
GSS
Gate Threshold Voltage
0.
5
—
0.7
5
1.
5
V
GS(TH)
mΩ
Drain-Source On-State Resistance
③
R
DS(ON)
R
DS(ON)
V
GS
=4.5V, I
D
=
20
A
V
GS
=2.5V, I
D
=
20
A
—
—
1.8
2.8
2.8
4
mΩ
mΩ
Drain-Source On-State Resistance
Drain-Source On-State Resistance
③
③
R
DS(ON)
Dynamic Electrical Characteristics @ T
J
= 25°C (unless otherwise stated)
Input Capacitance
3605
490
365
2.4
pF
pF
pF
Ω
C
iss
V
DS
=10V,V
GS
=0V,
Output Capacitance
C
oss
f=1MHz
Reverse Transfer Capacitance
C
rss
Gate Resistance
T
o
tal Gate Charge
Gate-Source Charge
Gate-Drain Charge
f=1MHz
—
—
—
—
—
—
R
g
Q
g
36.6
6.07
13.8
nC
nC
nC
V
DS
=10V,I
D
=15A,
V
GS
=10V
—
—
Q
gs
Q
gd
Switching
Characteristics
Turn-on Delay Time
11.2
49
—
—
—
—
—
—
—
—
nS
nS
nS
nS
t
d(on)
t
r
t
d(off)
t
f
V
DD
=10V,
I
D
=20A,
Turn-on Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
R
G
=1.5
Ω,
V
GS
=6V
35
7.8
Source- Drain Diode Characteristics@ T
J
= 25°C (unless otherwise stated)
Forward on voltage
I
SD
=2A,V
GS
=0V
—
—
0.8
20
1.2
—
V
V
SD
t
rr
T
j
=25
℃
,I
sd
=10A,
V
GS
=0V
Reverse Recovery Time
Reverse Recovery Charge
nS
nC
11.5
Q
rr
di/dt=5
00A/μs
NOTE:
①
This characteristics assumes the die are assembled in P
DFN5*
6
-8
packages. Actual performance may degrade when
assembled. Ascend does not guarantee device performance after assembly
.
②
Limited by T
Jmax
, starting T
J
= 25°C, L = 0.1mH,R
G
= 25
Ω
, I
AS
= 42A, V
GS
=6V. Part not recommended for use above this value.
③
Pulse width ≤ 300μs; duty cycle≤ 2%.
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Ascend Semicondutor Co.,Ltd
ASDM
2
0N
90
Q
2
0V N-C
HA
NNE
L
MOSFET
Ordering and Marking Information
Ordering Device No.
Marking
Package
Packing
Quantity
ASDM20N
90
Q
-R
20N
90
PD
F
N
5
*
6
-8
Tape&Reel
4
000
/
Reel
MARKING
PACKAGE
PD
F
N
5
*
6
–
8
2
0N
9
0
NOV 2019 Version
1.
0
3
/
5
Ascend Semicondutor Co.,Ltd
ASDM
2
0N
90
Q
2
0V N-C
HA
NNE
L
MOSFET
Package Outline Dimensions (Units: mm)
PDFN5
*
6-
8
A
b
C
D
D1
D2
E
E1
E2
e
L
L1
H
UNIT
mm
1.12
0.9
0.51
0.33
0.34
0.11
5.26
4.7
5.1
4.7
4. 5
6.25
5.75
6
3.66
3.18
1.37
1.17
0.71
0.35
0.2
0.71
0.35
3.56
5.6
0.06
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ASDM
2
0N
90
Q
2
0V N-C
HA
NNE
L
MOSFET
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incorporated
MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS
DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION).
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Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections
or other changes without further notice to this document and any product described herein.
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Incorporated does not
assume any liability arising out of the application or use of this document or any product described herein; neither does
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Semiconductor
Incorporated convey
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1.
0
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