CET-Chino-Excel-Tech-CEG8205A

Part #CET-Chino-Excel-Tech-CEG8205A
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CET-Chino-Excel-Tech-CEG8205A
CEG8205A  
Dual N-Channel Enhancement Mode Field Effect Transistor  
FEATURES  
20V, 6A, R

DS(ON)

= 25m
Ω
@V

GS

= 4.5V.  
R

DS(ON)

= 35m
Ω
@V

GS

= 2.5V.  
Super High dense cell design for extremely low R

DS(ON)  

.
High power and current handing capability.  
Lead free product is acquired.  
1
2
3
4
8
7
6
5
D
D
S
2  
S
2  
G
2  
S
1  
S
1  
TSSOP-8 for Surface Mount Package.  
G
1  
G
2  
S
2  
S
2  
D
G
1  
S
1  
S
1  
D
TSSOP-8  
ABSOLUTE MAXIMUM RATINGS
 
T

A

= 25 C unless otherwise noted  
Parameter  
Symbol  
V

DS  

V

GS  

I

D  

Limit  
Units  
Drain-Source Voltage  
20  
V
V
A
A
Gate-Source Voltage  
Drain Current-Continuous  
Drain Current-Pulsed

a  

±
12  
6
I

DM  

25  
Maximum Power Dissipation  
P

D  

1.5  
W
C
Operating and Store Temperature Range  
T
J
,T
stg  
-55 to 150  
Thermal Characteristics  
Parameter  
Symbol  
Limit  
Units  
Thermal Resistance, Junction-to-Ambient

b  

R
θ
JA  
83  
C/W  
Rev 2.
 
2010.Dec  
Details are subject to change without notice .  
1

CEG8205A  
Electrical Characteristics
 
T

A

= 25 C unless otherwise noted  
Parameter  
Off Characteristics  
Symbol  
Test Condition  
Min  
Typ  
Max  
Units  
Drain-Source Breakdown Voltage  
Zero Gate Voltage Drain Current  
Gate Body Leakage Current, Forward  
Gate Body Leakage Current, Reverse  
On Characteristics

c  

BV

DSS  

I

DSS  

V

GS

= 0
V
,
I

D

= 250
µ
A  
V

DS

= 18
V
,
 
V

GS

= 0V  
V

GS

= 12
V
,
 
V

DS

= 0V  
V

GS

= -12
V
,
V

DS

= 0V  
20  
V
1
µ
A  
nA  
nA  
I

GSSF  

I
GSSR  
100  
-100  
Gate Threshold Voltage  
Static Drain-Source  
V

GS(th)  

R

DS(on)  

V

GS

= V

DS

, I

D

= 250
µ
A  
V

GS

= 4.5
V
,
I

D

= 4.5A  
V

GS

= 2.5
V
,
I

D

= 3.5A  
0.5  
1.2  
25  
35  
V
21  
27  
m
Ω
 
m
Ω  
On-Resistance  
Dynamic Characteristics

d  

Input Capacitance  
C

iss  

C

oss  

C

rss  

720  
130  
95  
pF  
pF  
pF  
V

DS

= 8
V
,
V

GS

= 0
V
,  
f = 1.0 MHz  
Output Capacitance  
Reverse Transfer Capacitance  
Switching Characteristics

d  

Turn-On Delay Time  
t

d(on)  

t

r  

t

d(off)  

t

f  

10  
7
20  
14  
68  
12  
8.8  
ns  
ns  
V

DD

= 10
V
,
I

D

= 1A,  
V

GS

= 4.5
V
,
R

GEN

= 6
Ω  
Turn-On Rise Time  
Turn-Off Delay Time  
34  
6
ns  
Turn-Off Fall Time  
ns  
T
o
tal Gate Charge  
Q

g  

6.8  
0.5  
1.8  
nC  
nC  
nC  
V

DS

= 10
V
,
I

D

= 6A,  
V

GS

= 4.5V  
Gate-Source Charge  
Q

gs  

Q

gd  

Gate-Drain Charge  
Drain-Source Diode Characteristics and Maximun Ratings  
Drain-Source Diode Forward Current

b  

Drain-Source Diode Forward Voltage

c  

I

S  

1.7  
1.2  
A
V
V

SD  

V

GS

= 0
V
,
I

S

= 1.7A  
Notes :  
a.Repetitive Rating : Pulse width limited by maximum junction temperature.  
b.Surface Mounted on FR4 Board, t < 10 sec.  
c.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%.  
d.Guaranteed by design, not subject to production testing.  
2

CEG8205A  
10  
8
30  
24  
18  
12  
6
V

GS

=4.5,3.5,2.5V  
25 C  
V

GS

=2.0V  
6
4
2
0
V

GS

=1.5V  
T

J

=125 C  
-55 C  
0
0
1
2
3
0
1
2
2.0  
3
V
DS
, Drain-to-Source Voltage (V)  
V
GS
, Gate-to-Source Voltage (V)  
Figure 1. Output Characteristics  
Figure 2. Transfer Characteristics  
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
900  
750  
600  
450  
300  
150  
0
I

D

=4.5A  
V

GS

=4.5V  
C
iss  
C
oss  
C
rss  
0
2
4
6
8
10  
-100  
-50  
0
50  
100  
150  
200  
V
DS
, Drain-to-Source Voltage (V)  
T
J
, Junction Temperature( C)  
Figure 3. Capacitance  
Figure 4. On-Resistance
V
a
riation  
with
T
e
mperature  
1.3  
1.2  
1.1  
1.0  
0.9  
0.8  
0.7  
0.6  
V

DS

=V

GS  

I

D

=250µA  
V

GS

=0V  
10

1  

10

0  

10

-1  

-50 -25  
0
25 50 75 100 125 150  
0.4  
0.6  
0.8  
1.0  
1.2  
1.4  
T
J
, Junction Temperature( C)  
V
SD
, Body Diode Forward Voltage (V)  
Figure 5. Gate Threshold Variation  
with Temperature  
Figure 6. Body Diode Forward Voltage  
Variation with Source Current  
3

CEG8205A  
10

2  

10

1  

10

0  

10

-1  

10

-2  

5
4
3
2
1
0
V

DS

=10V  
I

D

=4.5A  
R

DS(ON)

Limit  
1ms  
10ms  
100ms  
1s  
DC  
T

A

=25 C  
T

J

=150 C  
Single Pulse  
10

-2  

10

-1  

10

0  

10

1  

10

2  

0
2
4
6
8
Qg, Total Gate Charge (nC)  
V
DS
, Drain-Source Voltage (V)  
Figure 7. Gate Charge  
Figure 8. Maximum Safe  
Operating Area  
V

DD  

on  
t
t
off  
d(off)  
t
r
t
d(on)  
OUT  
R
L  
t
f
t
V

IN  

90%  
10%  
90%  
D
OUT  
V
V
V
GS  
10%  
INVERTED  
R

GEN  

G
90%  
50%  
50%  
S
IN  
V
10%  
PULSE WIDTH  
Figure 10. Switching Waveforms  
Figure 9. Switching Test Circuit  
10

0  

D=0.5  
0.2  
10

-1  

0.1  
0.05  
0.02  
P
DM  
t
1  
t
2  
0.01  
10

-2  

1. R
θ
JA
(t)=r (t) * R
θ
JA  
2. R
θ
JA
=See Datasheet  
3. T
JM-
T
A
= P* R
θ
JA
(t)  
4. Duty Cycle, D=t1/t2  
Single Pulse  
10

-3  

10

-4  

10

-3  

10

-2  

10

-1  

10

0  

10

1  

10

2  

Square Wave Pulse Duration (sec)  
Figure 11. Normalized Thermal Transient Impedance Curve  
4