CET-Chino-Excel-Tech-CEP80N15
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CEP80N15/CEB80N15
CEF80N15
N-Channel Enhancement Mode Field Effect Transistor
PRELIMINARY
FEATURES
Type
V
DSS
150V
150V
150V
R
DS(ON)
19m
Ω
19m
Ω
19m
Ω
I
D
@V
GS
10V
CEP80N15
CEB80N15
CEF80N15
76A
76A
76A
d
10V
10V
Super high dense cell design for extremely low R
DS(ON)
.
D
High power and current handing capability.
Lead-free plating ; RoHS compliant.
TO-220 & TO-263 & TO-220F full-pak for through hole.
G
S
CEB SERIES
TO-263(DD-PAK)
CEP SERIES
TO-220
CEF SERIES
TO-220F
ABSOLUTE MAXIMUM RATINGS
T =
25 C unless otherwise noted
c
Limit
Parameter
Symbol
Units
TO-220/263
TO-220F
76
d
Drain-Source Voltage
V
DS
V
GS
150
V
V
A
Gate-Source Voltage
±
20
76
Drain Current-Continuous @ T
C
= 25 C
@ T
C
= 100 C
Drain Current-Pulsed
a
I
D
55
d
304
d
68
A
A
55
304
300
2
e
I
DM
Maximum Power Dissipation @ T
C
= 25 C
– Derate above 25 C
W
P
D
0.5
W/ C
C
Operating and Store Temperature Range
T
J
,T
stg
-55 to 175
Thermal Characteristics
Parameter
Symbol
R
θ
JC
Limit
Units
C/W
C/W
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
0.5
62.5
2.2
65
R
θ
JA
This is preliminary information on a new product in development now .
Details are subject to change without notice .
Rev 1.
2012.Mar.
1
CEP80N15/CEB80N15
CEF80N15
Electrical Characteristics
T =
25 C unless otherwise noted
c
Parameter
Off Characteristics
Symbol
Test Condition
Min
Typ
Max
Units
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate Body Leakage Current, Forward
Gate Body Leakage Current, Reverse
On Characteristics
b
BV
DSS
I
DSS
V
GS
= 0
V
,
I
D
= 250
µ
A
V
DS
= 150
V
,
V
GS
= 0V
V
GS
= 20
V
,
V
DS
= 0V
V
GS
= -20
V
,
V
DS
= 0V
150
V
1
µ
A
nA
nA
I
GSSF
I
GSSR
100
-100
Gate Threshold Voltage
V
GS(th)
R
DS(on)
V
GS
= V
DS
, I
D
= 250
µ
A
V
GS
= 10
V
,
I
D
= 35A
2
4
V
Static Drain-Source
14
19
m
Ω
On-Resistance
Dynamic Characteristics
c
Input Capacitance
C
iss
C
oss
C
rss
8540
455
pF
pF
pF
V
DS
= 25
V
,
V
GS
= 0
V
,
f = 800KHz
Output Capacitance
Reverse Transfer Capacitance
Switching Characteristics
c
Turn-On Delay Time
Turn-On Rise Time
365
t
d(on)
t
r
t
d(off)
t
f
45
24
90
48
ns
ns
V
DD
= 76
V
,
I
D
= 38A,
V
GS
= 10
V
,
R
GEN
= 5
Ω
Turn-Off Delay Time
Turn-Off Fall Time
193
33
386
66
ns
ns
T
o
tal Gate Charge
Q
g
262
53
340
nC
nC
nC
V
DS
= 76
V
,
I
D
= 38A,
V
GS
= 10V
Gate-Source Charge
Gate-Drain Charge
Q
gs
Q
gd
83
Drain-Source Diode Characteristics and Maximun Ratings
f
Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage
b
I
S
76
A
V
V
SD
V
GS
= 0
V
,
I
S
= 76A
g
1.2
Notes :
a.Repetitive Rating : Pulse width limited by maximum junction temperature .
b.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2% .
c.Guaranteed by design, not subject to production testing.
d.Limited only by maximum temperature allowed .
e .Pulse width limited by safe operating area .
f .Full package I
= 37A .
S(max)
g.Full package V
test condition I
= 37A .
SD
S
2
CEP80N15/CEB80N15
CEF80N15
60
50
40
30
20
10
0
100
-55 C
T
J
=125 C
V
GS
=10,
9,8,6V
80
60
V
GS
=5V
40
20
0
25 C
0
1
2
3
4
5
0
2
4
6
8
10
V
DS
, Drain-to-Source Voltage (V)
V
GS
, Gate-to-Source Voltage (V)
Figure 1. Output Characteristics
Figure 2. Transfer Characteristics
3.0
2.5
2.0
1.5
1.0
0.5
0.0
9000
7500
6000
4500
3000
1500
0
I
D
=35A
V
GS
=10V
C
iss
C
oss
C
rss
0
5
10
15
20
25
-100
-50
0
50
100
150
200
V
DS
, Drain-to-Source Voltage (V)
T
J
, Junction Temperature( C)
Figure 3. Capacitance
Figure 4. On-Resistance
V
a
riation
with
T
e
mperature
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
V
DS
=V
GS
I
D
=250µA
V
GS
=0V
10
2
10
1
10
0
-50 -25
0
25 50 75 100 125 150
0.4
0.6
0.8
1.0
1.2
1.4
T
J
, Junction Temperature( C)
V
SD
, Body Diode Forward Voltage (V)
Figure 5. Gate Threshold Variation
with Temperature
Figure 6. Body Diode Forward Voltage
Variation with Source Current
3
CEP80N15/CEB80N15
CEF80N15
10
3
10
8
V
DS
=75V
I
D
=38A
R
DS(ON)
Limit
100
µ
s
10
2
6
1ms
10ms
4
10
1
DC
2
T
C
=25 C
T
J
=175 C
Single Pulse
10
0
0
10
0
10
1
10
2
10
3
0
66
132
198
264
Qg, Total Gate Charge (nC)
-V
DS
, Drain-Source Voltage (V)
Figure 7. Gate Charge
Figure 8. Maximum Safe
Operating Area
V
DD
on
t
t
off
d(off)
t
r
t
R
L
t
d(on)
OUT
f
t
V
IN
90%
10%
90%
D
OUT
V
V
V
GS
10%
INVERTED
R
GEN
G
90%
50%
50%
S
IN
V
10%
PULSE WIDTH
Figure 10. Switching Waveforms
Figure 9. Switching Test Circuit
10
0
D=0.5
0.2
P
DM
10
-1
0.1
t
1
t
2
0.05
0.02
0.01
1. R
θ
JC
(t)=r (t) * R
θ
JC
2. R
θ
JC
=See Datasheet
3. T
JM-
T
C
= P* R
θ
JC
(t)
4. Duty Cycle, D=t1/t2
Single Pulse
10
-2
10
-1
10
0
10
1
10
2
10
3
10
4
10
-2
Square Wave Pulse Duration (msec)
Figure 11. Normalized Thermal Transient Impedance Curve
4
