CRMICRO-FTP20N60A
| Part # | CRMICRO-FTP20N60A |
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FTP20N60A
Pb
N-Channel MOSFET
Applications:
Lead Free Package and Finish
V
DSS
R
DS(ON)
(
Type
.)
0.
3
5
Ω
I
D
• Adaptor
• TV Main Power
• SMPS Power Supply
• LCD Panel Power
600 V
20 A
D
Features:
• RoHS Compliant
• Low ON Resistance
• Low Gate Charge
• Peak Current vs Pulse Width Curve
G
G
D
S
Ordering Information
TO-220
Packages
S
PART NUMBER
PACKAGE
BRAND
FTP20N60A
TO-220
FTP20N60A
Not to Scale
Absolute Maximum Ratings
T
C
=25
o
C unless otherwise specified
Symbol
V
DSS
Parameter
Drain-to-Source Voltage
FTP20N60A
600
Units
V
(NOTE *1)
(NOTE *2)
I
D
Continuous Drain Current
Continuous Drain Current
Pulse
d
D
rai
n
C
urrent
,
V
GS
@ 10V
Power Dissipation
20.0
I
D
@ 100
o
C
Figure 3
Figure 6
250
A
I
DM
W
W/
o
C
V
P
D
Derating Factor above 25
o
C
2.0
V
GS
E
AS
Gate-to-Source Voltage
± 30
Single Pulse Avalanche Engergy
L=10 mH
1000
mJ
I
AS
Pulsed Avalanche Rating
Figure 8
5.0
A
dv/dt
Peak Diode Recovery dv/dt
Maximum Temperature for Soldering
(NOTE *3)
V/ns
T
L
T
PKG
Leads at 0.063 in (1.6 mm) from Case for 10 seconds
Package Body for 10 seconds
300
260
o
C
Operating Junction and Storage
Temperature Range
T
J
and T
STG
-55 to 150
*
Drain Current Limited by Maximum Junction Temperature
Caution:
Stresses greater than those listed in the “Absolute Maximum Ratings” Table may cause permanent damage to the device.
Thermal Resistance
Symbol
Parameter
Junction-to-Case
Junction-to-Ambient
FTP20N60A
Units
o
C/W
Test Conditions
Drain lead soldered to water cooled heatsink, P
ad-
D
R
θ
JC
0.5
justed for a peak junction temperature of +150
o
C
.
R
θ
JA
62.5
1 cubic foot chamber, free air.
Page 1 of
9
©
2010 InPower Semiconductor Co., Ltd.
FTP20N60A REV.
B
.
Ap
r. 2010
OFF Characteristics
T =25
o
C unless otherwise specified
J
Symbol
BV
DSS
Parameter
Min.
600
Typ.
—
Max.
—
Units
V
Test Conditions
Drain-to-Source Breakdown Voltage
V
GS
=0V, I
D
=250µA
Reference to 25
o
C,
BreakdownVoltage Temperature
Coefficient, Figure 11.
V/
o
C
—
—
0.51
—
—
Δ
BV
DS
S
/
Δ
T
J
I
D
=250µA
10
V
DS
=600V, V
GS
=0V
I
DSS
Drain-to-Source Leakage Current
µA
V
DS
=480V, V
GS
=0V
T
J
=12
5
o
C
—
—
250
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
—
—
—
—
100
V
GS
=+30V
V
GS
= -30V
I
GSS
nA
-100
ON Characteristics
T =25
o
unless otherwise specified
C
J
Symbol
R
DS(ON)
V
GS(TH)
gfs
Parameter
Min.
Typ.
0.35
—
Max.
0.45
4.0
Units
Test Conditions
V
GS
=10V, I
D
=9.0A
Static Drain-to-Source On-Resistance
Figure 9 and 10.
—
Ω
(NOTE *4)
,
250
μ
A
I
D
=
GS
Gate Threshold Voltage, Figure 12.
Forward Transconductance
2.0
—
V
DS
V
=
V
S
V
DS
=15V, I
D
=10A
15
—
(NOTE *4)
Dynamic Characteristics
Essentially independent of operating temperature
Symbol
C
iss
Parameter
Input Capacitance
Min.
—
Typ.
2830
245
Max.
Units
Test Conditions
V
GS
=0V
—
—
V
DS
=25V
C
oss
Output Capacitance
—
pF
f =1.0MHz
Figure 14
C
rss
Reverse Transfer Capacitance
—
17
—
Q
g
Total Gate Charge
—
—
55
14
—
—
V
=300V
DD
I
Q
gs
Q
gd
Gate-to-Source Charge
nC
D=18A
Figure 15
Gate-to-Drain (“Miller”) Charge
—
21
—
Resistive Switching Characteristics
Essentially independent of operating temperature
Symbol
t
d(ON)
Parameter
Turn-on Delay Time
Min.
—
Typ.
40
Max.
Units
Test Conditions
V
DD
=300V
I
D
=18A
—
—
—
t
rise
Rise Time
—
75
ns
t
d(OFF)
t
fall
Turn-Off Delay Time
—
150
V
GS
=10V
R
G
=25
Ω
Fall Time
—
80
—
Page 2 of
9
©
2010 InPower Semiconductor Co., Ltd.
FTP20N60A REV.
B. Apr.
2010
Source-Drain Diode Characteristics
T =25
o
C unless otherwise specified
c
Symbol
Parameter
Continuous Source Current (Body Diode)
Maximum Pulsed Current (Body Diode)
Diode Forward Voltage
Min.
—
Typ.
Max.
Units
Test Conditions
I
S
—
—
20
80
1.5
—
A
A
Integral pn-diode
in MOSFET
I
SM
—
—
—
—
V
SD
I
S
=20A, V
GS
=0V
V
GS
=0V
—
V
t
rr
Reverse Recovery Time
615
5.8
ns
Q
rr
Reverse Recovery Charge
—
I
F
=20A, di/dt=100 A/µs
nC
Notes:
*1. T
= +25
o
C to +150
o
C.
J
*2. Repetitive rating; pulse width limited by maximum junction temperature.
*3. I
= 20 A, di/dt < 100 A/µs, V
< BV
, T =+150
o
C.
SD
DD
DSS
J
*4. Pulse width < 380µs; duty cycle < 2%.
Page 3 of
9
©
2010 InPower Semiconductor Co., Ltd.
FTP20N60A REV.
B. Apr.
2010
Figure 1. Maximum Effective Thermal Impedance, Junction-to-Case
Duty Factor
1.000
0.100
0.010
50%
20%
10%
2%
1%
P
DM
t
1
t
2
0.001
NOTES:
single pulse
DUTY FACTOR: D=t1/t2
PEAK T
=P x
Z x
R
+T
J
DM
θ
JC
θ
JC
C
0.0001
10E-6
1E-3
1E+0
1E-6
100E-6
10E-3
100E-3
10E+0
t
p
, Rectangular Pulse Duration (s)
F i g u r e
3 .
Maximum Power Dissipation
vs Case Temperature
Maximum Continuous Drain Current
vs Case Temperature
Figure 2.
250
200
150
20
15
10
100
50
0
5
0
25
50
75
100
125
150
25
50
75
100
125
150
T ,
Case Temperature (
o
)
C
T ,
Case Temperature (
o
)
C
C
C
F i g u r e
5 .
Typical Drain-to-Source ON Resistance
vs Gate Voltage and Drain Current
Figure 4. Typical Output Characteristics
2.1
20
PULSE DURATION = 250 µS
DUTY FACTOR = 0.5%
PULSE DURATION = 10 µS
DUTY FACTOR = 0.5% MAX
MAX, T
= 25
o
C
T
= 2
5
o
C
C
C
V
GS
= 7.0V
V
GS
= 6.5V
15
10
1.4
0.7
0.0
I
I
I
I
= 40A
= 20A
= 1
0
A
= 5.0A
D
D
D
D
V
GS
= 6.0V
V
GS
= 5.5V
V
GS
= 5.0V
5
0
18
0
3
6
9
12
15
4
12
6
8
10
14
V
DS
, Drain-to-Source Voltage (
)
V
GS
, Gate-to-Source Voltage (
)
V
V
Page 4 of
9
©
2010 InPower Semiconductor Co., Ltd.
FTP20N60A REV.
B. Apr.
2010
Figure 6. Maximum Peak Current Capability
1000
100
TRANSCONDUCTANCE
MAY LIMIT CURRENT IN
THIS REGION
FOR TEMPERATURES
ABOVE 25
o
C DERATE PEAK
CURRENT AS FOLLOWS:
150
–
T
C
I
=
I
——————–
125
25
10
V
= 10V
GS
1
10E-6
100E-6
1E-3
10E-3
100E-3
1E+0
10E+0
t
p
, Pulse Width (s)
Figure 7. Typical Transfer Characteristics
Unclamped Inductive
Switching Capability
F i g u r e
8 .
25
20
100
PULSE DURATION = 380 µs
DUTY CYCLE = 0.5% MAX
V
= 30 V
DS
STARTING T
= 2
5
o
C
J
10
1
15
10
5
STARTING T
= 15
0
o
C
J
+150
o
C
+25
o
C
-55
o
C
If R= 0: t
= (L×I
)/(1.3BV
AV AS
-V )
DSS DD
If R
≠
0: t
= (L/R) ln[I
×R)/(1.3BV
-V )+1]
AV AS
DSS DD
R equals total Series resistance of Drain circuit
0.1
1E-6
0
4
7
5
6
7
100E-6
1E-3
10E-3
10E-6
t
AV
, Time in Avalanche (s)
V
GS
, Gate-to-Source Voltage (
)
V
Figure 9.
Figure 10.
Typical Drain-to-Source
e
Typical Drain-to-Source ON
Resistance vs Drain Current
Resistanc
ON
vs Junction Temperature
1.8
1.5
1.2
2.75
2.50
2.25
2.00
1.75
PULSE DURATION = 10 µs
DUTY CYCLE = 0.5% MAX
T
C
=25°C
1.50
1.25
1.00
0.75
0.9
0.6
0.3
0.0
V
= 10V
GS
PULSE DURATION = 10 µs
DUTY CYCLE = 0.5% MAX
= 10V, I
= 10.0A
0.50
0.25
V
D
GS
0
5
10
15
-75 -50
-25
0
25
50
75 100
125
150
20
25
30
I
D
, Drain Current (A)
T
J
, Junction Temperature (
o
)
C
Page 5 of
9
©
2010 InPower Semiconductor Co., Ltd.
FTP20N60A REV.
B. Apr.
2010
Figure 11.
Typical Breakdown Voltage vs
Junction Temperature
Figure 12.
Typical Threshold Voltage vs
Junction Temperature
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
1.15
1.10
1.05
1.00
0.95
0.90
V
I
= 0V
V
I
= V
DS
GS
= 250 µA
GS
= 250 µA
D
D
-75
-25
0
25
50
75 100
125 150
-75 -50
-25
0
25
50
75 100
125 150
–
50
T
J
, Junction Temperature (
o
C)
T
J
, Junction Temperature (
o
C)
Figure 14.
Typical Capacitance vs
Drain-to-Source Voltage
Figure 13.
Maximum Forward Bias Safe
Operating Area
100.0
10.0
10000
10µs
C
iss
1000
100
10
100µ
1ms
C
oss
1.0
0.1
10m
DC
s
V
= 0V, f = 1MHz
= C
+ C
OPERATION IN THIS AREA
GS
MAY BE LIMITED BY R
C
C
C
iss
gs
gd
DS(ON)
C
rss
≅
C +
C
oss
rss
ds gd
T
T
= MAX RATED
= 25
o
C
J
= C
gd
C
1
1
10
100
1000
0.1
1
10
100
1000
V
DS
, Drain-to-Source Voltage (V)
V
DS
, Drain Voltage (V)
Figure 15.
Typical Gate Charge
vs Gate-to-Source Voltage
Figure 16.
Typical Body Diode Transfer
Characteristics
12
10
60
50
40
30
20
10
V
V
V
= 150V
= 300V
= 480V
DS
DS
DS
8
6
+15
0
o
C
+25
o
C
4
2
0
I
= 18A
V
= 0V
D
GS
0
0
10
20
30
40
50
60
0.2
0.4
V
0.6
0.8
1.0
1.2
1.4
Q
G
,
T
otal Gate Charge (nC)
SD
, Source-to-Drain Voltage (V)
Page 6 of
9
©
2010 InPower Semiconductor Co., Ltd.
FTP20N60A REV.
B. Apr.
2010
Test Circuits and Waveforms
V
DS
I
D
I
D
V
DS
V
Miller
GS
Region
V
GS
V
DD
D.U.T.
V
GS(TH)
1 mA
Q
Q
gs
gd
Q
g
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveform
V
DS
R
L
90%
V
DS
V
GS
V
DD
R
D.U.T.
G
10%
t
V
GS
t
t
t
d(OFF)
fall
d(ON)
rise
Figure 19. Resistive Switching Test Circuit
Figure 20. Resistive Switching Waveforms
Page 7 of
9
©
2010 InPower Semiconductor Co., Ltd.
FTP20N60A REV.
B. Apr.
2010
Test Circuits and Waveforms
di/dt adj.
Current
Pump
di/dt = 100A/µA
I
D
Double Pulse
D.U.T.
V
DD
Q
rr
L
t
rr
I
D
Figure 22. Diode Reverse Recovery Waveform
Figure 21. Diode Reverse Recovery Test Circuit
BV
DSS
Series Switch
(MOSFET)
L
I
AS
BV
DSS
V
DD
V
D.U.T.
DD
Commutating
Diode
0
t
AV
V
50
Ω
GS
I
AS
V
t
GS
p
2
I
L
AS
E
=
AS
2
Figure 23. Unclamped Inductive Switching Test Circuit
Figure 24. Unclamped Inductive Switching Waveforms
Page 8 of
9
©
2010 InPower Semiconductor Co., Ltd.
FTP20N60A REV.
B. Apr.
2010
Disclaimers:
InPower Semiconductor Co., Ltd (IPS) reserves the right to make changes without notice in order to improve reliability, function
or design and to discontinue any product or service without notice. Customers should obtain the latest relevant information before
orders and should verify that such information is current and complete. All products are sold subject to IPS’s terms and conditions
supplied at the time of order acknowledgement.
InPower Semiconductor Co., Ltd warrants performance of its hardware products to the specifications at the time of sale,
T
e
sting,
reliability and quality control are used to the extent IPS deems necessary to support this warrantee. Except where agreed upon
by contractual agreement, testing of all parameters of each product is not necessarily performed.
InPower Semiconductor Co., Ltd does not assume any liability arising from the use of any product or circuit designs described
herein. Customers are responsible for their products and applications using IPS’s components.
T
o
m
inimize risk, customers must
provide adequate design and operating safeguards.
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the rights of others. Reproduction of information in IPS’s data sheets or data books is permissible only if reproduction is without
modification or alteration. Reproduction of this information with any alteration is an unfair and deceptive business practice.
InPower Semiconductor Co., Ltd is not responsible or liable for such altered documentation.
Resale of IPS’s products with statements different from or beyond the parameters stated by InPower Semiconductor Co., Ltd
for that product or service voids all express or implied warrantees for the associated IPS’s product or service and is unfair and
deceptive business practice. InPower Semiconductor Co., Ltd is not responsible or liable for any such statements.
Life Support Policy:
InPower Semiconductor Co., Ltd’s products are not authorized for use as critical components in life support devices or
systems without the expressed written approval of InPower Semiconductor Co., Ltd.
As used herein:
1. Life support devices or systems are devices or systems which:
a. are intended for surgical implant into the human body,
b. support or sustain life,
c. whose failure to perform when properly used in accordance with instructions
for used provided in the labeling, can be reasonably expected to result in significant
injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Page 9 of
9
©
2010 InPower Semiconductor Co., Ltd.
FTP20N60A REV.
B. Apr.
2010
