HopeRF-Micro-electronics-CMT2119A-ESR
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A
CMT2119A
240 – 960 MHz (G)FSK/OOK Transmitter
Features
Applications
Optional Chip Feature Configuration Schemes
On-Line Registers Configuration
Off-Line EEPROM Programming
Frequency Range: 240 to 960 MHz
FSK, GFSK and OOK Modulation
Symbol Rate:
Low-Cost Consumer Electronics Applications
Home and Building Automation
Remote Fan Controllers
Infrared Transmitter Replacements
Industrial Monitoring and Controls
Remote Lighting Control
0.5 to 100 ksps (FSK/GFSK)
0.5 to 30 ksps (OOK)
Wireless Alarm and Security Systems
Remote Keyless Entry (RKE)
Deviation: 1.0 to 200 kHz
Two-wire Interface for Registers Accessing and
EEPROM Programming
Ordering Information
Output Power: -10 to +13 dBm
Supply Voltage: 1.8 to 3.6 V
Sleep Current: < 20 nA
Part Number
Frequency
Package
MOQ
CMT2119A-ESR
868.35 MHz
SOT23-6
3,000 pcs
FCC/ETSI Compliant
RoHS Compliant
6-pin SOT23-6 Package
Descriptions
The CMT2119A is a high performance, highly flexible,
low-cost, single-chip (G)FSK/OOK transmitter for various
240 to 960 MHz wireless applications. It is a part of the
CMOSTEK NextGenRF
TM
family, which includes a complete
line of transmitters, receivers and transceivers. The
CMT2119A provides the simplest way to control the data
transmission. The transmission is started when an effective
level turnover is detected on the DATA pin, while the
transmission action will stop after the DATA pin holding level
low for a defined time window, or after a two-wire interface
(TWI) command is issued. The chip features can be
configured in two different ways: setting the configuration
registers through the TWI, or programming the embedded
EEPROM with CMOSTEK USB Programmer and the
RFPDK. The device operates from a supply voltage of 1.8 V
to 3.6
V
,
c
onsumes 27.6 mA (FSK @ 868.35 MHz) when
transmitting +10 dBm output power, and only leak 20 nA
when it is in sleep state. The CMT2119A transmitter
together with the CMT2219A receiver enables a robust RF
link.
SOT23-6
6
1
2
3
VDD
XTAL
GND
5
4
RFO
CLK
DATA
CMT2119A
Rev 0.9 | Page 1/29
Copyright © By CMOSTEK
CMT2119A
Typical Application
CMT2119A
XTAL VDD
X1
VDD VDD
C0
1
2
3
6
5
4
ANT
C2
J1
VDD
MCU
U2
1
2
3
4
L1
DATA
CLK
DATA
CLK
L2
U1
GND
RFO
CLK
C1
Note: Connector
J1 is for EEPROM
Programming
DATA
CLK
DATA
Optional
Figure 1. CMT2119A Typical Application Schematic
Table 1. BOM of 433.92/868.35 MHz Low-Cost Application
Value
Designator
Descriptions
Unit
Manufacturer
433.92 MHz
868.35 MHz
CMT2119A, 240 – 960 MHz (G)FSK/OOK
transmitter
U1
U2
–
–
–
–
CMOSTEK
–
Optional MCU for on-line register
configuration
26
X1
C0
C1
C2
L1
L2
±20 ppm, SMD32*25 mm crystal
±20%, 0402 X7R, 25 V
MHz
uF
EPSON
0.1
Murata GRM15
Murata GRM15
Murata GRM15
Murata LQG18
Murata LQG18
±5%, 0402 NP0, 50 V
82
9
82
3.9
100
8.2
pF
±5%, 0402 NP0, 50 V
pF
±5%, 0603 multi-layer chip inductor
±5%, 0603 multi-layer chip inductor
180
27
nH
nH
Rev 0.9 | Page 2/29
CMT2119A
Abbreviations
Abbreviations used in this data sheet are described below
AN
Application Notes
PA
Power Amplifier
BOM
BSC
Bill of Materials
PC
Personal Computer
Printed Circuit Board
Phase Noise
Basic Spacing between Centers
PCB
EEPROM
Electrically Erasable Programmable Read-Only
PN
Memory
RCLK
Reference Clock
ESD
ESR
ETSI
Electro-Static Discharge
Equivalent Series Resistance
European
T
e
lecommunications Standards
Institute
RF
Radio Frequency
RF Product Development Kit
RFPDK
RoHS
Rx
Restriction of Hazardous Substances
Receiving, Receiver
Small-Outline Transistor
Symbol Rate
FCC
FSK
GFSK
Max
Federal Communications Commission
Frequency Shift Keying
Gauss Frequency Shift Keying
Maximum
SOT
SR
TWI
Two-wire Interface
Transmission, Transmitter
Typical
Tx
MCU
Min
Microcontroller Unit
Typ
Minimum
USB
XO/XOSC
XTAL
PA
Universal Serial Bus
Crystal Oscillator
Crystal
MOQ
NP0
Minimum Order Quantity
Negative-Positive-Zero
Occupied Bandwidth
On-Off Keying
OBW
OOK
Power Amplifier
Rev 0.9 | Page 3/29
CMT2119A
Table of Contents
Rev 0.9 | Page 4/29
CMT2119A
1. Electrical
Characteristics
V
DD
= 3.3
V
, T
OP
= 25
℃
, F
RF
= 868.35 MHz, FSK modulation,
output power is +10 dBm terminated in a matched 50 Ω
impedance, unless otherwise noted.
1.1 Recommended Operating Conditions
Table 2. Recommended Operation Conditions
Parameter
Symbol
V
DD
Conditions
Min
1.8
-40
1
Typ
Max
3.6
85
Unit
V
Operation Voltage Supply
Operation
T
e
mperature
Supply Voltage Slew Rate
T
OP
℃
mV/us
1.2 Absolute Maximum Ratings
Table 3. Absolute Maximum Ratings
[1]
Parameter
Supply Voltage
Symbol
Conditions
Min
Max
3.6
Unit
V
V
DD
V
IN
-0.3
-0.3
-40
-50
Interface Voltage
Junction
T
e
mperature
Storage
T
e
mperature
Soldering
T
e
mperature
ESD Rating
V
DD
+ 0.3
125
V
T
J
℃
℃
℃
kV
mA
T
STG
T
SDR
150
Lasts at least 30 seconds
Human Body Model (HBM)
@ 85
℃
255
-2
2
Latch-up Current
Note:
-100
100
[1]. Stresses
above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
Caution!
ESD sensitive device. Precaution should be used when handling the device in order
to prevent permanent damage.
Rev 0.9 | Page 5/29
CMT2119A
1.3 Transmitter Specifications
Table 4. Transmitter Specifications
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Frequency Range
[1]
F
RF
240
960
MHz
Hz
F
RF
≤
480 MHz
F
RF
> 480 MHz
FSK/GFSK
OOK
198
397
Synthesizer Frequency
Resolution
F
RES
SR
Hz
0.5
0.5
100
30
ksps
ksps
Symbol Rate
(G)FSK Modulation
F
DEV
1
–
200
–
kHz
Deviation Range
Bandwidth-Time Product
Maximum Output Power
Minimum Output Power
Output Power Step Size
OOK PA Ramping Time
[2]
BT
GFSK modulation
0.5
+13
-10
1
–
dBm
dBm
dB
P
OUT(Max)
P
OUT(Min)
P
STEP
t
RAMP
0
1024
us
OOK, 0 dBm, 50% duty cycle
OOK, +10 dBm, 50% duty cycle
OOK, +13 dBm, 50% duty cycle
FSK, 0 dBm, 9.6 ksps
6.7
13.4
17.4
10.5
23.5
32.5
8.0
mA
mA
mA
Current Consumption
@ 433.92 MHz
I
DD-433.92
mA
mA
FSK, +10 dBm, 9.6 ksps
FSK, +13 dBm, 9.6 ksps
mA
OOK, 0 dBm, 50% duty cycle
OOK, +10 dBm, 50% duty cycle
OOK, +13 dBm, 50% duty cycle
FSK, 0 dBm, 9.6 ksps
mA
mA
15.5
19.9
12.3
27.6
36.1
20
mA
Current Consumption
@ 868.35 MHz
I
DD-868.35
mA
mA
FSK, +10 dBm, 9.6 ksps
FSK, +13 dBm, 9.6 ksps
mA
Sleep Current
I
SLEEP
nA
Frequency Tune Time
t
TUNE
370
-80
us
100 kHz offset from F
RF
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBm
dBm
dBm
dBm
dB
Phase Noise @ 433.92
MHz
PN
433.92
600 kHz offset from F
RF
-98
1.2 MHz offset from F
RF
-107
-74
100 kHz offset from F
RF
Phase Noise @ 868.35
MHz
PN
868.35
600 kHz offset from F
RF
-92
1.2 MHz offset from F
RF
-101
-52
H2
433.92
H3
433.92
H2
868.35
H3
868.35
2
nd
harm @ 867.84 MHz, +13 dBm P
OUT
3
rd
harm @ 1301.76 MHz, +13 dBm P
OUT
2
nd
harm @ 1736.7 MHz, +13 dBm P
OUT
3
rd
harm @ 2605.05 MHz, +13 dBm P
OUT
Harmonics Output for
433.92 MHz
[3]
-60
-67
Harmonics Output for
868.35 MHz
[3]
-55
OOK Extinction Ration
60
Notes:
[1]. The
frequency range is continuous over the specified range.
[2]. 0
and 2
n
us, n = 0 to 10, when set to “0”, the PA output power will ramp to its configured value in the shortest possible
time.
Rev 0.9 | Page 6/29
CMT2119A
1.4 Crystal Oscillator
Table 5. Crystal Oscillator Specifications
Parameter
Symbol
Conditions
Min
Typ
26
Max
Unit
MHz
ppm
pF
Crystal Frequency
[1]
Crystal
T
o
lerance
[2]
Load Capacitance
[3]
Crystal ESR
F
XTAL
26
26
±20
C
LOAD
Rm
12
20
60
Ω
XTAL Startup Time
[4]
t
X
T
A
L
400
us
Notes:
[1]. The CMT2119A can directly work with external 26 MHz reference clock input to XTAL pin (a coupling capacitor is
required) with amplitude 0.3 to 0.7 Vpp.
[2]. This
is the total tolerance including (1) initial tolerance, (2) crystal loading, (3) aging, and (4) temperature dependence.
The acceptable crystal tolerance depends on RF frequency and channel spacing/bandwidth.
[3]. The
required crystal load capacitance is integrated on-chip to minimize the number of external components.
[4]. This
parameter is to a large degree crystal dependent.
Rev 0.9 | Page 7/29
CMT2119A
2. Pin
Descriptions
6
5
4
1
2
3
VDD
RFO
CLK
XTAL
GND
DATA
Figure 2. CMT2119A Pin Assignments
Table 6. CMT2119A Pin Descriptions
Pin Number
Name
I/O
Descriptions
26 MHz single-ended crystal oscillator input or
External 26 MHz reference clock input
Ground
1
2
XTAL
GND
I
I
Data input to be transmitted or
Data pin to access the embedded EEPROM
Pulled down internally to GND when configured as Transmission Enabled by
DATA Pin Falling Edge and used as input pin
Pulled up internally to VDD when configured as Transmission Enabled by DATA
Pin Rising Edge and used as input pin
3
DATA
IO
Clock pin to control the device
4
CLK
I
Clock pin to access the embedded EEPROM
Pulled up internally to VDD
5
6
RFO
VDD
O
I
Power amplifier output
Power supply input
Rev 0.9 | Page 8/29
CMT2119A
3. Typical
Performance Characteristics
Phase Noise @ 868.35 MHz
Phase Noise @ 433.92 MHz
15
13.0 dBm
20
10
@ 868.35
MHz
13.4 dBm
@ 433.92
MHz
5
-5
0
-10
-20
-30
-40
-50
-60
-70
-15
-25
-35
-45
-55
-65
-55.9 dBm
@ 869.55
MHz
-56.7 dBm
@ 435.12 MHz
432.42 432.67 432.92 433.17 433.42 433.67 433.92 434.17 434.42 434.67 434.92 435.17 435.42
866.85 867.1 867.35 867.6 867.85 868.1 868.35 868.6 868.85 869.1 869.35 869.6 869.85
Frequency (MHz) (RBW=10 kHz)
Frequency (MHz) (RBW = 10 kHz)
Figure 3. Phase Noise, F
RF
= 433.92 MHz,
P
OUT
= +13 dBm, Unmodulated
Figure 4. Phase Noise, F
RF
= 868.35 MHz,
P
OUT
= +13 dBm, Unmodulated
FSK vs. GFSK
OOK Spectrum, SR = 9.6 ksps
20
10
10
0
-10
-20
-30
-40
-50
0
FSK
-10
-20
-30
-40
-50
GFSK
433.18
433.37
433.55
433.74
433.92
434.11
434.29
434.48
434.66
433.62
433.72
433.82
433.92
434.02
434.12
434.22
Frequency (MHz)
Frequency (MHz)
Figure 5. OOK Spectrum, SR = 9.6 ksps,
P
OUT
= +10 dBm, t
RAMP
= 32 us
Figure 6. FSK/GFSK Spectrum,
SR = 9.6 ksps, F
DEV
= 15 kHz
Spectrum of Various
P
A Ramping Options
P
OUT
vs. V
DD
10
14
1024 us
512 us
256 us
128 us
64 us
12
10
8
0
-10
-20
-30
-40
-50
SR = 1.2 ksps
32 us
0 dBm
6
+10 dBm
+13 dBm
4
2
0
-2
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
433.17
433.37
433.57
433.77
433.97
434.17
434.37
434.57
Frequency (MHz)
Supply Voltage VDD (V)
Figure 7. Spectrum of PA Ramping,
SR = 1.2 ksps, P
OUT
= +10 dBm
Figure 8. Output Power vs. Supply
Voltages, F
RF
= 433.92 MHz
Rev 0.9 | Page 9/29
CMT2119A
4. Typical
Application Schematics
4.1 Low-Cost Application Schematic
CMT2119A
X1
VDD VDD
C0
1
2
3
6
5
4
ANT
C2
J1
VDD
XTAL
GND
VDD
RFO
CLK
MCU
U2
1
2
3
4
L1
DATA
CLK
DATA
CLK
L2
U1
C1
Note: Connector
J1 is for EEPROM
Programming
DATA
CLK
DATA
Optional
Figure 9. Low-Cost Application Schematic
Notes:
1. Connector
J1 is a must for the CMT2119A EEPROM access during development or manufacture.
2. An
external MCU U2 is necessary if on-line register configuration is required.
3. The
general layout guidelines are listed below. For more design details, please refer to “AN101 CMT211xA Schematic and
PCB Layout Design Guideline”
Use as much continuous ground plane metallization as possible.
Use as many grounding vias (especially near to the GND pins) as possible to minimize series parasitic inductance
between the ground pour and the GND pins.
Avoid using long and/or thin transmission lines to connect the components.
Avoid placing the nearby inductors in the same orientation to reduce the coupling between them.
Place C0 as close to the CMT2119A as possible for better filtering.
4. The
table below shows the BOM of 433.92/868.35 MHz Low-Cost Applications. For the BOM of 315/915 MHz application,
please refer to “AN101 CMT211xA Schematic and PCB Layout Design Guideline”.
Table 7. BOM of 433.92/868.35 MHz Low-Cost Application
Value
Designator
Descriptions
Unit
Manufacturer
433.92 MHz
868.35 MHz
CMT2119A, 240 – 960 MHz (G)FSK/OOK
transmitter
U1
U2
–
–
–
–
CMOSTEK
–
Optional MCU for on-line register
configuration
26
X1
C0
C1
C2
L1
L2
±20 ppm, SMD32*25 mm crystal
±20%, 0402 X7R, 25 V
MHz
uF
EPSON
0.1
Murata GRM15
Murata GRM15
Murata GRM15
Murata LQG18
Murata LQG18
±5%, 0402 NP0, 50 V
82
9
82
3.9
100
8.2
pF
±5%, 0402 NP0, 50 V
pF
±5%, 0603 multi-layer chip inductor
±5%, 0603 multi-layer chip inductor
180
27
nH
nH
Rev 0.9 | Page 10/29
CMT2119A
4.2 FCC/ETSI Compliant Application Schematic
CMT2119A
X1
VDD
VDD
C0
1
2
3
6
5
4
ANT
J1
VDD
XTAL
GND
VDD
RFO
CLK
MCU
U2
1
2
3
4
L1
DATA
CLK
DATA
CLK
L2
L3
C2
U1
C1
C3
Note: Connector
J1 is for EEPROM
Programming
DATA
CLK
DATA
Optional
Figure 10. FCC/ETSI Compliant Application Schematic
Notes:
1. Connector
J1 is a must for the CMT2119A EEPROM access during development or manufacture.
2. An
external MCU U2 is necessary if on-line register configuration is required.
3. The
general layout guidelines are listed below. For more design details, please refer to “AN101 CMT211xA Schematic and
PCB Layout Design Guideline”.
Use as much continuous ground plane metallization as possible.
Use as many grounding vias (especially near to the GND pins) as possible to minimize series parasitic inductance
between the ground pour and the GND pins.
Avoid using long and/or thin transmission lines to connect the components.
Avoid placing the nearby inductors in the same orientation to reduce the coupling between them.
Place C0 as close to the CMT2119A as possible for better filtering.
4. The
table below shows the BOM of 433.92/868.35 MHz FCC/ETSI Compliant Application. For the BOM of 315 and 915
MHz application, please refer to “AN101 CMT211xA Schematic and PCB Layout Design Guideline”.
Table 8. BOM of 433.92/868.35 MHz FCC/ETSI Compliant Application
Value
Designator
Descriptions
Unit
Manufacturer
433.92 MHz
868.35 MHz
CMT2119A, 240 – 960 MHz (G)FSK/OOK
transmitter
–
–
–
–
U1
U2
CMOSTEK
–
Optional MCU for on-line register
configuration
X1
C0
C1
C2
C3
L1
L2
L3
±20 ppm, SMD32*25 mm crystal
±20%, 0402 X7R, 25 V
26
MHz
uF
EPSON
0.1
Murata GRM15
Murata GRM15
Murata GRM15
Murata GRM15
Murata LQG18
Murata LQG18
Murata LQG18
±5%, 0402 NP0, 50 V
68
15
68
9.1
8.2
100
8.2
8.2
pF
±5%, 0402 NP0, 50 V
pF
±5%, 0402 NP0, 50 V
15
pF
±5%, 0603 multi-layer chip inductor
±5%, 0603 multi-layer chip inductor
±5%, 0603 multi-layer chip inductor
180
36
nH
nH
nH
18
Rev 0.9 | Page 11/29
CMT2119A
5. Functional
Descriptions
VDD
LDOs
GND
POR
Bandgap
XOSC
VCO
XTAL
PFD/CP
Loop Filter
RFO
PA
Fractional-N
DIV
Ramp
Control
EEPROM
Modulator
CLK
Interface and Digital Logic
DATA
Figure 11. CMT2119A Functional Block Diagram
5.1 Overview
The CMT2119A is a high performance, highly flexible, low-cost, single-chip (G)FSK/OOK transmitter for various 240 to 960
MHz wireless applications. It is part of the CMOSTEK NextGenRF
TM
family, which includes a complete line of transmitters,
receivers and transceivers. The chip is optimized for the low system cost, low power consumption, battery powered application
with its highly integrated and low power design.
The functional block diagram of the CMT2119A is shown in the figure above. The CMT2119A is based on direct synthesis of
the RF frequency, and the frequency is generated by a low-noise fractional-N frequency synthesizer. It uses a 1-pin crystal
oscillator circuit with the required crystal load capacitance integrated on-chip to minimize the number of external components.
Every analog block is calibrated on each Power-on Reset (POR) to the internal voltage reference. The calibration can help the
chip to finely work under different temperatures and supply voltages. The CMT2119A uses the DATA pin for the host MCU to
send in the data. The input data will be modulated and sent out by a highly efficient PA, which output power can be configured
from -10 to +13 dBm in 1 dB step size
The user can directly use the CMT2119A default configuration for immediate demands. If that cannot meet the system
requirement, on-line register configuration and off-line EEPROM programming configuration are available for the user to
customize the chip features. The on-line configuration means there is an MCU available in the application to configure the chip
registers through the 2-wire interface, while the off-line configuration is done by the CMOSTEK USB Programmer and the
RFPDK. After the configuration is done, only the DATA pin is required for the host MCU to send in the data and control the
transmission. The CMT2119A operates from 1.8 to 3.6 V so that it can finely work with most batteries to their useful power
limits. It only consumes 15.5 mA (OOK @ 868.35 MHz) / 27.6 mA (FSK @ 868.35 MHz) when transmitting +10 dBm power
under 3.3 V supply voltage.
5.2 Modulation, Frequency, Deviation and Symbol Rate
The CMT2119A supports GFSK/FSK modulation with the symbol rate up to 100 ksps, as well as OOK modulation with the
symbol rate up to 30 ksps. The supported deviation of the (G)FSK modulation ranges from 1 to 200 kHz. The CMT2119A
continuously covers the frequency range from 240 to 960 MHz, including the license free ISM frequency band around 315 MHz,
433.92 MHz, 868.35 MHz and 915 MHz. The device contains a high spectrum purity low power fractional-N frequency
synthesizer with output frequency resolution better than 198 Hz when the frequency is less than 480 MHz, and is about 397 Hz
Rev 0.9 | Page 12/29
CMT2119A
when the frequency is larger than 480 MHz. See the table below for the modulation, frequency and symbol rate specifications.
Table 9. Modulation, Frequency and Symbol Rate
Parameter
Value
(G)FSK/OOK
240 to 960
1 to 200
198
Unit
–
Modulation
Frequency
Deviation
MHz
kHz
Hz
Frequency Resolution (F
RF
≤
480 MHz)
Frequency Resolution (F
RF
> 480 MHz)
Symbol Rate (FSK/GFSK)
397
Hz
0.5 to 100
0.5 to 30
ksps
ksps
Symbol Rate (OOK)
5.3 Embedded EEPROM and RFPDK
The RFPDK (RF Products Development Kit) is a very user-friendly software tool delivered for the user configuring the
CMT2119A in the most intuitional way. The user only needs to fill in/select the proper value of each parameter and click the
“Burn” button to complete the chip configuration. See the figure below for the accessing of the EEPROM
and
T
a
ble 10
for the
summary of all the configurable parameters of the CMT2119A in the RFPDK.
CMT2119A
RFPDK
EEPROM
CLK
CMOSTEK USB
Programmer
Interface
DATA
Figure 12. Accessing Embedded EEPROM
For more details of the CMOSTEK USB Programmer and the RFPDK, please refer to “AN103 CMT211xA-221xA One-Way RF
Link Development Kits Users Guide”. For the detail of CMT2119A configurations with the RFPDK, please refer to “AN122
CMT2113/19A Configuration Guideline”.
Rev 0.9 | Page 13/29
CMT2119A
Table 10. Configurable Parameters in RFPDK
Descriptions
Category
Parameters
Default
Mode
To
i
nput a desired transmitting radio frequency in
the range from 240 to 960 MHz. The step size is
0.001 MHz.
Basic
Frequency
868.35 MHz
Advanced
Basic
Advanced
Basic
Modulation
Deviation
The option is FSK or GFSK and OOK.
FSK
The FSK frequency deviation. The range is from
1 to 100 kHz.
35 kHz
Advanced
The GFSK symbol rate. The user does not need
to specify symbol rate for FSK and OOK
modulation.
Basic
Symbol Rate
2.4 ksps
Advanced
To
s
elect a proper transmitting output power from
-10 dBm to +14 dBm, 1 dB margin is given above
+13 dBm.
Basic
RF Settings
Tx Power
Xtal Load
Data
+13 dBm
15 pF
Advanced
On-chip XOSC load capacitance options: from 10
to 22 p
F
.
T
he step size is 0.33 p
F
.
To
s
elect whether the frequency “Fo + Fdev”
represent data 0 or 1. The options are:
Basic Advanced
Advanced
0: F-low
Representation 0:
F-high 1: F-low, or
0: F-low 1: F-high.
1: F-high
To
c
ontrol PA output power ramp up/down time
PA Ramping
for OOK transmission, options are 0 and 2
n
us (n
0 us
Advanced
from 0 to 10).
Start condition of a transmitting cycle, by Data
Pin Rising/Falling Edge.
Data Pin Rising
Edge
Start by
Stop by
Advanced
Advanced
Transmitting
Settings
Data Pin
Stop condition of a transmitting cycle, by Data
Pin Holding Low for 2 to 90 ms.
Holding Low for
20 ms
5.4 On-line Register Configuration
The on-line register configuration means there is an MCU available in the application to configure the chip registers through
the TWI: CLK and DATA. The value of the registers, which is originally copied from the EEPROM at the chip’s power-up, will
remain its value until part or all of the registers are modified by the host MCU. The register value will be lost after the chip’s
power-down, and re-configuration is necessary when it is powered up again.
5.5 Power Amplifier
A highly efficient single-ended Power Amplifier (PA) is integrated in the CMT2119A to transmit the modulated signal out.
Depending on the application, the user can design a matching network for the PA to exhibit optimum efficiency at the desired
output power for a wide range of antennas, such as loop or monopole antenna. Typical application schematics and the
required BOM are shown in “Chapter 4 Typical Application Schematic”. For the schematic, layout guideline and the other
detailed information please refer to “AN101 CMT211xA Schematic and PCB Layout Design Guideline”.
The output power of the PA can be configured by the user within the range from -10 dBm to +13 dBm in 1 dB step size using
the CMOSTEK USB Programmer and RFPDK.
Rev 0.9 | Page 14/29
CMT2119A
5.6 PA Ramping
When the PA is switched on or off quickly, its changing input impedance momentarily disturbs the VCO output frequency. This
process is called VCO pulling, and it manifests as spectral splatter or spurs in the output spectrum around the desired carrier
frequency. By gradually ramping the PA on and off, PA transient spurs are minimized. The CMT2119A has built-in PA ramping
configurability with options of 0, 1, 2, 4, 8, 16, 32, 64, 128, 256, 512 and 1024 us, as shown in
Figure 13.
These options are
only available when the modulation type is OOK. When the option is set to “0”, the PA output power will ramp up to its
configured value in the shortest possible time. The ramp down time is identical to the ramp up time in the same configuration.
CMOSTEK recommends that the maximum symbol rate should be no higher than 1/2 of the PA ramping “rate”, as shown in the
formula below.
1
t
RAMP
)
SR
Max
≤
0.5 * (
In which the PA ramping “rate” is given by (1/t
RAMP
). In other words, by knowing the maximum symbol rate in the application,
the PA ramping time can be calculated by formula below.
1
t
RAMP
≤
0.5 * (
)
SR
MAX
The user can select one of the values of the t
RAMP
in the available options that meet the above requirement. If somehow the
RAMP
is set to be longer than “0.5 * (1/SR
Max
)”, it will possibly bring additional challenges to the OOK demodulation of the Rx
t
device. For more detail of calculating t
RAMP
, please refer to “AN122 CMT2113/19A Configuration Guideline”.
0 us
1 us
2 us
4 us
8 us
512 us
1024 us
Time
Time
Logic 1
Logic 0
Figure 13. PA Ramping Time
5.7 Crystal Oscillator and RCLK
The CMT2119A uses a 1-pin crystal oscillator circuit with the required crystal load capacitance integrated on-chip
. Figure 14
shows the configuration of the XTAL circuitry and the crystal model. The recommended specification for the crystal is 26 MHz
with ±20 ppm, ESR (Rm) <
60 Ω, load capacitance C
LOAD
ranging from 12 to 20 p
F
. To
s
ave the external load capacitors, a set
of variable load capacitors C
L
is built inside the CMT2119A to support the oscillation of the crystal.
The value of load capacitors is configurable with the CMOSTEK USB Programmer and RFPDK.
T
o
a
chieve the best
performance, the user only needs to input the desired value of the XTAL load capacitance C
LOAD
of the crystal (can be found in
the datasheet of the crystal) to the RFPDK, then finely tune the required XO load capacitance according to the actual XO
frequency. Please refer to “AN103 CMT211xA-221xA One-Way RF Link Development Kits Users Guide” for the method of
choosing the right value of C
L
.
Rev 0.9 | Page 15/29
CMT2119A
CMT211
9
A
Crystal Model
CMT2119A
Cc
XTAL
XTAL
RCLK
26 MHz
0. 3
–
0. 7 Vpp
Rm
C
L
Cm
Lm
C0
C
L
Figure 14. XTAL Circuitry and Crystal Model
Figure 15. RCLK Circuitry
If a 26 MHz RCLK (reference clock) is available in the system, the user can directly use it to drive the CMT2119A by feeding
the clock into the chip via the XTAL pin. This further saves the system cost due to the removal of the crystal. A coupling
capacitor is required if the RCLK is used. The recommended amplitude of the RCLK is 0.3 to 0.7 Vpp on the XTAL pin. Also,
the user should set the internal load capacitor C
L
to its minimum value. Se
e Figure 15
for the RCLK circuitry.
Rev 0.9 | Page 16/29
CMT2119A
6.
Working States and Transmission Control Interface
6.1 Working States
The CMT2119A has following 4 different working states: SLEE
P
,
X
O-STARTU
P
,
T
UNE and TRANSMI
T
.
SLEEP
When the CMT2119A is in the SLEEP state, all the internal blocks are turned off and the current consumption is minimized to
20 nA typically.
XO-STARTUP
After detecting a valid control signal on DATA pin, the CMT2119A goes into the XO-STARTUP state, and the internal XO starts
to work. The valid control signal can be a rising or falling edge on the DATA pin, which can be configured on the RFPDK. The
host MCU has to wait for the t
XTAL
to allow the XO to get stable. The t
XTAL
is to a large degree crystal dependent. A typical value
TUNE
The frequency synthesizer will tune the CMT2119A to the desired frequency in the time t
TUNE
. The PA can be turned on to
transmit the incoming data only after the TUNE state is done, before that the incoming data will not be transmitted. S
ee Figure
TRANSMIT
The CMT2119A starts to modulate and transmit the data coming from the DATA pin. The transmission can be ended in 2
methods: firstly, driving the DATA pin low for t
STOP
time, where the t
STOP
can be configured from 20 to 90 ms on the RFPDK;
secondly, issuing SOFT_RST command over the two-wire interface, this will stop the transmission in 1 ms. See Secti
on 6.2.3
for details of the two-wire interface.
Table 11.Timing in Different Working States
Parameter
Symbol
t
X
T
A
L
Min
Typ
400
370
Max
Unit
us
XTAL Startup Time
[1]
Time to Tune to Desired Frequency
Hold Time After Rising Edge
t
TUNE
us
t
HOLD
10
2
ns
Time to Stop the Transmission
[2]
t
STOP
90
ms
Notes:
[1]. This
parameter is to a large degree crystal dependent.
[2]. Configurable
from 2 to 9 in 1 ms step size and 20 to 90 ms in 10 ms step size.
6.2 Transmission Control Interface
The CMT2119A uses the DATA pin for the host MCU to send in data for modulation and transmission. The DATA pin can be
used as pin for EEPROM programming, data transmission, as well as controlling the transmission. The transmission can be
started by detecting rising or falling edge on the DATA pin, and stopped by driving the DATA pin low for t
STOP
as shown in the
table above. Besides communicating over the DATA pin, the host MCU can also communicate with the device over the
two-wire interface, so that the transmission is more robust, and consumes less current.
Please note that the user is recommended to use the Tx Enabled by DATA pin Rising Edge, which is described in Section
Rev 0.9 | Page 17/29
CMT2119A
6.2.1 Tx
Enabled by D
A
TA Pin Rising Edge
As shown in the figure below, once the CMT2119A detects a rising edge on the DATA pin, it goes into the XO-STARTUP state.
The user has to pull the DATA pin high for at least 10 ns (t
HOLD
) after detecting the rising edge, as well as wait for the sum of
t
X
T
A
L
and t
TUNE
before sending any useful information (data to be transmitted) into the chip on the DATA pin. The logic state of
the DATA pin is “Don’t Care” from the end of t
HOLD
till the end of t
TUNE
. In the TRANSMIT state, PA sends out the input data after
they are modulated. The user has to pull the DATA pin low for t
STOP
in order to end the transmission.
SLEEP
SLEEP
XO-STARTUP TUNE
TRANSMIT
STATE
t
TUNE
t
XTAL
t
STOP
0
Rising Edge
0
Don’t Care
Valid Transmitted Data
RF Signals
1
DATA pin
PA out
t
HOLD
Figure 16. Transmission Enabled by D
A
TA Pin Rising Edge
6.2.2 Tx
Enabled by D
A
TA Pin Falling Edge
As shown in the figure below, once the CMT2119A detects a falling edge on the DATA pin, it goes into XO-STARTUP state and
the XO starts to work. During the XO-STARTUP state, the DATA pin needs to be pulled low. After the XO is settled, the
CMT2119A goes to the TUNE state. The logic state of the DATA pin is “Don’t Care” during the TUNE state. In the TRANSMIT
state, PA sends out the input data after they are modulated. The user has to pull the DATA pin low for t
STOP
in order to end the
transmission. Before starting the next transmit cycle, the user has to pull the DATA pin back to high.
TRANSMIT
SLEEP
SLEEP XO-STARTUP
TUNE
STATE
t
TUNE
t
STOP
t
XTAL
Falling Edge
Don’t Care
1
0
0
1
Valid Transmitted Data
RF Signals
DATA pin
PA out
Figure 17. Transmission Enabled by D
A
TA Pin Falling Edge
6.2.3 Two-wire
Interface
For power-saving and reliable transmission purposes, the CMT2119A is recommended to communicate with the host MCU
over a two-wire interface (TWI): DATA and CLK. The TWI is designed to operate at a maximum of 1 MHz. The timing
requirement and data transmission control through the TWI are shown in this section.
Rev 0.9 | Page 18/29
CMT2119A
Table 12. TWI Requirements
Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Digital Input Level High
Digital Input Level Low
CLK Frequency
V
IH
V
IL
0.8
V
DD
V
DD
kHz
ns
0.2
F
CLK
t
CH
10
1,000
CLK High Time
500
500
CLK Low Time
t
CL
ns
CLK delay time for the first falling edge of the
The data delay time from the last CLK rising
edge of the TWI command to the time DATA
return to default state
CLK Delay Time
t
CD
20
15,000
15,000
ns
DATA Delay Time
t
DD
ns
DATA Setup Time
DATA Hold Time
t
DS
t
DH
From DATA change to CLK falling edge
From CLK falling edge to DATA change
20
ns
ns
200
CLK
t
CH
t
CL
t
DS DH
t
DATA
Figure 18. Two-wire Interface Timing Diagram
Once the device is powered up, TWI_RST and SOFT_RST should be issued to make sure the device works in SLEEP state
robustly. On every transmission, TWI_RST and TWI_OFF should be issued before the transmission to make sure the TWI
circuit functions correctly. TWI_RST and SOFT_RST should be issued again after the transmission for the device going back to
SLEEP state reliably till the next transmission. The operation flow with TWI is shown as the figure below.
Reset TWI
One Transmission Cycle
One Transmission Cycle
(1) – TWI_RST
(2) – SOFT_RST
(1) – TWI_RST
(2) – TWI_OFF
(1) – TWI_RST
(2) – SOFT_RST
(1) – TWI_RST
(2) – TWI_OFF
(1) – TWI_RST
(2) – SOFT_RST
TRANSMISSION
TRANSMISSION
Figure 19. CMT2119A Operation Flow with TWI
Table 13. TWI Commands Descriptions
Descriptions
Command
Implemented by pulling the DATA pin low for 32 clock cycles and clocking in 0x8D00, 48 clock cycles in total.
It only resets the TWI circuit to make sure it functions correctly. The DATA pin cannot detect the
Rising/Falling edge to trigger transmission after this command, until the TWI_OFF command is issued.
TWI_RST
Notes:
1.
2.
Please ensure the DATA pin is firmly pulled low during the first 32 clock cycles.
When the device is configured as Transmission Enabled by DATA Pin Falling Edge, in order to issue
the TWI_RST command correctly, the first falling edge of the CLK should be sent t
CD
after the DATA
falling edge, which should be longer than the minimum DATA setup time 20 ns, and shorter than 15 us,
Rev 0.9 | Page 19/29
CMT2119A
Command
Descriptions
3.
When the device is configured as Transmission Enabled by DATA Pin Rising Edge, the default state of
Implemented by clocking in 0x8D02, 16 clock cycles in total.
TWI_OFF
It turns off the TWI circuit, and the DATA pin is able to detect the Rising/Falling edge to trigger transmission
Implemented by clocking in 0xBD01, 16 clock cycles in total.
It resets all the other circuits of the chip except the TWI circuit. This command will trigger internal calibration
for getting the optimal device performance. After issuing the SOFT_RST command, the host MCU should
wait 1 ms before sending in any new command. After that, the device goes to SLEEP state. The command is
SOFT_RST
32 clock cycles
16 clock cycles
CLK
…
…
t
CD
t
DD
DATA
1
0
0x8D00
1
Figure 20. TWI_RST Command When Transmission Enabled by D
A
TA Pin Falling Edge
32 clock cycles
16 clock cycles
CLK
…
…
0
0x8D00
0
DATA
Figure 21. TWI_RST Command When Transmission Enabled by D
A
TA Pin Rising Edge
16 clock cycles
16 clock cycles
CLK
…
CLK
…
t
DD
t
DD
Default
State
Default
State
DATA
0xBD01 (SOFT_RST)
DATA
0x8D02 (TWI_OFF)
Figure 22. TWI_OFF Command
Figure 23. SOFT_RST Command
The DATA is generated by the host MCU on the rising edge of CLK, and is sampled by the device on the falling edge. The CLK
should be pulled up by the host MCU during the TRANSMISSION shown i
n Figure 19.
The TRANSMISSION process should
refer t
o Figure 16
or
Figure 17
for its timing requirement, depending on the “Start By” setting configured on the RFPDK.
The device will go to SLEEP state by driving the DATA low for t
STOP
, or issuing SOFT_RST command. A helpful practice for the
device to go to SLEEP is to issue TWI_RST and SOFT_RST commands right after the useful data is transmitted, instead of
waiting the t
STOP
, this can save power significantly.
Rev 0.9 | Page 20/29
CMT2119A
7. On-Line
Register Configuration Flow
Besides off-line EEPROM programming to tailor the chip features, on-line register configuration through the two-wire interface
can do the work in another way, which is mentioned in Section 5.4. This chapter gives more details on accessing chip registers
with TWI.
7.1 Accessing Registers with TWI
The TWI includes an input port CLK and a bi-directional port DATA. A complete Write/Read (W/R) process has 16 clock cycles.
For the first 8 clock cycles, the DATA is used as input port for writing register address; and for the last 8 clock cycles, the DATA
is used as input port during write process, and output port during read process. The timing chart for the TWI W/R is shown as
the figure below. Please note that the TWI_RST command is a special command which does not apply to the guidelines
CLK
t
DD
Default
State
X
1
W/R
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
DATA
Figure 24. TWI W/R Timing Chart (Except for TWI_RST Command)
Notes:
1.
2.
3.
At the end of each command, the DATA should return to its default state after the last CLK rising edge within the time t
DD
The command always start with “1”, the first 8 clock cycle includes the W/R control and address bits A[5:0]. It is a Read
command when W/R is 1, and Write command when W/R is 0. The range of the address bits is from 0x00 to 0x3F.
In a Write command, D[7:0] is the data to be written into the register. In a Read command, D[7:0] is the data to be read
from the register.
.
4.
5.
The DATA pin is a bi-directional port, and it will be switched to output port in the last 8 clock cycle of a Read command. At
this time, the host MCU should switch the corresponding port which is connected to the DATA pin to input port at the
coming CLK rising edge, shown as dash line in the middle of
Figure 24, s
o that there is no voltage conflict between the
two ports and the read out function is correctly behaved.
6.
To simplify the expression, this datasheet is using the TWI_WRREG and TWI_RDREG to represent the write and read
command to specified registers, as shown in the table below.
Table 14.TWI_WRREG and TWI_RDREG
Command
Description
TWI write command. TWI_WRREG(XX, YY) means clocking in 16b’10xx xxxx yyyy yyyy, which xx xxxx
is the register address to be written, ranging from 0x00 to 0x3F; yyyy yyyy is the register content to be
written ranging from 0x00 to 0xFF.
TWI_WRREG
For example, TWI_WRREG(0x12, 0xAA) means clocking in 0x92AA.
TWI read command, TWI_RDREG(XX, ZZ) means clocking in 8b’11xx xxxx and read out zzzz zzzz,
which xx xxxx is the register address to be written, ranging from 0x00 to 0x3F; zzzz zzzz is the read out
value from the register, ranging from 0x00 to 0xFF
TWI_RDREG
For example, TWI_RDREG(0x2A, DAT), means clocking in 0xEA, and read out DAT which is an 8-bit
value.
Rev 0.9 | Page 21/29
CMT2119A
7.
Specific commands TWI_RST, TWI_OFF and SOFT_RST are also used in the on-line register configuration, refer to
Table 13
for the definition of the 3 commands.
7.2 Configuration Flow
The user should follow below flow chart for the on-line register configuration.
Step-1
Step-2
Step-3
Step-6
1
4
7
2
5
8
3
6
SOFT_RST
(wait 1 ms before moving to Step-3)
TWI_RST
TWI_WRREG(0x02, 0x78)
Step-4
Step-5
(1) – TWI_WRREG(0x2F, 0x80)
(2) – TWI_WRREG(0x35, 0xCA)
(3) – TWI_WRREG(0x36, 0xEB)
(4) – TWI_WRREG(0x37, 0x37)
(5) – TWI_WRREG(0x38, 0x82)
(1) – TWI_WRREG(0x12, 0x10)
(2) – TWI_WRREG(0x12, 0x00)
(3) – TWI_WRREG(0x24, 0x07)
(4) – TWI_WRREG(0x1D, 0x20)
(1) – TWI_WRREG(0x18, Addr)
(2) – TWI_WRREG(0x19, Low_data)
(3) – TWI_WRREG(0x1A, High_data)
(4) – TWI_WRREG(0x25, 0x01)
3
6
Step-7
Step-8
Step-9
TWI_OFF
TRANSMISSION
TWI_WRREG( 0x02, 0x7F)
Figure 25. On-line Register Configuration Flow
Notes:
1.
2.
In step-2, the host MCU issues the SOFT_RST command and needs to wait 1 ms before moving to step-3.
The feature registers are 16-bit wide, which address is indicated as Addr in step-6. The host MCU needs to first write the
Addr to register 0x18. After that, the host MCU divides the feature register content into two 8-bit parts: Low_data and
High_data, then write them into two temporary registers, which addresses are 0x19 and 0x1A, and finally overwrite the
target 16-bit register by issuing TWI_WRREG(0x25, 0x1) to complete the feature register writing, as shown in step-6.
Repeat step-6 if multiple feature registers are need to configured.
For example, if the user wants to write 0xC3F6 to feature register which address is 0x02, the user should issue the
commands shown in step-6, and listed as below.
a)
b)
c)
d)
TWI_WRREG(0x18, 0x02);
TWI_WRREG(0x19, 0xF6);
TWI_WRREG(0x1A, 0xC3);
TWI_WRREG(0x25, 0x01);
// Write the Addr 0x02 to register 0x18
// Write the Low_data 0xF6 to register 0x19
// Write the High_data 0xC3 to register 0x1A
// Trigger the overwriting to the feature register, the writing process completes
3.
As a specific feature could be related to several registers, in order to change the feature correctly, the user is
recommended to find out the corresponding registers by Export function on the RFPDK, as shown i
n Figure 26
. For
more RFPDK details, refer to “AN103 CMT211xA-221xA One-Way RF Link Development Kits Users Guide”. An example
of changing the frequency from 433.92 MHz to 868 MHz is listed below.
a)
Configure the device to work in 433.92 MHz, use the Export function on the RFPDK to generate the configuration
file named as 433.92MHz.exp.
b)
c)
Configure the device to work in 868 MHz, generate the configuration file named as 868MHz.exp in the same way.
Compare the 868MHz.exp file with the 433.92MHz.exp file and find out the registers being changed, as shown in
Figure 27.
Please note that the address of the registers starts from 0x00 and ends at 0x15 (21 registers in total).
d)
Rev 0.9 | Page 22/29
CMT2119A
Figure 26. Export Button on the RFPDK
Figure 27. Examples of Changing Frequency
Rev 0.9 | Page 23/29
CMT2119A
8. Ordering
Information
Table 15. CMT2119A Ordering Information
Package
Type
Package
Option
Operating
Condition
1.8 to 3.6 V,
-40 to 85
℃
MOQ /
Part Number
Descriptions
Multiple
240-960 MHz (G)FSK/OOK
Transmitter
CMT2119A-ESR
[1]
SOT23-6
Tape & Reel
3,000
Notes:
[1]. “E”
stands for extended industrial product grade, which supports the temperature range from -40 to +85
℃
.
“S” stands for the package type of SOT23-6 for this product.
“R” stands for the tape and reel package option, the minimum order quantity (MOQ) for this option is 3,000 pieces.
Rev 0.9 | Page 24/29
CMT2119A
9. Package
Outline
The 6-pin SOT23-6 illustrates the package details for the CMT2119A. The table below lists the values for the dimensions
shown in the illustration.
e1
e
0.25
L
E1
E
c
b
θ
D
A
A2
A3
A1
Figure 28. 6-Pin SOT23-6
Table 16. 6-Pin SOT23-6 Package Dimensions
Size (millimeters)
Symbol
Min
—
Typ
—
Max
1.35
0.15
1.20
0.75
0.48
0.20
3.12
3.00
1.80
A
A1
A2
A3
b
0.04
1.00
0.55
0.38
0.08
2.72
2.60
1.40
—
1.10
0.65
—
C
—
D
2.92
2.80
1.60
0.95 BSC
1.90 BSC
—
E
E1
e
e1
L
0.30
0
0.60
8°
θ
—
Rev 0.9 | Page 25/29
CMT2119A
10
.
T
op Marking
10.1
CMT2119A Top Marking
6
5
4
9 A
① ② ③
1
2
3
Figure 29. CMT2119A Top Marking
Table 17. CMT2119A Top Marking Explanation
Top Mark
9A
①②③
Mark Method
Font Size
Laser
0.6 mm, right-justified
9, represents CMT2119
A: represents revision A
1
st
letter
2
nd
letter
3
rd
– 5
th
letter
①②③
: Internal reference for data code tracking, assigned by the assembly house
Rev 0.9 | Page 26/29
CMT2119A
11
.
O
ther Documentations
Table 18. Other Documentations for CMT2119A
Brief
Name
Descriptions
Details of CMT211xA PCB schematic and layout design
rules, RF matching network and other application layout
design related issues.
CMT211xA Schematic and PCB Layout
Design Guideline
AN101
Details of configuring CMT2113/19A features on the RFPDK,
and the on-line configuration guideline for CMT2119A.
AN122
AN103
CMT2113/19A Configuration Guideline
User’s Guides for CMT211xA/CMT221xA Development Kits,
including Evaluation Board and Evaluation Module,
CMOSTEK USB Programmer and RFPDK.
CMT211xA-221xA One-Way RF Link
Development Kits Users Guide
Rev 0.9 | Page 27/29
CMT2119A
12
.
D
ocument Change List
Table 19. Document Change List
Rev. No.
0.6
Chapter
Description of Changes
Date
All
6, 7
6
Initial Released
2014-12-05
2015-01-16
2015-01-23
0.8
Adding Chapter 6 and Chapter 7
0.9
Rev 0.9 | Page 28/29
CMT2119A
13
.
C
ontact Information
Hope Microelectronics Co., Ltd
Address: 2/
F
,
Building3,Pingshan Private Enterprise science and
T
e
chnology Park,Xili
T
o
wn,Nanshan District,Shenzhen,China
T
e
l: +86-755-82973805
Fax: +86-755-82973550
Copyright. CMOSTEK Microelectronics Co., Ltd. All rights are reserved.
The information furnished by CMOSTEK is believed to be accurate and reliable. However, no responsibility is assumed for
inaccuracies and specifications within this document are subject to change without notice. The material contained herein is
the exclusive property of CMOSTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior
written permission of CMOSTEK. CMOSTEK products are not authorized for use as critical components in life support
devices or systems without express written approval of CMOSTEK. The CMOSTEK logo is a registered trademark of
CMOSTEK Microelectronics Co., Ltd. All other names are the property of their respective owners.
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