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BGT24AR2
Silicon Germanium 24 GHz Twin IQ Receiver MMIC
Data Sheet
Revision 3.0, 2013-06-26
RF & Protection Devices
Edition 2013-06-26
Published by
Infineon Technologies AG
81726 Munich, Germany
©
2013 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon
T
e
chnologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further informatio
n on technology, delivery term
s and conditions and prices, please contact the nearest
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon
T
e
chnologies Office.
Infineon
T
e
chnologies components may be used in life-support devices or systems only with the express written
approval of Infineon
T
e
chnologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
BGT24AR2
Silicon Germanium 24 GHz Twin IQ Receiver MMIC
BGT24AR2 Silicon Germanium 24 GHz Twin IQ Receiver MMIC
Revision History: 2013-06-26, Revision 3.0
Previous Revision: 2011-08-01, Revision 2.3
Page
Subjects (major changes since last revision)
update parameter
all
Trademarks of Infineon Technologies AG
AURIX™, BlueMoon™, C166™, CanPAK™, CIPOS™, CIPURSE™, COMNEON™, EconoPACK™, CoolMOS™,
CoolSET™, CORECONTROL™, CROSSAVE™, DAVE™, EasyPIM™, EconoBRIDGE™, EconoDUAL™,
EconoPIM™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™, ISOFACE™, IsoPACK™,
MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OmniTune™, OptiMOS™, ORIGA™, PRIMARION™,
PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™, ReverSave™, SatRIC™, SIEGET™,
SINDRION™, SIPMOS™, SMARTi™, SmartLEWIS™, SOLID
FLASH™, TEMPFET™, thinQ!™,
TRENCHSTOP™, TriCore™, X-GOLD™, X-PMU™, XMM™, XPOSYS™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™,
PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR
development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™,
FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG.
FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of
Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data
Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of
MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics
Corporation. Mifare™ of NXP. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™
of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc.,
OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc.
RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc.
SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden
Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA.
UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™
of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of
Diodes Zetex Limited.
Last Trademarks Update 2010-10-26
Data Sheet
3
Revision 3.0, 2013-06-26
BGT24AR2
Silicon Germanium 24 GHz Twin IQ Receiver MMIC
Table of Contents
Table of Contents
Table of Contents
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
List of Figures
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
List of Tables
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
Features
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
1
2
Electrical Characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
Absolute Maximum Ratings
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
Thermal Resistance
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
ESD Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
Measured RF Characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
RX Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
2.1
2.2
2.3
2.4
2.4.1
2.4.2
2.5
3
Application Circuit and Block Diagram
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
Application Circuit Schematic
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
Pin Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
SPI .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
Application Board
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
Equivalent Circuit Diagram of MMIC Interfaces
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
3.1
3.2
3.3
3.4
3.5
4
Physical Characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
Package Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
Reflow Profile
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
Package Dimensions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
4.1
4.2
4.3
Data Sheet
4
Revision 3.0, 2013-06-26
BGT24AR2
Silicon Germanium 24 GHz Twin IQ Receiver MMIC
List of Figures
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
BGT24AR2 Block Diagra
m
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
Application Circuit with Chip Outline (Top View)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
Timing Diagram of the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
Cross-Section View of Application Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
Detail of Compensation Structure (valid for appl. board mat. Ro4350B, 0.254mm acc. to Fig. 4) .
18
Application Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
Equivalent Circuit Diagram of MMIC Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
Recommended Footprint and Stencil Layout for the VQFN32-9 Package . . . . . . . . . . . . . . . . . . .
21
Reflow Profile for BGT24AR2 (VQFN32-9)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
Figure 10
Package Outline (Top, Side and Bottom View)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
Figure 11
Marking Layout VQFN32-
9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
3
Figure 12
Tape of VQFN32-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
Data Sheet
5
Revision 3.0, 2013-06-26
BGT24AR2
Silicon Germanium 24 GHz Twin IQ Receiver MMIC
List of Tables
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
ESD Integrity
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
Typical Characteristics
T
A
= -40 .. 125 °C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
Typical Characteristics
T
A
= -40 .. 125 °C, f = 24.0 .. 24.25 GHz
. . . . . . . . . . . . . . . . . . . . . . . . .
11
Typical Characteristics Temperature Sensor
T
A
= -40 .. 125 °C
. . . . . . . . . . . . . . . . . . . . . . . . .
12
Bill of Materials
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
Pin Definition and Function
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
SPI Data Bit Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
SPI Timing and Logic Levels
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
Data Sheet
6
Revision 3.0, 2013-06-26
Silicon Germanium 24 GHz Twin IQ
Receiver MMIC
BGT24AR2
1
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Gilbert based dual homodyne quadrature receiver
Qualified according AEC Q100
Single ended RF terminals
Low noise figure: NF
SSB
: 12 dB
High conversion gain: 26 dB
High 1 dB input compression point: -12 dBm
Low LO input power
Single supply voltage of 3.3 V
Integrated temperature sensor for monitoring purposes
Low power consumption 300 mW
200 GHz bipolar SiGe:C technology b7hf200
Fully ESD protected device
VQFN-32-9 leadless plastic package incl. LTI-feature
Pb-free (RoHS compliant) package
Description
The BGT24AR2 is a Silicon Germanium MMIC accommodating two separate homodyne quadrature
downconversion chains, operating in the 24 GHz ISM band from 24.00 to 24.25 GHz. LO buffer amplifiers are
included to relax LO drive requirements and individual LNAs provide low noise figures. RC polyphase filters (PPF)
are used for LO quadrature phase generation. The circuit is manufactured in a 0.18µm SiGe:C technology offering
a cutoff frequency of 200 GHz. The MMIC is packaged in a 32 pin leadless RoHs compliant VQFN package.
Product Name
Package
Chip
Marking
BGT24AR2
VQFN32-9
T1525
BGT24AR2
Data Sheet
7
Revision 3.0, 2013-06-26
BGT24AR2
Silicon Germanium 24 GHz Twin IQ Receiver MMIC
Features
IFQ 2
90°
IFQX 2
LO
Bu
f
f
e
r
RF
I
N
2
PPF *
LNA
0°
TE MP
IFI 2
IFIX 2
T
E
M
P
SENS
O
R
Power
S plitter
LO
I
N
SPI
SI CS
CLK
IFQ1
90°
IFQX 1
3
LO
Bu
f
f
e
r
RF
I
N 1
PPF *
LNA
0°
IFI 1
IFIX 1
* Poly Phase Filter
BGT24AR2_Chip_BID.vsd
Figure 1
BGT24AR2 Block Diagram
Data Sheet
8
Revision 3.0, 2013-06-26
BGT24AR2
Silicon Germanium 24 GHz Twin IQ Receiver MMIC
Electrical Characteristics
2
Electrical Characteristics
2.1
Absolute Maximum Ratings
T
A
= -40 °C to 125 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise
specified)
1)
Table 1
Absolute Maximum Ratings
Symbol
Parameter
Values
Unit
Note / Test Condition
Min.
-0.3
0
Typ.
Max.
3.6
0
Supply voltage
V
CC
–
–
V
V
–
DC voltage at Pins RFIN1,
RFIN2, LOIN
VDC
RF
MMIC provides short circuit
to GND for all RF Pins
DC voltage at Pins IFI1/2,
IFIX1/2, IFQ1/2, IFQX1/2
VDC
IF
I
IF
0
–
–
Vcc
3.5
V
–
DC current into Pins IFI1/2,
IFIX1/2, IFQ1/2, IFQX1/2
-8.5
mA
max. values indicate
current due to short circuit
to GND and Vcc
respectively
DC voltage at Pin TEMP
DC current into Pin TEMP
VDC
TEMP
I
TEMP
-0.3
-1
–
–
3.6
1.5
V
–
mA
max. values indicate
current due to short circuit
to GND and Vcc
respectively
DC voltage at SPI input Pins
SI, CLK, CS
VDC
SPIIN
-0.3
–
–
–
–
3.6
3
V
–
–
–
DC current into SPI input Pins
I
SPIIN
SI, CLK, CS
mA
dBm
RF input power into Pins
RFIN1, RFIN2
P
RF
–
0
LO input power into Pin LOIN
P
LO
–
–
–
–
–
10
dBm
mW
°C
–
Total power dissipation
Junction temperature
P
DISS
–
500
150
125
With BIST deactivated
–
T
J
-40
-40
Ambient temperature range
T
A
°C
T
A
= Package soldering
point
Storage temperature range
T
STG
-40
–
150
°C
–
Attention: Stresses exceeding the max. values listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. Maximum ratings are absolute ratings; exceeding only one of these values may
cause irreversible damage to the integrated circuit.
1) Not
subject to production test, specified by design
Data Sheet
9
Revision 3.0, 2013-06-26
BGT24AR2
Silicon Germanium 24 GHz Twin IQ Receiver MMIC
Electrical Characteristics
2.2
Thermal Resistance
Table 2
Thermal Resistance
Parameter
Symbol
Values
Typ.
–
Unit
Note / Test Condition
Min.
Max.
Junction – soldering point
1)
R
thJS
–
40
K/W
–
1) For
calculation of R
thJA
please refer to application note thermal resistance
2.3
ESD Integrity
Table 3
ESD Integrity
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
1
ESD robustness, HBM
1)
ESD robustness, CDM
2)
V
ESD-HBM
-1
–
–
kV
V
All pins
All pins
V
ESD-CDM
-500
500
1) According
to ANSI/ESDA/JEDEC JS-001 (R = 1.5k
Ω
, C = 100pF) for Electrostatic Discharge Sensitivity Testing, Human
Body Model (HBM)-Component Level
2) According
to JEDEC JESD22-C101 Field-Induced Charged Device Model (CDM), Test Method for Electrostatic-Discharge-
Withstand Thresholds of Microelectronic Components
Data Sheet
10
Revision 3.0, 2013-06-26
BGT24AR2
Silicon Germanium 24 GHz Twin IQ Receiver MMIC
Electrical Characteristics
2.4
Measured RF Characteristics
2.4.1
Power Supply
Table 4
Typical Characteristics
T
A
= -40 .. 125 °C
Symbol
Min.
Values
Typ.
Unit
Note /
Test Condition
Parameter
Max.
3.465
120
V
CC
I
CC
3.135
70
3.3
90
V
–
–
Supply voltage
Supply current
mA
2.4.2
RX Section
Table 5
Typical Characteristics
T
A
= -40 .. 125 °C, f = 24.0 .. 24.25 GHz
1)
Symbol
Values
Typ.
Unit
Note /
Test Condition
Parameter
Min.
Max.
24.0
–
24.25
GHz
–
RFIN and LOIN frequency
range
f
RFIN,
f
LOIN
–
–
14.0-j4.8
14.9-j6.3
27.3+j9.9
–
Ω
Typical value at
24.125GHz and
VSWR
≤
2:1
RFIN and LOIN port
impedance
2)
Z
RFIN1
Z
RFIN2
Z
LOIN
–
2:1
–
At source port of off
chip compensation
network as pro-
posed
RFIN and LOIN VSWR
VSWR
RFIN
VSWR
LOIN
,
f
IF
f
c
0
–
10
MHz
kHz
Ω
–
–
–
IF frequeny range
–
10
1000
–
20
IF 1/f corner frequency
IF port impedance
850
–
1150
-30
Z
IF
L
LOIN=>RFIN
I
RFIN1-RFIN2
P
LOIN
dBm
Parameter based on
IFX eval board
design
Leakage LOIN to RFIN
30
–
–
dB
Parameter based on
IFX eval board
design
Isolation RFIN1 to RFIN2
-6
19
3
–
3
dBm
dB
–
LOIN input power
Voltage conversion gain
3)
LNA gain reduction
SSB Noise figure
G
C
R
–
LOAD,IF
>
10k
Ω
26
5
31
8
dB
Δ
G
CLG
NF
SSB
–
12
20
dB
Single sideband at
100kHz
IP
-1dB
IIP3
ε
P
-17
-8
-12
-4
–
–
dBm
dBm
deg
–
–
–
1dB input compression
–
3‘rd order input intercept point
Quadrature phase imbalance
-10
10
Data Sheet
11
Revision 3.0, 2013-06-26
BGT24AR2
Silicon Germanium 24 GHz Twin IQ Receiver MMIC
Electrical Characteristics
Table 5
Typical Characteristics
T
A
= -40 .. 125 °C, f = 24.0 .. 24.25 GHz
1)
(cont’d)
Symbol
Values
Typ.
Unit
Note /
Test Condition
Parameter
Min.
Max.
Δ
ε
p
-8
–
8
deg
–
Quadrat. phase imbalance over
temperature and aging of both
receivers
ε
A
-1
–
–
1
dB
dB
–
–
Quadrat. amplitude imbalance
Δ
ε
A
-0.5
0.5
Quadrat. amplitude imbalance
over temperature and aging of
both receivers
1) Performance
based on Application Circuit Figure 2
on Page 13, Cross Section of Application Board, Compensation
Structures and Application Board Layout Figure 4
on Page 18ff and Footprint Figure 8
on Page 21
2) Guaranteed
by device design
3) Lowest
gain at high temperature, highest gain at low temperature
2.5
Temperature Sensor
Monitoring of the chip temperature is provided by the on-chip temperature sensor which delivers temperature-
proportional voltage to the TEMP output.
Table 6
Typical Characteristics Temperature Sensor
T
A
= -40 .. 125 °C
1)
Parameter
Symbol
Values
Typ.
–
Unit
Note / Test Condition
Min.
-40
–
Max.
125
–
Temperature range
Output temperature voltage
Sensitivity
T
TSENS
°C
V
–
V
OUT,TEMP
S
TSENS
1.50
4.5
@ 25°C
–
–
mV/K
K
–
–
Overall accuracy error
E
rr
TSENS
–
–
±
15
1) all
voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Data Sheet
12
Revision 3.0, 2013-06-26
BGT24AR2
Silicon Germanium 24 GHz Twin IQ Receiver MMIC
Application Circuit and Block Diagram
3
Application Circuit and Block Diagram
3.1
Application Circuit Schematic
VCC
2)
C3
1μF
26
25
24
23
22
21
20
19
18
17
n.c.
5)
TEMP
27
28
29
30
31
16
15
14
13
12
IFIX1
IFI1
IFIX2
IFI2
IFQ1
IFQ2
IFQX1
IFQX2
VEE
32
11
VEE
7
8
9
3
4
6
1
2
5
10
C2
3)
470μF
C1
1μF
VCC
2)
1) Connect test pin 24 and 25
2) Galvanic connection of VCC pins on silicon (pin 5, 6 and 17)
3) Optional value: according to quality of supply voltage (C2)
4) Recommendation: Connect pin 1 and 10 to VEE for better RF performance
5) Floating pin 16 and 26 – do not connect with any other pin
BGT24AR2_Appl_BID.vsd
Figure 2
Application Circuit with Chip Outline (Top View)
Data Sheet
13
Revision 3.0, 2013-06-26
BGT24AR2
Silicon Germanium 24 GHz Twin IQ Receiver MMIC
Application Circuit and Block Diagram
Table 7
Bill of Materials
Part Number
Part Type
Manufacturer
Size
Comment
C1 … C3
Chip capacitor
Various
Various
–
Data Sheet
14
Revision 3.0, 2013-06-26
BGT24AR2
Silicon Germanium 24 GHz Twin IQ Receiver MMIC
Application Circuit and Block Diagram
3.2
Pin Description
Table 8
Pin No.
1
Pin Definition and Function
Name
n.c.
Function
Not connected
2
VEE
Ground
3
RFIN1
VEE
RF input downconverter 1
4
Ground
5
VCC
VCC
VEE
Supply voltage
6
Supply voltage
7
Ground
8
RFIN2
VEE
RF input downconverter 2
Ground
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
n.c.
Not connected
VEE
Ground
IFQX2
IFQ2
IFI2
Complementary quadrature phase IF output downconverter 2
Quadrature phase IF output downconverter 2
In phase IF output downconverter 2
Complementary in phase IF output downconverter 2
Do not connect; DC coupled pin
Supply voltage
IFIX2
n.c.
VCC
CS
Chip select input SPI (inverted)
Clock input SPI
CLK
SI
Data input SPI
VEE
Ground
LOIN
VEE
LO input
Ground
TEST PIN
TEST PIN
n.c.
Test pin; DC coupled pin
Test pin; DC coupled pin
Do not connect; DC coupled pin
Temperature sensor output
Complementary in phase IF output downconverter 1
In phase IF output downconverter 1
Quadrature phase IF output downconverter 1
Complementary quadratrue phase IF output downconverter 1
Ground
TEMP
IFIX1
IFI1
IFQ1
IFQX1
VEE
Data Sheet
15
Revision 3.0, 2013-06-26
BGT24AR2
Silicon Germanium 24 GHz Twin IQ Receiver MMIC
Application Circuit and Block Diagram
3.3
SPI
1.) Three signals control the serial peripheral interface of the BGT24AR2:
SI (Data); CLK (Clock); CS (Chip select)
2.) The data bits SI (MSB first) are read in the shift register with falling edge of the CLK signal.
Please make sure, that the data is present at least 10 ns before and at least 10 ns after the falling edge of the
clock signal.
3.) The CLK and CS signals are combined internally.
At least 20 ns before first rising edge of the first CLK signal CS needs to be in “low” state.
While the Data is read, CS has to remain in “low” state.
4.) When Data read in is finished, the shift register content will be written in the latch at the rising edge of the CS
signal. The
time between the last falling edge of the CLK signal and the rising edge of the CS must be at least 20
ns.
Table 9
Data Bit
15 (MSB)
14
SPI Data Bit Description
Name
GS
Description (Logic High)
LNA Gain reduction
Not used
Power ON State
low
low
–
13
Test Bit
Test bit, must be low otherwise
low
malfunction
12
11
10
9
Test Bit
Test Bit
Test Bit
Test Bit
Test Bit
Test Bit
Test Bit
Test Bit
Test Bit
Test Bit
Test Bit
Test bit, must be low otherwise
low
malfunction
Test bit, must be low otherwise
low
malfunction
Test bit, must be high
otherwise malfunction
high
high
high
Test bit, must be high
otherwise malfunction
8
Test bit, must be high
otherwise malfunction
7
Test bit, must be low otherwise
low
malfunction
6
Test bit, must be low otherwise
low
malfunction
5
Test bit, must be low otherwise
low
malfunction
4
Test bit, must be high
otherwise malfunction
high
3
Test bit, must be low otherwise
low
malfunction
2
Test bit, must be high
otherwise malfunction
high
Data Sheet
16
Revision 3.0, 2013-06-26
BGT24AR2
Silicon Germanium 24 GHz Twin IQ Receiver MMIC
Application Circuit and Block Diagram
Table 9
Data Bit
1
SPI Data Bit Description
(cont’d)
Name
Description (Logic High)
Power ON State
Test Bit
Test bit, must be low otherwise
low
malfunction
0
Test Bit
Test bit, must be low otherwise
low
malfunction
BGT24AR2_SPI.vsd
Figure 3
Timing Diagram of the SPI
SPI Timing and Logic Levels
Table 10
Parameter
Symbol
Values
Typ.
Unit
Min.
0
Max.
50
–
Serial clock frequency
Serial clock high time
Serial clock low time
Chip select lead time
Chip select lag time
f
SCLK
–
–
–
–
–
–
–
–
–
–
–
MHz
ns
ns
ns
ns
ns
ns
V
f
SCLK(H)
t
SCLK(L)
t
CS(lead)
t
CS(lag)
t
SI(su)
t
SI(h)
10
10
20
20
10
10
0
–
–
–
Data setup time
–
Data hold time
–
Low level (SI, CLK, CS)
High level (SI, CLK, CS)
Input capacitance (SI, CLK, CS)
Input current (SI, CLK, CS)
V
IN(L)
V
IN(H)
C
IN
0.8
V
CC
2
2.0
–
V
pF
µA
I
IN
-150
150
Data Sheet
17
Revision 3.0, 2013-06-26
BGT24AR2
Silicon Germanium 24 GHz Twin IQ Receiver MMIC
Application Circuit and Block Diagram
3.4
Application Board
Blind-Vias
Vias
Ro4350B, 0.254mm
Copper
35um
FR4, 0.5mm
FR4, 0.25mm
BGT24AR2_Cross_Section_View.vsd
Figure 4
Cross-Section View of Application Board
Single-Ended RFIN
Single-Ended LOIN
0.50
0.50
1.00
0.65
0.30
0.30
All specified values in [mm]
BGT24AR2_VQFN32-9-CS.vsd
Figure 5
Detail of Compensation Structure
(valid for appl. board mat. Ro4350B, 0.254mm acc. to Fig. 4)
Data Sheet
18
Revision 3.0, 2013-06-26
BGT24AR2
Silicon Germanium 24 GHz Twin IQ Receiver MMIC
Application Circuit and Block Diagram
Mid1 and Bottom layer (top
Mid2 layer (top view)
view)
Top layer (top view)
BGT24AR2_App_Board_Layout.vsd
Figure 6
Application Board Layout
Note
:
I
n order to achieve the same performance as given in this datasheet please follow the suggested PCB-
layout. The compensation structure is critical for RF performance. Via holes as recommended on one of next
pages (not shown above).
Data Sheet
19
Revision 3.0, 2013-06-26
BGT24AR2
Silicon Germanium 24 GHz Twin IQ Receiver MMIC
Application Circuit and Block Diagram
3.5
Equivalent Circuit Diagram of MMIC Interfaces
Pin 12, 13, 14, 15,
28, 29, 30, 31
Pin 3, 8, 22
VCC
400Ω
RFIN1, RFIN2,
LOIN
IFx
VEE
VEE
Pin 27
Pin 18, 19, 20
VCC
VCC
TEMP
40Ω
54kΩ
CS, CLK, SI
1500Ω
VEE
VEE
Tolerance of all resistors +/- 20%
BGT24AR2_ESB.vsd
Figure 7
Equivalent Circuit Diagram of MMIC Interfaces
Data Sheet
20
Revision 3.0, 2013-06-26
BGT24AR2
Silicon Germanium 24 GHz Twin IQ Receiver MMIC
Physical Characteristics
4
Physical Characteristics
4.1
Package Footprint
Copper
Solder Mask
Vias
4.3
3.9
3.2
Pastefree
Area
1.0
0.7
0.3
0.5
0.3
All specified values in [mm]
BGT24AR2_VQFN32-9-F
P
.
vsd
Figure 8
Recommended Footprint and Stencil Layout for the VQFN32-9 Package
Data Sheet
21
Revision 3.0, 2013-06-26
BGT24AR2
Silicon Germanium 24 GHz Twin IQ Receiver MMIC
Physical Characteristics
4.2
Reflow Profile
Soldering process qualified during qualification with “Preconditioning MSL-3: 30°C. 60%r.h., 192h, according to
JEDEC JSTD20”.
Reflow Profile recommended by Infineon Technologies AG
(based on IPC/JEDEC J-STD-020C)
BGT24AR2_Reflow_Profile.vsd
Figure 9
Reflow Profile for BGT24AR2 (VQFN32-9)
Data Sheet
22
Revision 3.0, 2013-06-26
BGT24AR2
Silicon Germanium 24 GHz Twin IQ Receiver MMIC
Physical Characteristics
4.3
Package Dimensions
All specified values in [mm]
BGT24AR2_VQFN32-9-PO.vsd
Figure 10
Package Outline (Top, Side and Bottom View)
BGT24AR2_VQFN32-9_ML.vsd
Figure 11
Marking Layout VQFN32-9
Data Sheet
23
Revision 3.0, 2013-06-26
BGT24AR2
Silicon Germanium 24 GHz Twin IQ Receiver MMIC
Physical Characteristics
All specified values in [mm]
BGT24AR2_VQFN32-9_C
T
.vsd
Figure 12
Tape of VQFN32-9
Data Sheet
24
Revision 3.0, 2013-06-26
Published by Infineon Technologies AG
