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BSC072N04LD
MOSFET
OptiMOS
TM
-T2ꢀPowerꢀTransistor,ꢀ40ꢀV
PG-TDSON-8-4
8
4
1
7
6
5
2
Features
·ꢀDualꢀN-channel,ꢀlogicꢀlevel
3
4
·ꢀFastꢀswitchingꢀMOSFETsꢀforꢀSMPS
·ꢀOptimizedꢀtechnologyꢀforꢀSynchronousꢀRectification
·ꢀPb-freeꢀplating;ꢀRoHSꢀcompliant
·ꢀ100%ꢀAvalancheꢀtested
·ꢀHalogen-freeꢀaccordingꢀtoꢀIEC61249-2-21
·ꢀSuperiorꢀthermalꢀresistance
1
8
7
6
2
3
5
ProductꢀValidation
Qualifiedꢀforꢀindustrialꢀapplicationsꢀaccordingꢀtoꢀtheꢀrelevantꢀtestsꢀof
JEDEC47/20/22
D1 D1
D2 D2
Tableꢀ1ꢀꢀꢀꢀꢀKeyꢀPerformanceꢀParameters
Parameter
Value
Unit
V
DS
40
V
S1
G1 S2
G2
R
DS(on),max
I
D
7.2
m
Ω
A
20
Typeꢀ/ꢀOrderingꢀCode
Package
SSO8 dual (TDSON-8-4)
Marking
RelatedꢀLinks
BSC072N04LD
072N04LD
–
Final Data Sheet
1
Rev.ꢀ2.0,ꢀꢀ2018-12-11
OptiMOS
TM
-T2ꢀPowerꢀTransistor,ꢀ40ꢀV
BSC072N04LD
TableꢀofꢀContents
Description .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Maximum ratings
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
Thermal characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
Electrical characteristics diagrams
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
Package Outlines
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision History
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
Trademarks .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
Disclaimer .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
Final Data Sheet
2
Rev.ꢀ2.0,ꢀꢀ2018-12-11
OptiMOS
TM
-T2ꢀPowerꢀTransistor,ꢀ40ꢀV
BSC072N04LD
1ꢀꢀꢀꢀꢀMaximumꢀratings
atꢀ
T
A
=25ꢀ°C,ꢀunlessꢀotherwiseꢀspecified,ꢀoneꢀtransistorꢀactive
Tableꢀ2ꢀꢀꢀꢀꢀMaximumꢀratings
Values
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Typ.
Max.
20
Continuous drain current
Pulsed drain current
1)
Avalanche energy, single pulse
2)
Gate source voltage
I
D
–
–
–
–
–
–
A
V
GS
=10ꢀV,ꢀ
T
C
=25ꢀ°C
T
A
=25ꢀ°C
I
D,pulse
E
AS
V
GS
P
tot
–
80
A
–
87
mJ
V
I
D
=10ꢀA,ꢀ
R
GS
=25ꢀ
Ω
–
-16
–
16
Power dissipation
65
W
T
C
=25ꢀ°C
IEC climatic category; DIN IEC 68-1:
55/175/56
Operating and storage temperature
T
j
,ꢀ
T
stg
-55
–
175
°C
2ꢀꢀꢀꢀꢀThermalꢀcharacteristics
Tableꢀ3ꢀꢀꢀꢀꢀThermalꢀcharacteristics
Values
Typ.
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Max.
Thermal resistance, junction – case,
bottom
R
thJC
R
thJA
R
thJA
–
–
–
–
2.3
°C/W –
°C/W –
°C/W –
Device on PCB,
–
–
60
6 cm² cooling area
3)
Device on PCB,
100
minimal footprint
4)
3ꢀꢀꢀꢀꢀElectricalꢀcharacteristics
atꢀ
T
j
=25ꢀ°C,ꢀunlessꢀotherwiseꢀspecified
Tableꢀ4ꢀꢀꢀꢀꢀStaticꢀcharacteristics
Values
Typ.
–
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
40
Max.
–
Drain-source breakdown voltage
Gate threshold voltage
V
(BR)DSS
V
GS(th)
V
V
V
GS
=0ꢀV,ꢀ
I
D
=1ꢀmA
V
DS
=
V
GS
,ꢀ
I
D
=30ꢀµA
1.2
1.7
2.2
–
–
0.1
10
1
100
V
DS
=40ꢀV,ꢀ
V
GS
=0ꢀV,ꢀ
T
j
=25ꢀ°C
V
DS
=40ꢀV,ꢀ
V
GS
=0ꢀV,ꢀ
T
j
=125ꢀ°C
Zero gate voltage drain current
Gate-source leakage current
Drain-source on-state resistance
I
DSS
µA
nA
I
GSS
–
–
100
V
GS
=20ꢀV,ꢀ
V
DS
=0ꢀV
–
–
6.5
8.0
7.2
9.2
V
GS
=10ꢀV,ꢀ
I
D
=17ꢀA
V
GS
=4.5ꢀV,ꢀ
I
D
=10ꢀA
R
DS(on)
m
Ω
1)
See Diagram 3 for more detailed information
2)
See Diagram 13 for more detailed information
3)
Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm
2
(one layer, 70 µm thick) copper area for drain connection.
PCB is vertical in still air.
4)
device mounted on a minimum pad (one layer, 70 µm thick)
Final Data Sheet
3
Rev.ꢀ2.0,ꢀꢀ2018-12-11
OptiMOS
TM
-T2ꢀPowerꢀTransistor,ꢀ40ꢀV
BSC072N04LD
Tableꢀ5ꢀꢀꢀꢀꢀDynamicꢀcharacteristics
Values
Typ.
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Max.
Input capacitance
1)
Output capacitance
1)
Reverse transfer capacitance
1)
C
iss
C
oss
C
rss
–
–
–
3070 3990 pF
V
GS
=0ꢀV,ꢀ
V
DS
=20ꢀV,ꢀ
f
=1ꢀMHz
V
GS
=0ꢀV,ꢀ
V
DS
=20ꢀV,ꢀ
f
=1ꢀMHz
V
GS
=0ꢀV,ꢀ
V
DS
=20ꢀV,ꢀ
f
=1ꢀMHz
680
36
880
72
pF
pF
V
DD
=20ꢀV,ꢀ
V
GS
=10ꢀV,ꢀ
I
D
=20ꢀA,
R
G,ext
=11ꢀ
Ω
Turn-on delay time
Rise time
t
d(on)
t
r
t
d(off)
t
f
–
–
–
–
9
–
–
–
–
ns
ns
ns
ns
V
DD
=20ꢀV,ꢀ
V
GS
=10ꢀV,ꢀ
I
D
=20ꢀA,
R
G,ext
=11ꢀ
Ω
4
V
DD
=20ꢀV,ꢀ
V
GS
=10ꢀV,ꢀ
I
D
=20ꢀA,
R
G,ext
=11ꢀ
Ω
Turn-off delay time
Fall time
50
25
V
DD
=20ꢀV,ꢀ
V
GS
=10ꢀV,ꢀ
I
D
=20ꢀA,
R
G,ext
=11ꢀ
Ω
Tableꢀ6ꢀꢀꢀꢀꢀGateꢀchargeꢀcharacteristics
2)
ꢀ
Values
Typ.
9
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Max.
13
Gate to source charge
Gate to drain charge
Gate charge total
1)
Q
gs
–
–
–
–
nC
nC
nC
V
V
DD
=20ꢀV,ꢀ
I
D
=20ꢀA,ꢀ
V
GS
=0ꢀtoꢀ10ꢀV
V
DD
=20ꢀV,ꢀ
I
D
=20ꢀA,ꢀ
V
GS
=0ꢀtoꢀ10ꢀV
V
DD
=20ꢀV,ꢀ
I
D
=20ꢀA,ꢀ
V
GS
=0ꢀtoꢀ10ꢀV
V
DD
=20ꢀV,ꢀ
I
D
=20ꢀA,ꢀ
V
GS
=0ꢀtoꢀ10ꢀV
Q
gd
4.1
8.2
52
Q
g
39
Gate plateau voltage
V
plateau
3.1
–
Tableꢀ7ꢀꢀꢀꢀꢀReverseꢀdiode
Values
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Typ.
–
Max.
20
80
1.1
–
Diode continuous forward current
Diode pulse current
I
S
–
–
–
–
–
A
T
C
=25ꢀ°C
I
S,pulse
V
SD
t
rr
–
A
T
C
=25ꢀ°C
Diode forward voltage
0.85
35
35
V
V
GS
=0ꢀV,ꢀ
I
F
=17ꢀA,ꢀ
T
j
=25ꢀ°C
V
R
=15ꢀV,ꢀ
I
F
=9ꢀA,ꢀd
i
F
/d
t
=100ꢀA/µs
V
R
=15ꢀV,ꢀ
I
F
=9ꢀA,ꢀd
i
F
/d
t
=100ꢀA/µs
Reverse recovery time
1)
Reverse recovery charge
1)
ns
nC
Q
rr
–
1)
Defined by design. Not subject to production test.
2)
See
″
Gate charge waveforms
″
for parameter definition
Final Data Sheet
4
Rev.ꢀ2.0,ꢀꢀ2018-12-11
OptiMOS
TM
-T2ꢀPowerꢀTransistor,ꢀ40ꢀV
BSC072N04LD
4ꢀꢀꢀꢀꢀElectricalꢀcharacteristicsꢀdiagrams
Diagramꢀ1:ꢀPowerꢀdissipation
Diagramꢀ2:ꢀDrainꢀcurrent
70
80
70
60
50
40
30
20
10
0
silicon limit
60
50
40
30
20
10
0
package limit
0
25
50
75
100
125
150
175
200
0
25
50
75
100
125
150
175
200
T
A
ꢀ[°C]
T
A
ꢀ[°C]
P
tot
=f(
T
A
),ꢀminimalꢀfootprint
I
D
=f(
T
A
);ꢀminimalꢀfootprint
Diagramꢀ3:ꢀSafeꢀoperatingꢀarea
Diagramꢀ4:ꢀMax.ꢀtransientꢀthermalꢀimpedance
10
2
10
1
single pulse
0.01
0.02
1 µs
10 µs
100 µs
0.05
0.1
10 ms
0.2
0.5
DC
1 ms
10
1
10
0
10
-1
10
-2
10
0
10
-1
10
-1
10
0
10
1
10
2
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
V
DS
ꢀ[V]
t
p
ꢀ[s]
I
D
=f(
V
DS
);ꢀ
T
C
=25ꢀ°C;ꢀ
D
=0;ꢀparameter:ꢀ
t
p
Z
thJC
=f(
t
p
);ꢀparameter:ꢀ
D
=
t
p
/
T
Final Data Sheet
5
Rev.ꢀ2.0,ꢀꢀ2018-12-11
OptiMOS
TM
-T2ꢀPowerꢀTransistor,ꢀ40ꢀV
BSC072N04LD
Diagramꢀ5:ꢀTyp.ꢀoutputꢀcharacteristics
Diagramꢀ6:ꢀTyp.ꢀdrain-sourceꢀonꢀresistance
80
40
4 V
3.5 V
70
60
50
40
30
20
10
0
4.5 V
10 V
30
3.5 V
4 V
3 V
20
10
4.5 V
10 V
3 V
0
0.0
1.0
2.0
3.0
4.0
0
10
20
30
40
50
60
70
80
V
DS
ꢀ[V]
I
D
ꢀ[A]
I
D
=f(
V
DS
),ꢀ
T
j
=25ꢀ°C;ꢀparameter:ꢀ
V
GS
R
DS(on)
=f(
I
D
),ꢀ
T
j
=25ꢀ°C;ꢀparameter:ꢀ
V
GS
Diagramꢀ7:ꢀTyp.ꢀtransferꢀcharacteristics
Diagramꢀ8:ꢀTyp.ꢀdrain-sourceꢀonꢀresistance
80
20.0
70
60
50
40
30
17.5
15.0
12.5
175 °C
10.0
7.5
5.0
2.5
0.0
25 °C
20
175 °C
10
0
25 °C
0
1
2
3
4
5
0
2
4
6
8
10
V
GS
ꢀ[V]
V
GS
ꢀ[V]
I
D
=f(
V
GS
),ꢀ|
V
DS
|>2|
I
D
|
R
DS(on)max
;ꢀparameter:ꢀ
T
j
R
DS(on)
=f(
V
GS
),ꢀ
I
D
=17ꢀA;ꢀparameter:ꢀ
T
j
Final Data Sheet
6
Rev.ꢀ2.0,ꢀꢀ2018-12-11
OptiMOS
TM
-T2ꢀPowerꢀTransistor,ꢀ40ꢀV
BSC072N04LD
Diagramꢀ9:ꢀNormalizedꢀdrain-sourceꢀonꢀresistance
Diagramꢀ10:ꢀTyp.ꢀgateꢀthresholdꢀvoltage
1.75
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
1.50
1.25
1.00
0.75
0.50
0.25
0.00
300 µA
30 µA
-80
-40
0
40
80
120
160
200
-80
-40
0
40
80
120
160
200
T
j
ꢀ[°C]
T
j
ꢀ[°C]
R
DS(on)
=f(
T
j
),ꢀ
I
D
=17ꢀA,ꢀ
V
GS
=10ꢀV
V
GS(th
=f(
T
j
),ꢀ
V
GS
=
V
DS
;ꢀparameter:ꢀ
I
D
Diagramꢀ11:ꢀTyp.ꢀcapacitances
Diagramꢀ12:ꢀForwardꢀcharacteristicsꢀofꢀreverseꢀdiode
10
4
10
2
25 °C
25 °C, max
175 °C
175 °C, max
Ciss
10
3
10
2
10
1
10
1
Coss
10
0
Crss
40
10
-1
0
5
10
15
20
25
30
35
0.00
0.25
0.50
0.75
1.00
1.25
1.50
V
DS
ꢀ[V]
V
SD
ꢀ[V]
C
=f(
V
DS
);ꢀ
V
GS
=0ꢀV;ꢀ
f
=1ꢀMHz
I
F
=f(
V
SD
);ꢀparameter:ꢀ
T
j
Final Data Sheet
7
Rev.ꢀ2.0,ꢀꢀ2018-12-11
OptiMOS
TM
-T2ꢀPowerꢀTransistor,ꢀ40ꢀV
BSC072N04LD
Diagramꢀ13:ꢀAvalancheꢀcharacteristics
Diagramꢀ14:ꢀTyp.ꢀgateꢀcharge
10
2
10
8 V
20 V
32 V
8
6
4
2
0
10
1
25 °C
100 °C
10
0
150 °C
10
-1
10
0
10
1
10
2
10
3
0
5
10
15
20
25
30
35
40
t
AV
ꢀ[µs]
Q
gate
ꢀ[nC]
I
AS
=f(
t
AV
);ꢀ
R
GS
=25ꢀ
Ω
;ꢀparameter:ꢀ
T
j,start
V
GS
=f(
Q
gate
),ꢀ
I
D
=20ꢀAꢀpulsed,ꢀ
T
j
=25ꢀ°C;ꢀparameter:ꢀ
V
DD
Diagramꢀ15:ꢀDrain-sourceꢀbreakdownꢀvoltage
Diagram Gate charge waveforms
44
43
42
41
40
39
38
-80
-40
0
40
80
120
160
200
T
j
ꢀ[°C]
V
BR(DSS)
=f(
T
j
);ꢀ
I
D
=1ꢀmA
Final Data Sheet
8
Rev.ꢀ2.0,ꢀꢀ2018-12-11
OptiMOS
TM
-T2ꢀPowerꢀTransistor,ꢀ40ꢀV
BSC072N04LD
5ꢀꢀꢀꢀꢀPackageꢀOutlines
MILLIMETERS
DIMENSIONS
MIN.
0.90
0.15
0.34
0.02
4.95
4.20
0.50
5.95
5.70
4.075
4.035
0.15
MAX.
1.10
0.35
0.54
0.22
5.35
4.40
0.70
6.35
6.10
4.275
4.235
0.35
DOCUMENT NO.
Z8B00189767
A
A1
b
REVISION
01
b1
D
D1
D2
E
SCALE 5:1
4mm
0
1
2
3
E1
E2
E3
E4
e
EUROPEAN PROJECTION
1.27
L
0.45
0.45
8.5
°
0.65
0.65
M
Θ
11.5
°
ISSUE DATE
31.07.2018
aaa
ddd
0.05
0.10
Figureꢀ1ꢀꢀꢀꢀꢀOutlineꢀSSO8ꢀdualꢀ(TDSON-8-4),ꢀdimensionsꢀinꢀmm
Final Data Sheet
9
Rev.ꢀ2.0,ꢀꢀ2018-12-11
OptiMOS
TM
-T2ꢀPowerꢀTransistor,ꢀ40ꢀV
BSC072N04LD
RevisionꢀHistory
BSC072N04LD
Revision:ꢀ2018-12-11,ꢀRev.ꢀ2.0
Previous Revision
Revision Date
Subjects (major changes since last revision)
Release of final version
2.0
2018-12-11
Trademarks
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Publishedꢀby
InfineonꢀTechnologiesꢀAG
81726ꢀMünchen,ꢀGermany
©ꢀ2018ꢀInfineonꢀTechnologiesꢀAG
AllꢀRightsꢀReserved.
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(“Beschaffenheitsgarantie”)ꢀ.
Withꢀrespectꢀtoꢀanyꢀexamples,ꢀhintsꢀorꢀanyꢀtypicalꢀvaluesꢀstatedꢀhereinꢀand/orꢀanyꢀinformationꢀregardingꢀtheꢀapplicationꢀofꢀthe
product,ꢀInfineonꢀTechnologiesꢀherebyꢀdisclaimsꢀanyꢀandꢀallꢀwarrantiesꢀandꢀliabilitiesꢀofꢀanyꢀkind,ꢀincludingꢀwithoutꢀlimitation
warrantiesꢀofꢀnon-infringementꢀofꢀintellectualꢀpropertyꢀrightsꢀofꢀanyꢀthirdꢀparty.
Inꢀaddition,ꢀanyꢀinformationꢀgivenꢀinꢀthisꢀdocumentꢀisꢀsubjectꢀtoꢀcustomer’sꢀcomplianceꢀwithꢀitsꢀobligationsꢀstatedꢀinꢀthis
documentꢀandꢀanyꢀapplicableꢀlegalꢀrequirements,ꢀnormsꢀandꢀstandardsꢀconcerningꢀcustomer’sꢀproductsꢀandꢀanyꢀuseꢀofꢀthe
productꢀofꢀInfineonꢀTechnologiesꢀinꢀcustomer’sꢀapplications.
Theꢀdataꢀcontainedꢀinꢀthisꢀdocumentꢀisꢀexclusivelyꢀintendedꢀforꢀtechnicallyꢀtrainedꢀstaff.ꢀItꢀisꢀtheꢀresponsibilityꢀofꢀcustomer’s
technicalꢀdepartmentsꢀtoꢀevaluateꢀtheꢀsuitabilityꢀofꢀtheꢀproductꢀforꢀtheꢀintendedꢀapplicationꢀandꢀtheꢀcompletenessꢀofꢀtheꢀproduct
informationꢀgivenꢀinꢀthisꢀdocumentꢀwithꢀrespectꢀtoꢀsuchꢀapplication.
Information
Forꢀfurtherꢀinformationꢀonꢀtechnology,ꢀdeliveryꢀtermsꢀandꢀconditionsꢀandꢀpricesꢀpleaseꢀcontactꢀyourꢀnearestꢀInfineon
Warnings
Dueꢀtoꢀtechnicalꢀrequirements,ꢀcomponentsꢀmayꢀcontainꢀdangerousꢀsubstances.ꢀForꢀinformationꢀonꢀtheꢀtypesꢀinꢀquestion,
pleaseꢀcontactꢀtheꢀnearestꢀInfineonꢀTechnologiesꢀOffice.
TheꢀInfineonꢀTechnologiesꢀcomponentꢀdescribedꢀinꢀthisꢀDataꢀSheetꢀmayꢀbeꢀusedꢀinꢀlife-supportꢀdevicesꢀorꢀsystemsꢀand/or
automotive,ꢀaviationꢀandꢀaerospaceꢀapplicationsꢀorꢀsystemsꢀonlyꢀwithꢀtheꢀexpressꢀwrittenꢀapprovalꢀofꢀInfineonꢀTechnologies,ꢀifꢀa
failureꢀofꢀsuchꢀcomponentsꢀcanꢀreasonablyꢀbeꢀexpectedꢀtoꢀcauseꢀtheꢀfailureꢀofꢀthatꢀlife-support,ꢀautomotive,ꢀaviationꢀand
aerospaceꢀdeviceꢀorꢀsystemꢀorꢀtoꢀaffectꢀtheꢀsafetyꢀorꢀeffectivenessꢀofꢀthatꢀdeviceꢀorꢀsystem.ꢀLifeꢀsupportꢀdevicesꢀorꢀsystemsꢀare
intendedꢀtoꢀbeꢀimplantedꢀinꢀtheꢀhumanꢀbodyꢀorꢀtoꢀsupportꢀand/orꢀmaintainꢀandꢀsustainꢀand/orꢀprotectꢀhumanꢀlife.ꢀIfꢀtheyꢀfail,ꢀitꢀis
reasonableꢀtoꢀassumeꢀthatꢀtheꢀhealthꢀofꢀtheꢀuserꢀorꢀotherꢀpersonsꢀmayꢀbeꢀendangered.
Final Data Sheet
10
Rev.ꢀ2.0,ꢀꢀ2018-12-11
