Infineon-Technologies-BSZ097N10NS5

Part #Infineon-Technologies-BSZ097N10NS5
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Infineon-Technologies-BSZ097N10NS5
BSZ097N10NS5  
MOSFET  
OptiMOS

TM

5ꢀPower-Transistor,ꢀ100ꢀV  
TSDSON-8ꢀFL  
(enlarged source interconnection)  
Features  
•ꢀIdealꢀforꢀhighꢀfrequencyꢀswitching  
•ꢀOptimizedꢀtechnologyꢀforꢀDC/DCꢀconverters  
•ꢀExcellentꢀgateꢀchargeꢀxꢀ
R

DS(on)

ꢀproductꢀ(FOM)  
•ꢀN-channel,ꢀLogicꢀlevel  
•ꢀ100%ꢀavalancheꢀtested  
•ꢀPb-freeꢀplating;ꢀRoHSꢀcompliant  
•ꢀQualifiedꢀaccordingꢀtoꢀJEDEC

1)

ꢀꢀforꢀtargetꢀapplications  
•ꢀHalogen-freeꢀaccordingꢀtoꢀIEC61249-2-21  
Tableꢀ1ꢀꢀꢀꢀꢀKeyꢀPerformanceꢀParameters  
S 1  
S 2  
S 3  
G 4  
8 D  
7 D  
Parameter  
Value  
100  
9.7  
Unit  
V

DS  

V
6 D  
5 D  
R

DS(on),max  

I

D  

m
Ω
 
A
40  
Typeꢀ/ꢀOrderingꢀCode  
Package  
PG-TSDSON-8 FL  
Marking  
RelatedꢀLinks  
BSZ097N10NS5  
097N10N  
–

1)

J-STD20 and JESD22  
Final Data Sheet  
1
Rev.ꢀ2.3,ꢀꢀ2017-01-26  

OptiMOS

TM

5ꢀPower-Transistor,ꢀ100ꢀV  
BSZ097N10NS5  
TableꢀofꢀContents  
Description .
 
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Maximum ratings
 
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3  
Thermal characteristics
 
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Electrical characteristics
 
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4  
Electrical characteristics diagrams
 
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6  
Package Outlines
 
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10  
Revision History
 
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11  
Trademarks .
 
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11  
Disclaimer .
 
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11  
Final Data Sheet  
2
Rev.ꢀ2.3,ꢀꢀ2017-01-26  

OptiMOS

TM

5ꢀPower-Transistor,ꢀ100ꢀV  
BSZ097N10NS5  
1ꢀꢀꢀꢀꢀMaximumꢀratings  
atꢀ
T

A

=25ꢀ°C,ꢀunlessꢀotherwiseꢀspecified  
Tableꢀ2ꢀꢀꢀꢀꢀMaximumꢀratings  
Values  
Typ.  
Parameter  
Symbol  
Unit Noteꢀ/ꢀTestꢀCondition  
Min.  
Max.  
–
–
–
–
–
–
40  
39  
11  
V

GS

=10ꢀV,ꢀ
T

C

=25ꢀ°C  
Continuous drain current  
I

D  

A
V

GS

=10ꢀV,ꢀ
T

C

=100ꢀ°C  
V

GS

=10ꢀV,ꢀ
T

A

=25ꢀ°C,ꢀ
R

thJA

=60ꢀK/W

1)  

Pulsed drain current

2)  

Avalanche energy, single pulse

3)  

I

D,pulse  

E

AS  

–
–
–
–
160  
97  
A
T

C

=25ꢀ°C  
–
mJ  
V
I

D

=20ꢀA,ꢀ
R

GS

=25ꢀ
Ω  
Gate source voltage  
V

GS  

-20  
20  
–
–
–
–
–
69  
2.1  
T

C

=25ꢀ°C  
Power dissipation  
P

tot  

W
T

A

=25ꢀ°C,ꢀ
R

thJA

=60ꢀK/W

1)  

IEC climatic category;  
DIN IEC 68-1: 55/150/56  
Operating and storage temperature  
T

j

,ꢀ
T

stg  

-55  
–
150  
°C  
2ꢀꢀꢀꢀꢀThermalꢀcharacteristics  
Tableꢀ3ꢀꢀꢀꢀꢀThermalꢀcharacteristics  
Values  
Typ.  
1.1  
Parameter  
Symbol  
Unit Noteꢀ/ꢀTestꢀCondition  
Min.  
Max.  
Thermal resistance, junction – case  
R

thJC  

R

thJA  

–
1.8  
K/W  
K/W  
–
–
Device on PCB,  
–
–
60  
6 cm

2

cooling area

1)  

1)

Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain  
connection. PCB is vertical in still air.  

2)

See Diagram 3 for more detailed information  

3)

See Diagram 13 for more detailed information  
Final Data Sheet  
3
Rev.ꢀ2.3,ꢀꢀ2017-01-26  

OptiMOS

TM

5ꢀPower-Transistor,ꢀ100ꢀV  
BSZ097N10NS5  
3ꢀꢀꢀꢀꢀElectricalꢀcharacteristics  
Tableꢀ4ꢀꢀꢀꢀꢀStaticꢀcharacteristics  
Values  
Typ.  
–
Parameter  
Symbol  
Unit Noteꢀ/ꢀTestꢀCondition  
Min.  
100  
2.2  
Max.  
–
Drain-source breakdown voltage  
Gate threshold voltage  
V

(BR)DSS  

V

GS(th)  

V
V
V

GS

=0ꢀV,ꢀ
I

D

=1ꢀmA  
V

DS

=
V

GS

,ꢀ
I

D

=36ꢀµA  
3.0  
3.8  
–
–
0.1  
10  
1
100  
V

DS

=100ꢀV,ꢀ
V

GS

=0ꢀV,ꢀ
T

j

=25ꢀ°C  
V

DS

=100ꢀV,ꢀ
V

GS

=0ꢀV,ꢀ
T

j

=125ꢀ°C  
Zero gate voltage drain current  
Gate-source leakage current  
Drain-source on-state resistance  
I

DSS  

µA  
nA  
I

GSS  

–
10  
100  
V

GS

=20ꢀV,ꢀ
V

DS

=0ꢀV  
–
–
10.3  
8.3  
13.0  
9.7  
V

GS

=6ꢀV,ꢀ
I

D

=5ꢀA  
V

GS

=10ꢀV,ꢀ
I

D

=20ꢀA  
R

DS(on)  

m
Ω  
Gate resistance

1)  

Transconductance  
R

G  

g

fs  

–
1.2  
46  
1.8  
–
Ω
–
23  
S
|
V

DS

|>2|
I

D

|
R

DS(on)max

,ꢀ
I

D

=20ꢀA  
Tableꢀ5ꢀꢀꢀꢀꢀDynamicꢀcharacteristics  
Values  
Typ.  
Parameter  
Symbol  
Unit Noteꢀ/ꢀTestꢀCondition  
Min.  
Max.  
Input capacitance

1)  

Output capacitance

1)  

Reverse transfer capacitance

1)  

C

iss  

C

oss  

C

rss  

–
–
–
1600 2080 pF  
V

GS

=0ꢀV,ꢀ
V

DS

=50ꢀV,ꢀ
f
=1ꢀMHz  
V

GS

=0ꢀV,ꢀ
V

DS

=50ꢀV,ꢀ
f
=1ꢀMHz  
V

GS

=0ꢀV,ꢀ
V

DS

=50ꢀV,ꢀ
f
=1ꢀMHz  
250  
12  
325  
21  
pF  
pF  
V

DD

=50ꢀV,ꢀ
V

GS

=10ꢀV,ꢀ
I

D

=20ꢀA,  
R

G,ext

=3ꢀ
Ω  
Turn-on delay time  
Rise time  
t

d(on)  

t

r  

t

d(off)  

t

f  

–
–
–
–
11  
5
–
–
–
–
ns  
ns  
ns  
ns  
V

DD

=50ꢀV,ꢀ
V

GS

=10ꢀV,ꢀ
I

D

=20ꢀA,  
R

G,ext

=3ꢀ
Ω  
V

DD

=50ꢀV,ꢀ
V

GS

=10ꢀV,ꢀ
I

D

=20ꢀA,  
R

G,ext

=3ꢀ
Ω  
Turn-off delay time  
Fall time  
21  
5
V

DD

=50ꢀV,ꢀ
V

GS

=10ꢀV,ꢀ
I

D

=20ꢀA,  
R

G,ext

=3ꢀ
Ω  
Tableꢀ6ꢀꢀꢀꢀꢀGateꢀchargeꢀcharacteristics

2)

ꢀ  
Values  
Parameter  
Symbol  
Unit Noteꢀ/ꢀTestꢀCondition  
Min.  
Typ.  
7
Max.  
Gate to source charge  
Gate charge at threshold  
Gate to drain charge

1)  

Switching charge  
Gate charge total

1)  

Gate plateau voltage  
Output charge

1)  

Q

gs  

–
–
–
–
–
–
–
–
nC  
nC  
nC  
nC  
nC  
V
V

DD

=50ꢀV,ꢀ
I

D

=20ꢀA,ꢀ
V

GS

=0ꢀtoꢀ10ꢀV  
V

DD

=50ꢀV,ꢀ
I

D

=20ꢀA,ꢀ
V

GS

=0ꢀtoꢀ10ꢀV  
V

DD

=50ꢀV,ꢀ
I

D

=20ꢀA,ꢀ
V

GS

=0ꢀtoꢀ10ꢀV  
V

DD

=50ꢀV,ꢀ
I

D

=20ꢀA,ꢀ
V

GS

=0ꢀtoꢀ10ꢀV  
V

DD

=50ꢀV,ꢀ
I

D

=20ꢀA,ꢀ
V

GS

=0ꢀtoꢀ10ꢀV  
V

DD

=50ꢀV,ꢀ
I

D

=20ꢀA,ꢀ
V

GS

=0ꢀtoꢀ10ꢀV  
V

DD

=50ꢀV,ꢀ
V

GS

=0ꢀV  
Q

g(th)  

Q

gd  

4
–
5
8
–
Q

sw  

7
Q

g  

22  
4.6  
30  
28  
–
V

plateau  

Q

oss  

40  
nC  

1)

Defined by design. Not subject to production test  

2)

See
″
Gate charge waveforms
″
for parameter definition  
Final Data Sheet  
4
Rev.ꢀ2.3,ꢀꢀ2017-01-26  

OptiMOS

TM

5ꢀPower-Transistor,ꢀ100ꢀV  
BSZ097N10NS5  
Tableꢀ7ꢀꢀꢀꢀꢀReverseꢀdiode  
Values  
Parameter  
Symbol  
Unit Noteꢀ/ꢀTestꢀCondition  
Min.  
Typ.  
–
Max.  
40  
Diode continuous forward current  
Diode pulse current  
I

S  

–
–
–
–
–
A
T

C

=25ꢀ°C  
I

S,pulse  

V

SD  

t

rr  

–
160  
1.2  
85  
A
T

C

=25ꢀ°C  
Diode forward voltage  
0.9  
43  
60  
V
V

GS

=0ꢀV,ꢀ
I

F

=20ꢀA,ꢀ
T

j

=25ꢀ°C  
V

R

=50ꢀV,ꢀ
I

F

=20ꢀA,ꢀd
i

F

/d
t
=100ꢀA/µs  
V

R

=50ꢀV,ꢀ
I

F

=20ꢀA,ꢀd
i

F

/d
t
=100ꢀA/µs  
Reverse recovery time

1)  

Reverse recovery charge

1)  

ns  
nC  
Q

rr  

120  

1)

Defined by design. Not subject to production test  
Final Data Sheet  
5
Rev.ꢀ2.3,ꢀꢀ2017-01-26  

OptiMOS

TM

5ꢀPower-Transistor,ꢀ100ꢀV  
BSZ097N10NS5  
4ꢀꢀꢀꢀꢀElectricalꢀcharacteristicsꢀdiagrams  
Diagramꢀ1:ꢀPowerꢀdissipation  
Diagramꢀ2:ꢀDrainꢀcurrent  
80  
45  
40  
35  
30  
25  
20  
15  
10  
5
70  
60  
50  
40  
30  
20  
10  
0
0
0
25  
50  
75  
100  
125  
150  
175  
0
25  
50  
75  
100  
125  
150  
175  
T

C

ꢀ[°C]  
T

C

ꢀ[°C]  
P

tot

=f(
T

C

)  
I

D

=f(
T

C

);ꢀ
V

GS

≥
10ꢀV  
Diagramꢀ3:ꢀSafeꢀoperatingꢀarea  
Diagramꢀ4:ꢀMax.ꢀtransientꢀthermalꢀimpedance  
10

3  

10

1  

1 µs  
10

2  

10

0  

10 µs  
0.5  
0.2  
0.1  
100 µs  
10

1  

DC  
0.05  
10

-1  

1 ms  
0.02  
10

0  

0.01  
10 ms  
single pulse  
10

-1  

10

-2  

10

-1  

10

0  

10

1  

10

2  

10

3  

10

-6  

10

-5  

10

-4  

10

-3  

10

-2  

10

-1  

10

0  

V

DS

ꢀ[V]  
t

p

ꢀ[s]  
I

D

=f(
V

DS

);ꢀ
T

C

=25ꢀ°C;ꢀ
D
=0;ꢀparameter:ꢀ
t

p  

Z

thJC

=f(
t

p

);ꢀparameter:ꢀ
D
=
t

p

/
T  
Final Data Sheet  
6
Rev.ꢀ2.3,ꢀꢀ2017-01-26  

OptiMOS

TM

5ꢀPower-Transistor,ꢀ100ꢀV  
BSZ097N10NS5  
Diagramꢀ5:ꢀTyp.ꢀoutputꢀcharacteristics  
Diagramꢀ6:ꢀTyp.ꢀdrain-sourceꢀonꢀresistance  
160  
32  
8 V  
140  
28  
7 V  
10 V  
6 V  
120  
100  
24  
4.5 V  
20  
5 V  
5.5 V  
80  
16  
5.5 V  
60  
12  
6 V  
7 V  
5 V  
10 V  
40  
8
20  
4
4.5 V  
4 V  
0
0
0
1
2
3
4
5
0
20  
40  
60  
80  
100  
V

DS

ꢀ[V]  
I

D

ꢀ[A]  
I

D

=f(
V

DS

);ꢀ
T

j

=25ꢀ°C;ꢀparameter:ꢀ
V

GS  

R

DS(on)

=f(
I

D

);ꢀ
T

j

=25ꢀ°C;ꢀparameter:ꢀ
V

GS  

Diagramꢀ7:ꢀTyp.ꢀtransferꢀcharacteristics  
Diagramꢀ8:ꢀTyp.ꢀforwardꢀtransconductance  
80  
70  
60  
50  
40  
30  
20  
10  
0
60  
40  
20  
150 °C  
25 °C  
0
0
1
2
3
4
5
6
7
0
10  
20  
30  
40  
50  
V

GS

ꢀ[V]  
I

D

ꢀ[A]  
I

D

=f(
V

GS

);ꢀ|
V

DS

|>2|
I

D

|
R

DS(on)max

;ꢀparameter:ꢀ
T

j  

g

fs

=f(
I

D

);ꢀ
T

j

=25ꢀ°C  
Final Data Sheet  
7
Rev.ꢀ2.3,ꢀꢀ2017-01-26  

OptiMOS

TM

5ꢀPower-Transistor,ꢀ100ꢀV  
BSZ097N10NS5  
Diagramꢀ9:ꢀDrain-sourceꢀon-stateꢀresistance  
Diagramꢀ10:ꢀTyp.ꢀgateꢀthresholdꢀvoltage  
20  
4.0  
3.5  
360 µA  
15  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
36 µA  
max  
10  
Typ  
5
0
-60  
-20  
20  
60  
100  
140  
180  
-60  
-20  
20  
60  
100  
140  
180  
T

j

ꢀ[°C]  
T

j

ꢀ[°C]  
R

DS(on)

=f(
T

j

);ꢀ
I

D

=20ꢀA;ꢀ
V

GS

=10ꢀV  
V

GS(th)

=f(
T

j

);ꢀ
V

GS

=
V

DS  

Diagramꢀ11:ꢀTyp.ꢀcapacitances  
Diagramꢀ12:ꢀForwardꢀcharacteristicsꢀofꢀreverseꢀdiode  
10

4  

10

3  

25 °C  
150 °C  
25 °C max  
150 °C max  
Ciss  
10

3  

10

2  

10

1  

10

0  

10

2  

10

1  

10

0  

Coss  
Crss  
0
20  
40  
60  
80  
0.0  
0.5  
1.0  
1.5  
2.0  
V

DS

ꢀ[V]  
V

SD

ꢀ[V]  
C
=f(
V

DS

);ꢀ
V

GS

=0ꢀV;ꢀ
f
=1ꢀMHz  
I

F

=f(
V

SD

);ꢀparameter:ꢀ
T

j  

Final Data Sheet  
8
Rev.ꢀ2.3,ꢀꢀ2017-01-26  

OptiMOS

TM

5ꢀPower-Transistor,ꢀ100ꢀV  
BSZ097N10NS5  
Diagramꢀ13:ꢀAvalancheꢀcharacteristics  
Diagramꢀ14:ꢀTyp.ꢀgateꢀcharge  
10

2  

10  
80 V  
9
8
7
6
5
4
3
2
1
0
50 V  
20 V  
10

1  

25 °C  
100 °C  
125 °C  
10

0  

10

-1  

10

0  

10

1  

10

2  

10

3  

0
5
10  
15  
20  
25  
30  
t

AV

ꢀ[µs]  
Q

gate

ꢀ[nC]  
I

AS

=f(
t

AV

);ꢀ
R

GS

=25ꢀ
Ω
;ꢀparameter:ꢀ
T

j(start)  

V

GS

=f(
Q

gate

);ꢀ
I

D

=20ꢀAꢀpulsed;ꢀparameter:ꢀ
V

DD  

Diagramꢀ15:ꢀDrain-sourceꢀbreakdownꢀvoltage  
Gate charge waveforms  
110  
105  
100  
95  
90  
-60  
-20  
20  
60  
100  
140  
180  
T

j

ꢀ[°C]  
V

BR(DSS)

=f(
T

j

);ꢀ
I

D

=1ꢀmA  
Final Data Sheet  
9
Rev.ꢀ2.3,ꢀꢀ2017-01-26  

OptiMOS

TM

5ꢀPower-Transistor,ꢀ100ꢀV  
BSZ097N10NS5  
5ꢀꢀꢀꢀꢀPackageꢀOutlines  
Figureꢀ1ꢀꢀꢀꢀꢀOutlineꢀPG-TSDSON-8ꢀFL,ꢀdimensionsꢀinꢀmm/inches  
Final Data Sheet  
10  
Rev.ꢀ2.3,ꢀꢀ2017-01-26  

OptiMOS

TM

5ꢀPower-Transistor,ꢀ100ꢀV  
BSZ097N10NS5  
RevisionꢀHistory  
BSZ097N10NS5  
Revision:ꢀ2017-01-26,ꢀRev.ꢀ2.3  
Previous Revision  
Revision Date  
Subjects (major changes since last revision)  
2.1  
2.2  
2.3  
Release of Final Version  
2014-05-05  
2016-09-23  
2017-01-26  
Update Avalanche Energy  
Update Id at Tc=100°C and Ta=25°C  
TrademarksꢀofꢀInfineonꢀTechnologiesꢀAG  
AURIX™,ꢀC166™,ꢀCanPAK™,ꢀCIPOS™,ꢀCoolGaN™,ꢀCoolMOS™,ꢀCoolSET™,ꢀCoolSiC™,ꢀCORECONTROL™,ꢀCROSSAVE™,ꢀDAVE™,ꢀDI-POL™,ꢀDrBlade™,  
EasyPIM™,ꢀEconoBRIDGE™,ꢀEconoDUAL™,ꢀEconoPACK™,ꢀEconoPIM™,ꢀEiceDRIVER™,ꢀeupec™,ꢀFCOS™,ꢀHITFET™,ꢀHybridPACK™,ꢀInfineon™,  
ISOFACE™,ꢀIsoPACK™,ꢀi-Wafer™,ꢀMIPAQ™,ꢀModSTACK™,ꢀmy-d™,ꢀNovalithIC™,ꢀOmniTune™,ꢀOPTIGA™,ꢀOptiMOS™,ꢀORIGA™,ꢀPOWERCODE™,  
PRIMARION™,ꢀPrimePACK™,ꢀPrimeSTACK™,ꢀPROFET™,ꢀPRO-SIL™,ꢀRASIC™,ꢀREAL3™,ꢀReverSave™,ꢀSatRIC™,ꢀSIEGET™,ꢀSIPMOS™,ꢀSmartLEWIS™,  
SOLIDꢀFLASH™,ꢀSPOC™,ꢀTEMPFET™,ꢀthinQꢁ™,ꢀTRENCHSTOP™,ꢀTriCore™.  
TrademarksꢀupdatedꢀAugustꢀ2015  
OtherꢀTrademarks  
Allꢀreferencedꢀproductꢀorꢀserviceꢀnamesꢀandꢀtrademarksꢀareꢀtheꢀpropertyꢀofꢀtheirꢀrespectiveꢀowners.  
WeꢀListenꢀtoꢀYourꢀComments  
Anyꢀinformationꢀwithinꢀthisꢀdocumentꢀthatꢀyouꢀfeelꢀisꢀwrong,ꢀunclearꢀorꢀmissingꢀatꢀall?ꢀYourꢀfeedbackꢀwillꢀhelpꢀusꢀtoꢀcontinuously  
improveꢀtheꢀqualityꢀofꢀthisꢀdocument.ꢀPleaseꢀsendꢀyourꢀproposalꢀ(includingꢀaꢀreferenceꢀtoꢀthisꢀdocument)ꢀto:  
Publishedꢀby  
InfineonꢀTechnologiesꢀAG  
81726ꢀMünchen,ꢀGermany  
©ꢀ2017ꢀInfineonꢀTechnologiesꢀAG  
AllꢀRightsꢀReserved.  
LegalꢀDisclaimer  
Theꢀinformationꢀgivenꢀinꢀthisꢀdocumentꢀshallꢀinꢀnoꢀeventꢀbeꢀregardedꢀasꢀaꢀguaranteeꢀofꢀconditionsꢀorꢀcharacteristicsꢀ  
(“Beschaffenheitsgarantie”)ꢀ.  
Withꢀrespectꢀtoꢀanyꢀexamples,ꢀhintsꢀorꢀanyꢀtypicalꢀvaluesꢀstatedꢀhereinꢀand/orꢀanyꢀinformationꢀregardingꢀtheꢀapplicationꢀofꢀthe  
product,ꢀInfineonꢀTechnologiesꢀherebyꢀdisclaimsꢀanyꢀandꢀallꢀwarrantiesꢀandꢀliabilitiesꢀofꢀanyꢀkind,ꢀincludingꢀwithoutꢀlimitation  
warrantiesꢀofꢀnon-infringementꢀofꢀintellectualꢀpropertyꢀrightsꢀofꢀanyꢀthirdꢀparty.  
Inꢀaddition,ꢀanyꢀinformationꢀgivenꢀinꢀthisꢀdocumentꢀisꢀsubjectꢀtoꢀcustomer’sꢀcomplianceꢀwithꢀitsꢀobligationsꢀstatedꢀinꢀthis  
documentꢀandꢀanyꢀapplicableꢀlegalꢀrequirements,ꢀnormsꢀandꢀstandardsꢀconcerningꢀcustomer’sꢀproductsꢀandꢀanyꢀuseꢀofꢀthe  
productꢀofꢀInfineonꢀTechnologiesꢀinꢀcustomer’sꢀapplications.  
Theꢀdataꢀcontainedꢀinꢀthisꢀdocumentꢀisꢀexclusivelyꢀintendedꢀforꢀtechnicallyꢀtrainedꢀstaff.ꢀItꢀisꢀtheꢀresponsibilityꢀofꢀcustomer’s  
technicalꢀdepartmentsꢀtoꢀevaluateꢀtheꢀsuitabilityꢀofꢀtheꢀproductꢀforꢀtheꢀintendedꢀapplicationꢀandꢀtheꢀcompletenessꢀofꢀtheꢀproduct  
informationꢀgivenꢀinꢀthisꢀdocumentꢀwithꢀrespectꢀtoꢀsuchꢀapplication.  
Information  
Forꢀfurtherꢀinformationꢀonꢀtechnology,ꢀdeliveryꢀtermsꢀandꢀconditionsꢀandꢀpricesꢀpleaseꢀcontactꢀyourꢀnearestꢀInfineon  
TechnologiesꢀOfficeꢀ(

).  
Warnings  
Dueꢀtoꢀtechnicalꢀrequirements,ꢀcomponentsꢀmayꢀcontainꢀdangerousꢀsubstances.ꢀForꢀinformationꢀonꢀtheꢀtypesꢀinꢀquestion,  
pleaseꢀcontactꢀtheꢀnearestꢀInfineonꢀTechnologiesꢀOffice.  
TheꢀInfineonꢀTechnologiesꢀcomponentꢀdescribedꢀinꢀthisꢀDataꢀSheetꢀmayꢀbeꢀusedꢀinꢀlife-supportꢀdevicesꢀorꢀsystemsꢀand/or  
automotive,ꢀaviationꢀandꢀaerospaceꢀapplicationsꢀorꢀsystemsꢀonlyꢀwithꢀtheꢀexpressꢀwrittenꢀapprovalꢀofꢀInfineonꢀTechnologies,ꢀifꢀa  
failureꢀofꢀsuchꢀcomponentsꢀcanꢀreasonablyꢀbeꢀexpectedꢀtoꢀcauseꢀtheꢀfailureꢀofꢀthatꢀlife-support,ꢀautomotive,ꢀaviationꢀand  
aerospaceꢀdeviceꢀorꢀsystemꢀorꢀtoꢀaffectꢀtheꢀsafetyꢀorꢀeffectivenessꢀofꢀthatꢀdeviceꢀorꢀsystem.ꢀLifeꢀsupportꢀdevicesꢀorꢀsystemsꢀare  
intendedꢀtoꢀbeꢀimplantedꢀinꢀtheꢀhumanꢀbodyꢀorꢀtoꢀsupportꢀand/orꢀmaintainꢀandꢀsustainꢀand/orꢀprotectꢀhumanꢀlife.ꢀIfꢀtheyꢀfail,ꢀitꢀis  
reasonableꢀtoꢀassumeꢀthatꢀtheꢀhealthꢀofꢀtheꢀuserꢀorꢀotherꢀpersonsꢀmayꢀbeꢀendangered.  
Final Data Sheet  
11  
Rev.ꢀ2.3,ꢀꢀ2017-01-26