Infineon-Technologies-IGLD60R070D1

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Infineon-Technologies-IGLD60R070D1
IGLD60R070D1  
IGLD60R070D1  
600V CoolGaN
™
enhancement-mode Power Transistor  
Features  
Enhancement mode transistor – Normally OFF switch  
Ultra fast switching  
No reverse-recovery charge  
G
SK  
Capable of reverse conduction  
S
S
Low gate charge, low output charge  
Superior commutation ruggedness  
Qualified for industrial applications according to JEDEC  
Standards (JESD47 and JESD22)  
D
D
D
D
1
S
S
K  
G
8
Benefits  
Gate  
8
Improves system efficiency  
Drain  
1,2,3,4  
7
Improves power density  
Enables higher operating frequency  
System cost reduction savings  
Reduces EMI  
Kelvin Source  
Source  
5,6  
Applications  
Industrial, telecom, datacenter SMPS based on the half-bridge topology  
(half-bridge topologies for hard and soft switching such as Totem pole PFC,  
high frequency LLC).  
For other applications:
review CoolGaN
™
reliability white paper and contact  
Infineon regional support  
Table 1  
Key Performance Parameters at T

j

= 25 °C  
Parameter  
V

DS,max  

R

DS(on),max  

Q

G,typ  

Value  
600  
70  
5.8  
60  
Unit  
V
m
Ω  
nC  
A
I

D,pulse  

Q

oss

@ 400 V  
Q

rr  

41  
0
nC  
nC  
Table 2  
Ordering Information  
Type / Ordering Code  
Package  
Marking  
Related links  
IGLD60R070D1  
PG-LSON-8-1  
60R070D1  
see Appendix A  
Final Data Sheet  
Please read the Important Notice and Warnings at the end of this document  
Rev. 2.1  
2020-01-16  
 
 
 

IGLD60R070D1  
600V CoolGaN
™
enhancement-mode Power Transistor  
Table of Contents  
Final Data Sheet  
2
Rev. 2.1  
2020-01-16  
 

IGLD60R070D1  
600V CoolGaN
™
enhancement-mode Power Transistor  
1
Maximum ratings  
at T

j

= 25 °C, unless otherwise specified.Continuous application of maximum ratings can deteriorate transistor  
lifetime. For further information, contact your local Infineon sales office.  
Table 3  
Maximum ratings  
Parameter  
Symbol  
Values  
Unit  
Note/Test Condition  
V

GS

= 0 V  
Min. Typ. Max.  
Drain Source Voltage, continuous

V

DS,max  

V

DS,bd  

–
–
–
600  
–
V
V
Drain source destructive breakdown  
voltage

2  

800  
V

GS

= 0 V, I

DS

= 12.2 mA  
Drain source voltage, pulsed

2  

V

DS,pulse  

–
–
–
750  
650  
V
V
T

j

= 25 °C;
 
V

GS

≤ 0 V;
 
≤1 hour  
of total time  
T

j

= 125 °C,
 
V

GS

≤ 0 V; ≤1 hour  
of total time  
Switching surge voltage, pulsed

2  

V

DS,surge  

–
750  
V
DC bus voltage = 700 V;
 
turn  
off V

DS,pulse

= 750 V; turn on  
I

D,pulse

= 27 A; T

j

= 105 °C;  
f ≤ 100 kHz, t ≤ 100 secs (10  
million pulses)  
Continuous current, drain source  
I

D  

–
–
–
–
15  
60  
A
A
T

C

= 25 °C;  
3 4  
Pulsed current, drain source  
I

D,pulse  

T

C

= 25 °C; I

G

= 26.1 mA;  
T

C

= 125 °C;
 
I

G

= 26.1 mA;  
–
–
35  
A
4 5  
Pulsed current, drain source  
I

D,pulse  

4 5 6  
Gate current, continuous  
I

G,avg  

–
–
–
–
20  
mA T

j

= -55 °C
 
to 150 °C;  
Gate current, pulsed

4 6  

I

G,pulse  

2000  
mA T

j

= -55 °C
 
to 150 °C;  
t

PULSE

= 50 ns, f=100 kHz  
Gate source voltage, continuous

6  

Gate source voltage, pulsed

6  

V

GS  

-10  
-25  
–
–
–
–
V
V
T

j

= -55 °C
 
to 150 °C;  
V

GS,pulse  

T

j

= -55 °C to 150 °C;  
t

PULSE

= 50 ns, f = 100 kHz;  
open drain  
Power dissipation  
P

tot  

T

j  

–
–
–
–
114  
150  
150  
W
T

C

= 25 °C  
Operating temperature  
Storage temperature  
-55  
°C  
T

stg  

°C Max
 
shelf life depends on  
storage conditions.  
-55  
Drain-source voltage slew-rate  
dV/dt  
200  
V/ns  
1
All devices are 100% tested at I

DS

= 12.2 mA to assure V

DS

≥ 800 V  
2
3
4
5
6
Provided as measure of robustness under abnormal operating conditions and not recommended for normal operation  
Limits derived from product characterization, parameter not measured during production  
Ensure that average gate drive current, I

G,avg

is ≤ 20 mA. Please see figure 27 for I

G,avg

, I

G,pulse

and I

G

details  
Parameter is influenced by rel-requirements. Please contact the local Infineon Sales Office to get an assessment of your application  
We recommend using an advanced driving technique to optimize the device performance. Please see gate drive application note for  
details  
Final Data Sheet  
3
Rev. 2.1  
2020-01-16  
 
 

IGLD60R070D1  
600V CoolGaN
™
enhancement-mode Power Transistor  
2
Thermal characteristics  
Table 4  
Thermal characteristics  
Parameter  
Symbol  
Values  
Unit  
Note/Test Condition  
Min. Typ. Max.  
Thermal resistance, junction-case  
Reflow soldering temperature  
R

thJC  

T

sold  

–
–
–
–
1.1  
°C/W  
245  
°C MSL3  
Final Data Sheet  
4
Rev. 2.1  
2020-01-16  
 

IGLD60R070D1  
600V CoolGaN
™
enhancement-mode Power Transistor  
3
Electrical characteristics  
at T

j

= 25 °C, unless specified otherwise  
Table 5
 
Static characteristics  
Parameter  
Symbol  
Values  
Unit  
Note/Test Condition  
Min. Typ.
 
Max.  
Gate threshold voltage  
V

GS(th)  

0.9  
0.7  
1.2  
1.0  
1
20  
60  
1.6  
1.4  
100  
–
V
I

DS

= 2.6 mA; V

DS

= 10 V; T

j

=25 °C  
I

DS

= 2.6 mA; V

DS

= 10 V; T

j

=125 °C  
Drain-Source leakage current  
–
–
–
µA V

DS

= 600 V; V

GS

= 0 V; T

j

= 25 °C  
V

DS

= 600 V; V

GS

= 0 V; T

j

= 150 °C  
I

DSS  

Drain-Source leakage current at  
application conditions

Gate-Source leakage

rrent  
–
μA  
I

DSSapp  

I

GSS  

V

DS

= 400 V; V

GS

= 0 V; T

j

= 125 °C  
-1  
-1  
–
–
–
–
–
mA V

DS

= 0 V; V

GS

= -10 V; T

j

= 25 °C  
V

DS

= 0 V; V

GS

= -10 V; T

j

= 125 °C  
Drain-Source on-state resistance  
Gate resistance  
0.055 0.070  
0.100  
Ω
I

G

= 26.1 mA; I

D

= 8 A; T

j

= 25 °C  
I

G

= 26.1 mA; I

D

= 8 A; T

j

= 150 °C  
R

DS(on)  

R

G,int  

–
–
–
0.78  
–
Ω
LCR impedance measurement;  
f = f

res

; open drain;  
Table 6  
Dynamic characteristics  
Parameter Symbol  
Values  
Unit  
Note/Test Condition  
Min. Typ.
 
Max.  
V

GS

= 0 V; V

DS

= 400 V;  
f = 1 MHz  
380  
72  
–
–
–
–
–
Input capacitance  
C

iss  

–
–
–
–
–
pF  
pF  
pF  
pF  
pF  
V

GS

= 0 V; V

DS

= 400 V;  
f = 1 MHz  
Output capacitance  
C

oss  

C

rss  

Reverse Transfer capacitance  
V

GS

= 0 V; V

DS

= 400 V;  
f = 1 MHz  
0.3  
80  
Effective o

capacitance,  
energy related

C

o(er)  

C

o(tr)  

V

DS

= 0 to 400 V  
Effective o

t capacitance,  
time related

V

GS

= 0 V; V

DS

= 0 to 400 V;  
Id = const  
102.5  
41  
Output charge  
Turn- on delay time  
Turn- off delay time  
Rise time  
Q

oss  

t

d(on)  

t

d(off)  

t

r  

–
–
–
–
–
–
–
–
–
–
nC V

DS

= 0 to 400 V  
15  
15  
ns  
ns  
ns  
ns  
9
13  
t

f  

Fall time  

1

Parameter represents end of use leakage in applications  

2

C

o(er)

is a fixed capacitance that gives the same stored energy as Coss while VDS is rising from 0 to 400 V  

3

C

o(tr)

is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 400 V  
Final Data Sheet  
5
Rev. 2.1  
2020-01-16  
 
 
 
 

IGLD60R070D1  
600V CoolGaN
™
enhancement-mode Power Transistor  
Table 7  
Gate charge characteristics  
Parameter Symbol  
Values  
Unit  
Note/Test Condition  
Min. Typ.
 
Max.  
I

GS

= 0 to 10 mA; V

DS

= 400 V;  
I

D

= 8 A  
5.8  
–
Gate charge  
Q

G  

–
nC  
Table 8  
Reverse conduction characteristics  
Parameter Symbol
 
Values  
Min. Typ.
 
Max.  
Unit  
Note/Test Condition  
2.2  
–
2.5  
60  
–
Source-Drain reverse voltage  
Pulsed current, reverse  
V

SD  

–
–
–
–
–
V
A
V

GS

= 0 V; I

SD

= 8 A  
I

G

= 26.1 mA  
I

S,pulse  

Reverse recovery charge  
Reverse recovery time  
Q

rr  

0
I

S

= 8 A, V

DS

= 400 V  
nC  
ns  
A
t

rr  

0
–
Peak reverse recovery current  
I

rrm  

0
–

1

Excluding Qoss  
Final Data Sheet  
6
Rev. 2.1  
2020-01-16  
 

IGLD60R070D1  
600V CoolGaN
™
enhancement-mode Power Transistor  
4
Electrical characteristics diagrams  
at T

j

= 25 °C, unless specified otherwise  
Figure 1  
Power dissipation  
Figure 2  
Max. transient thermal impedance  
120  
1
100  
80  
60  
40  
20  
0
0.1  
D=  
0.5  
0.2  
0.1  
0.05  
0.02  
0.01  
single pulse  
0.01  
0
20  
40  
60  
80  
100 120 140 160  
1E-6  
1E-4  
1E-2  
1E+0  
1E+2  
T

C

[

o

C]  
t

p

[s]  
P

tot

=f(T

c

)  
Z

thJC

=f(t

p

, D)  
Figure 3  
Safe operating area  
Figure 4  
Safe operating area  
100  
100  
tp = 20 ns  
tp = 20 ns  
tp = 10 μs  
tp = 10 μs  
10  
1
10  
1
tp = 100 μs  
tp = 1 ms  
DC  
Limited by  
R

DS

(on)  
Limited by  
R

DS

(on)  
tp = 100 μs  
tp = 1 ms  
DC  
0.1  
0.01  
0.1  
0.01  
1
10  
100  
1000  
1
10  
100  
1000  
V

DS

[V]  
V

DS

[V]  
I

D

=f(V

DS

);
T

C

= 25 °C  
I

D

=f(V

DS

);
T

C

= 125 °C  
Final Data Sheet  
7
Rev. 2.1  
2020-01-16  
 
 
 

IGLD60R070D1  
600V CoolGaN
™
enhancement-mode Power Transistor  
Figure 5  
Repetitive safe operating area

Figure 6  
Repetitive safe operating area

1  

70  
70  
60  
50  
40  
30  
20  
10  
0
60  
50  
40  
30  
20  
10  
0
tp ≤ 20ns  
Limited by  
R

DS(on)  

tp ≤ 20ns  
Limited by  
R

DS(on)  

0
100  
200  
300  
400  
500  
600  
0
100  
200  
300  
400  
500  
600  
V

DS

[V]  
V

DS

[V]  
Tc = 25 °C; T

j

≤ 150 °C  
Tc = 125 °C; T

j

≤ 150 °C  
Figure 7  
Typ. output characteristics  
Figure 8  
Typ. output characteristics  
90  
90  
I

G

=
26.1 mA  
I

G

=
10 mA  
80  
70  
60  
50  
40  
30  
20  
10  
0
80  
70  
60  
50  
40  
30  
20  
10  
0
I

G

=
2.6 mA  
I

G

=
1 mA  
I

G

=
26.1 mA  
I

G

=
10 mA  
I

G

=
0.26 mA  
I

G

=
0.1 mA  
I

G

=
2.6 mA  
I

G

=
1 mA  
I

G

=
0.26 mA  
I

G

=
0.1 mA  
0
2
4
6
8
10  
0
2
4
6
8
10  
V

DS

[V]  
V

DS

[V]  
I

D

=f(V

DS

,I

G

);
T

j

= 25 °C  
I

D

=f(V

DS

,I

G

);
T

j

= 125 °C  
1
Parameter is influenced by rel-requirements. Please contact the local Infineon Sales Office to get an assessment of your application.  
Final Data Sheet  
8
Rev. 2.1  
2020-01-16  
 
 
 

IGLD60R070D1  
600V CoolGaN
™
enhancement-mode Power Transistor  
Figure 9  
Typ. Drain-source on-state resistance  
Figure 10
 
Drain-source on-state resistance  
140  
120  
100  
80  
200  
180  
160  
140  
120  
100  
80  
I

G

=
0.26 mA  
I

G

=
0.1 mA  
I

G

=
1 mA  
I

G

=
10 mA  
V

GS

= 3 V  
60  
I

G

= 26.1 mA  
I

G

=
2.6 mA  
I

G

=
26.1 mA  
40  
20  
0
-50  
0
50  
100  
150  
0
10  
20  
30  
40  
50  
60  
T

j

[

o

C]  
I

D

[A]  
R

DS(on)

=f(I

D

,I

G

);
T

j

= 125 °C  
R

DS(on)

=f(T

j

);
I

D

= 8 A  
Figure 11
 
Typ. gate characteristics forward  
Figure 12
 
Typ. gate characteristics reverse  
V

GS

(V)  
500  
450  
400  
350  
-25  
-20  
-15  
-10  
-5  
0
0
-50  
-100  
-150  
-200  
-250  
-300  
-350  
300  
250  
200  
150  
100  
50  
125°C  
25°C  
-55°C  
0
0
0.5  
1
1.5  
2
2.5  
3
3.5  
4
4.5  
V

GS

(V)  
I

GS

=f(V

GS

,T

j

);
open drain  
I

GS

=f(V

GS

);
T

j

= 25 °C  
Final Data Sheet  
9
Rev. 2.1  
2020-01-16  

IGLD60R070D1  
600V CoolGaN
™
enhancement-mode Power Transistor  
Figure 13
 
Typ. transfer characteristics  
Figure 14
 
Typ. transfer characteristics  

I I
 
=f(V );
 
V

DS

= 8 V; T = 25 °C  
I I
 
=f(V );
 
V

DS

= 8 V ; T = 125 °C  
,
,
D
G
GS  
j
D
G
GS  
j
Figure 15
 
Typ. channel reverse characteristics  
Figure 16
 
Typ. channel reverse characteristics  
V

DS

(V)  
V

DS

(V)  
-8  
-7  
-6  
-5  
-4  
-3  
-2  
-1  
0
-8  
-6  
-4  
-2  
0
0
0
-1  
-2  
-3  
-4  
-5  
-6  
-7  
-8  
-9  
-10  
-1  
-2  
-3  
-4  
-5  
-6  
-7  
-8  
-9  
-10  
-5V  
–
3V  
-4V  
-2V  
-5V  
-1V  
0V  
-1V  
-4V  
–
3V  
-2V  
0V  
V

GS  

V

GS  

V

DS

=f(I

D

, V

GS

);
T

j

= 25 °C  
V

DS

=f(I

D

, V

GS

);
T

j

= 125 °C  
Final Data Sheet  
10  
Rev. 2.1  
2020-01-16  

IGLD60R070D1  
600V CoolGaN
™
enhancement-mode Power Transistor  
Figure 17
 
Typ. channel reverse characteristics  
Figure 18
 
Typ. channel reverse characteristics  
60  
60  
50  
40  
30  
20  
10  
0
+4V  
50  
40  
30  
20  
10  
0
0V  
+4V  
0V  
0
2
4
6
8
0
2
4
6
8
10  
V

SD

(V)  
V

SD

(V)  
I

D

=f(V

DS

, V

GS

);
T

j

= 25 °C  
I

D

=f(V

DS

, V

GS

);
T

j

= 125 °C  
Figure 19
 
Typ. gate charge  
Figure 20
 
Typ. capacitances  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
1,000.0  
Ciss  
Coss  
100.0  
10.0  
1.0  
Crss  
0.1  
0
100  
200  
300  
400  
500  
0
1
2
3
4
5
6
Q (nC)  
V

DS

(V)  
V

GS

= f(Q

G

);
V

DCLINK

= 400 V; I

D

= 8 A  
C

xSS

= f(V

DS

)  
Final Data Sheet  
11  
Rev. 2.1  
2020-01-16  

IGLD60R070D1  
600V CoolGaN
™
enhancement-mode Power Transistor  
Figure 21
 
Typ. output charge  
Figure 22
 
Typ. Coss stored Energy  
10  
9
8
7
6
5
4
3
2
1
0
50  
45  
40  
35  
30  
25  
20  
15  
10  
5
0
0
100  
200  
300  
V

DS

(V)  
400  
500  
0
100  
200  
300  
400  
500  
V

DS

(V)  
Q

OSS

= f(V

DS

)  
E

OSS

= f(V

DS

)  
Final Data Sheet  
12  
Rev. 2.1  
2020-01-16  

IGLD60R070D1  
600V CoolGaN
™
enhancement-mode Power Transistor  
5
Test Circuits  
Figure 23
 
Switching times with inductive load  
Figure 24
 
Switching times waveform  
D
R

SS  

C

G  

T1  
R

ON  

L
G
SK  
R

OFF  

+
S
D
I

D  

R

SS  

C

G  

T2  
R

ON  

t
G
SK  
R

OFF  

S
I

D

= 8A, R

ON

= 10
Ω
; R

OFF

= 10
Ω; R

SS

= 820 Ω; C

G

= 2 nF;  
V

DRV

= 12V  
Figure 25
 
Reverse Channel Characteristics Test  
Figure 26
 
Typical Reverse
 
Channel Recovery  
D
R

SS  

C

G  

T1  
R

ON  

L
G
SK  
R

OFF  

+
S
D
I

D  

R

SS  

C

G  

T2  
R

ON  

G
SK  
R

OFF  

S
I

D

= 8A, R

ON

= 10
Ω
; R

OFF

= 10
Ω; R

SS

= 820 Ω; C

G

= 2 nF;  
V

DRV

= 12V  
The recovery charge is Q

OSS

only, no additional Q

rr  

Figure 27
 
Gate current switching waveform  
I

G,pulse  

I

G  

I

G, avg  

t
Final Data Sheet  
13  
Rev. 2.1  
2020-01-16  
 
 

IGLD60R070D1  
600V CoolGaN
™
enhancement-mode Power Transistor  
6
Package Outlines  
Figure 28
 
PG-LSON-8-1 Package Outline, dimensions (mm)  
Final Data Sheet  
14  
Rev. 2.1  
2020-01-16  
 

IGLD60R070D1  
600V CoolGaN
™
enhancement-mode Power Transistor  
7
Appendix A  
Table 9  
Related links  
IFX CoolGaN

TM

webpage:

IFX CoolGaN

TM

reliability white paper:
 

IFX CoolGaN

TM

gate drive application note:
 

IFX CoolGaN

TM

applications information:  
o
o
o
o
Final Data Sheet  
15  
Rev. 2.1  
2020-01-16  
 

IGLD60R070D1  
600V CoolGaN
™
enhancement-mode Power Transistor  
8
Revision History  
Major changes since the last revision  
Revision Date
 
Description of
 
changes  
2.0  
2.1  
2018-10-12  
2020-01-16  
Final version release  
Added V

DS,bd

, V

DS,pulse

, V

DS,surge

specifications in maximum ratings table of page3  
Final Data Sheet  
16  
Rev. 2.1  
2020-01-16  
 

Trademarks of Infineon Technologies AG  
µHVIC
™
, µIPM
™
, µPFC
™
, AU-ConvertIR
™
, AURIX
™
, C166
™
, CanPAK
™
, CIPOS
™
, CIPURSE
™
, CoolDP
™
, CoolGaN
™
, COOLiR
™
, CoolMOS
™
, CoolSET
™
, CoolSiC
™
,  
DAVE
™
, DI-POL
™
, DirectFET
™
, DrBlade
™
, EasyPIM
™
, EconoBRIDGE
™
, EconoDUAL
™
, EconoPACK
™
, EconoPIM
™
, EiceDRIVER
™
, eupec
™
, FCOS
™
, GaNpowIR
™
,  
HEXFET
™
, HITFET
™
, HybridPACK
™
, iMOTION
™
, IRAM
™
, ISOFACE
™
, IsoPACK
™
, LEDrivIR
™
, LITIX
™
, MIPAQ
™
, ModSTACK
™
, my-d
™
, NovalithIC
™
, OPTIGA
™
,  
OptiMOS
™
, ORIGA
™
, PowIRaudio
™
, PowIRStage
™
, PrimePACK
™
, PrimeSTACK
™
, PROFET
™
, PRO-SIL
™
, RASIC
™
, REAL3
™
, SmartLEWIS
™
, SOLID FLASH
™
,  
SPOC
™
, StrongIRFET
™
, SupIRBuck
™
, TEMPFET
™
, TRENCHSTOP
™
, TriCore
™
, UHVIC
™
, XHP
™
, XMC
™  
Trademarks updated November 2015  
Other Trademarks  
All referenced product or service names and trademarks are the property of their respective owners.  
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For further information on the product, technology,  
Edition 2020-01-16  
event be regarded as a guarantee of conditions or
 
delivery terms and conditions and prices please  
Published by  
characteristics (“Beschaffenheitsgarantie”)
 
.  
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ifx1  
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