Infineon-Technologies-IPA040N08NM5S
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IPA040N08NM5S
MOSFET
OptiMOS
TMꢀ
5ꢀPower-Transistor,ꢀ80ꢀV
PG-TOꢀ220ꢀFP
Features
•ꢀIdealꢀforꢀhighꢀfrequencyꢀswitchingꢀandꢀsync.ꢀrec.
•ꢀExcellentꢀgateꢀchargeꢀxꢀ
R
DS(on)
ꢀproductꢀ(FOM)
•ꢀVeryꢀlowꢀon-resistanceꢀꢀR
DS(on)
•ꢀN-channel,ꢀnormalꢀlevel
•ꢀ100%ꢀavalancheꢀtested
•ꢀPb-freeꢀplating;ꢀRoHSꢀcompliant
•ꢀHalogen-freeꢀaccordingꢀtoꢀIEC61249-2-21
Productꢀvalidation
QualifiedꢀaccordingꢀtoꢀJEDECꢀStandard
Drain
Pin 2
Tableꢀ1ꢀꢀꢀꢀꢀKeyꢀPerformanceꢀParameters
Gate
Pin 1
Parameter
Value
Unit
Source
Pin 3
V
DS
80
V
R
DS(on),max
I
D
4.0
75
m
Ω
A
Q
oss
83
nC
nC
Q
G
(0V..10V)
70
Typeꢀ/ꢀOrderingꢀCode
Package
PG-TO 220 FullPAK
Marking
RelatedꢀLinks
IPA040N08NM5S
040N085S
–
Final Data Sheet
1
Rev.ꢀ2.1,ꢀꢀ2019-09-02
OptiMOS
TMꢀ
5ꢀPower-Transistor,ꢀ80ꢀV
IPA040N08NM5S
TableꢀofꢀContents
Description .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Maximum ratings
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
Thermal characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
Electrical characteristics diagrams
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
Package Outlines
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision History
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
Trademarks .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
Disclaimer .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
Final Data Sheet
2
Rev.ꢀ2.1,ꢀꢀ2019-09-02
OptiMOS
TMꢀ
5ꢀPower-Transistor,ꢀ80ꢀV
IPA040N08NM5S
1ꢀꢀꢀꢀꢀMaximumꢀratings
atꢀ
T
A
=25ꢀ°C,ꢀunlessꢀotherwiseꢀspecified
Tableꢀ2ꢀꢀꢀꢀꢀMaximumꢀratings
Values
Typ.
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Max.
–
–
–
–
75
53
V
GS
=10ꢀV,ꢀ
T
C
=25ꢀ°C
V
GS
=10ꢀV,ꢀ
T
C
=100ꢀ°C
Continuous drain current
I
D
A
Pulsed drain current
1)
Avalanche energy, single pulse
2)
Gate source voltage
I
D,pulse
E
AS
–
–
–
–
–
300
186
20
A
T
C
=25ꢀ°C
–
mJ
V
I
D
=75ꢀA,ꢀ
R
GS
=25ꢀ
Ω
V
GS
P
tot
-20
–
–
Power dissipation
39
W
T
C
=25ꢀ°C
IEC climatic category; DIN IEC 68-1:
55/175/56
Operating and storage temperature
T
j
,ꢀ
T
stg
-55
–
175
°C
2ꢀꢀꢀꢀꢀThermalꢀcharacteristics
Tableꢀ3ꢀꢀꢀꢀꢀThermalꢀcharacteristics
Values
Typ.
–
Parameter
Symbol
R
thJC
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Max.
Thermal resistance, junction – case
–
3.8
°C/W –
3ꢀꢀꢀꢀꢀElectricalꢀcharacteristics
atꢀ
T
j
=25ꢀ°C,ꢀunlessꢀotherwiseꢀspecified
Tableꢀ4ꢀꢀꢀꢀꢀStaticꢀcharacteristics
Values
Typ.
–
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
80
Max.
–
Drain-source breakdown voltage
Gate threshold voltage
V
(BR)DSS
V
GS(th)
V
V
V
GS
=0ꢀV,ꢀ
I
D
=1ꢀmA
2.2
3.0
3.8
V
DS
=
V
GS
,ꢀ
I
D
=109ꢀµA
–
–
0.1
10
1
100
V
DS
=80ꢀV,ꢀ
V
GS
=0ꢀV,ꢀ
T
j
=25ꢀ°C
V
DS
=80ꢀV,ꢀ
V
GS
=0ꢀV,ꢀ
T
j
=125ꢀ°C
Zero gate voltage drain current
Gate-source leakage current
Drain-source on-state resistance
I
DSS
µA
nA
I
GSS
–
1
100
V
GS
=20ꢀV,ꢀ
V
DS
=0ꢀV
–
–
3.4
4.2
4.0
–
V
GS
=10ꢀV,ꢀ
I
D
=38ꢀA
V
GS
=6ꢀV,ꢀ
I
D
=19ꢀA
R
DS(on)
m
Ω
Gate resistance
3)
Transconductance
R
G
g
fs
–
–
1.5
93
–
–
Ω
–
S
|
V
DS
|
≥
2|
I
D
|
R
DS(on)max
,ꢀ
I
D
=38ꢀA
1)
See Diagram 3 for more detailed information
2)
See Diagram 13 for more detailed information
3)
Defined by design. Not subject to production test.
Final Data Sheet
3
Rev.ꢀ2.1,ꢀꢀ2019-09-02
OptiMOS
TMꢀ
5ꢀPower-Transistor,ꢀ80ꢀV
IPA040N08NM5S
Tableꢀ5ꢀꢀꢀꢀꢀDynamicꢀcharacteristics
Values
Typ.
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Max.
Input capacitance
1)
C
iss
C
oss
C
rss
–
–
–
4900 6400 pF
V
GS
=0ꢀV,ꢀ
V
DS
=40ꢀV,ꢀ
f
=1ꢀMHz
V
GS
=0ꢀV,ꢀ
V
DS
=40ꢀV,ꢀ
f
=1ꢀMHz
V
GS
=0ꢀV,ꢀ
V
DS
=40ꢀV,ꢀ
f
=1ꢀMHz
Output capacitance
790
36
–
–
pF
pF
Reverse transfer capacitance
V
DD
=40ꢀV,ꢀ
V
GS
=10ꢀV,ꢀ
I
D
=38ꢀA,
R
G,ext
=1.6ꢀ
Ω
Turn-on delay time
Rise time
t
d(on)
t
r
t
d(off)
t
f
–
–
–
–
18
12
37
12
–
–
–
–
ns
ns
ns
ns
V
DD
=40ꢀV,ꢀ
V
GS
=10ꢀV,ꢀ
I
D
=38ꢀA,
R
G,ext
=1.6ꢀ
Ω
V
DD
=40ꢀV,ꢀ
V
GS
=10ꢀV,ꢀ
I
D
=38ꢀA,
R
G,ext
=1.6ꢀ
Ω
Turn-off delay time
Fall time
V
DD
=40ꢀV,ꢀ
V
GS
=10ꢀV,ꢀ
I
D
=38ꢀA,
R
G,ext
=1.6ꢀ
Ω
Tableꢀ6ꢀꢀꢀꢀꢀGateꢀchargeꢀcharacteristics
2)
ꢀ
Values
Typ.
22
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Max.
Gate to source charge
Gate charge at threshold
Gate to drain charge
Switching charge
Q
gs
–
–
–
–
–
–
–
–
–
nC
nC
nC
nC
nC
V
V
DD
=40ꢀV,ꢀ
I
D
=38ꢀA,ꢀ
V
GS
=0ꢀtoꢀ10ꢀV
V
DD
=40ꢀV,ꢀ
I
D
=38ꢀA,ꢀ
V
GS
=0ꢀtoꢀ10ꢀV
V
DD
=40ꢀV,ꢀ
I
D
=38ꢀA,ꢀ
V
GS
=0ꢀtoꢀ10ꢀV
V
DD
=40ꢀV,ꢀ
I
D
=38ꢀA,ꢀ
V
GS
=0ꢀtoꢀ10ꢀV
V
DD
=40ꢀV,ꢀ
I
D
=38ꢀA,ꢀ
V
GS
=0ꢀtoꢀ10ꢀV
V
DD
=40ꢀV,ꢀ
I
D
=38ꢀA,ꢀ
V
GS
=0ꢀtoꢀ10ꢀV
V
DS
=0.1ꢀV,ꢀ
V
GS
=0ꢀtoꢀ10ꢀV
Q
g(th)
Q
gd
15
–
15
–
Q
sw
22
–
Gate charge total
1)
Q
g
70
93
–
Gate plateau voltage
Gate charge total, sync. FET
Output charge
V
plateau
Q
g(sync)
Q
oss
4.5
60
–
nC
nC
83
–
V
DD
=40ꢀV,ꢀ
V
GS
=0ꢀV
Tableꢀ7ꢀꢀꢀꢀꢀReverseꢀdiode
Values
Typ.
–
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Max.
33
300
1.2
–
Diode continuous forward current
Diode pulse current
I
S
–
–
–
–
–
A
T
C
=25ꢀ°C
I
S,pulse
V
SD
t
rr
–
A
T
C
=25ꢀ°C
Diode forward voltage
0.87
73
V
V
GS
=0ꢀV,ꢀ
I
F
=38ꢀA,ꢀ
T
j
=25ꢀ°C
V
R
=40ꢀV,ꢀ
I
F
=38ꢀA,ꢀd
i
F
/d
t
=100ꢀA/µs
V
R
=40ꢀV,ꢀ
I
F
=38ꢀA,ꢀd
i
F
/d
t
=100ꢀA/µs
Reverse recovery time
1)
Reverse recovery charge
1)
ns
nC
Q
rr
166
–
1)
Defined by design. Not subject to production test.
2)
See
″
Gate charge waveforms
″
for parameter definition
Final Data Sheet
4
Rev.ꢀ2.1,ꢀꢀ2019-09-02
OptiMOS
TMꢀ
5ꢀPower-Transistor,ꢀ80ꢀV
IPA040N08NM5S
4ꢀꢀꢀꢀꢀElectricalꢀcharacteristicsꢀdiagrams
Diagramꢀ1:ꢀPowerꢀdissipation
Diagramꢀ2:ꢀDrainꢀcurrent
40
80
35
30
25
20
15
10
5
70
60
50
40
30
20
10
0
0
0
25
50
75
100
125
150
175
200
0
25
50
75
100
125
150
175
200
T
C
ꢀ[°C]
T
C
ꢀ[°C]
P
tot
=f(
T
C
)
I
D
=f(
T
C
);ꢀ
V
GS
≥
10ꢀV
Diagramꢀ3:ꢀSafeꢀoperatingꢀarea
Diagramꢀ4:ꢀMax.ꢀtransientꢀthermalꢀimpedance
10
3
10
1
single pulse
0.01
0.02
1 µs
10
2
10
1
0.05
0.1
0.2
0.5
10 µs
100 µs
1 ms
10 ms
10
0
10
-1
10
-2
10
0
DC
10
-1
10
-2
10
-3
10
-1
10
0
10
1
10
2
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
V
DS
ꢀ[V]
t
p
ꢀ[s]
I
D
=f(
V
DS
);ꢀ
T
C
=25ꢀ°C;ꢀ
D
=0;ꢀparameter:ꢀ
t
p
Z
thJC
=f(
t
p
);ꢀparameter:ꢀ
D
=
t
p
/
T
Final Data Sheet
5
Rev.ꢀ2.1,ꢀꢀ2019-09-02
OptiMOS
TMꢀ
5ꢀPower-Transistor,ꢀ80ꢀV
IPA040N08NM5S
Diagramꢀ5:ꢀTyp.ꢀoutputꢀcharacteristics
Diagramꢀ6:ꢀTyp.ꢀdrain-sourceꢀonꢀresistance
300
10 V
8 V
12
7 V
6 V
4.5 V
250
200
150
100
50
10
5 V
8
6
6 V
7 V
4
2
0
8 V
10 V
5 V
4.5 V
0
0
1
2
3
4
5
0
25
50
75
100
125
150
V
DS
ꢀ[V]
I
D
ꢀ[A]
I
D
=f(
V
DS
),ꢀ
T
j
=25ꢀ°C;ꢀparameter:ꢀ
V
GS
R
DS(on)
=f(
I
D
),ꢀ
T
j
=25ꢀ°C;ꢀparameter:ꢀ
V
GS
Diagramꢀ7:ꢀTyp.ꢀtransferꢀcharacteristics
Diagramꢀ8:ꢀTyp.ꢀdrain-sourceꢀonꢀresistance
300
12
250
200
150
100
10
8
175 °C
6
4
25 °C
50
2
175 °C
25 °C
0
0
0
1
2
3
4
5
6
7
0
2
4
6
8
10
V
GS
ꢀ[V]
V
GS
ꢀ[V]
I
D
=f(
V
GS
),ꢀ|
V
DS
|>2|
I
D
|
R
DS(on)max
;ꢀparameter:ꢀ
T
j
R
DS(on)
=f(
V
GS
),ꢀ
I
D
=38ꢀA;ꢀparameter:ꢀ
T
j
Final Data Sheet
6
Rev.ꢀ2.1,ꢀꢀ2019-09-02
OptiMOS
TMꢀ
5ꢀPower-Transistor,ꢀ80ꢀV
IPA040N08NM5S
Diagramꢀ9:ꢀNormalizedꢀdrain-sourceꢀonꢀresistance
Diagramꢀ10:ꢀTyp.ꢀgateꢀthresholdꢀvoltage
2.0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.6
1.2
0.8
0.4
0.0
1090 µA
109 µA
-80
-40
0
40
80
120
160
200
-80
-40
0
40
80
120
160
200
T
j
ꢀ[°C]
T
j
ꢀ[°C]
R
DS(on)
=f(
T
j
),ꢀ
I
D
=38ꢀA,ꢀ
V
GS
=10ꢀV
V
GS(th
=f(
T
j
),ꢀ
V
GS
=
V
DS
;ꢀparameter:ꢀ
I
D
Diagramꢀ11:ꢀTyp.ꢀcapacitances
Diagramꢀ12:ꢀForwardꢀcharacteristicsꢀofꢀreverseꢀdiode
10
4
10
3
25 °C
25 °C, max
175 °C
Ciss
175 °C, max
10
3
10
2
10
1
10
2
10
1
10
0
Coss
Crss
0
10
20
30
40
50
60
70
80
0.00
0.25
0.50
0.75
1.00
1.25
1.50
V
DS
ꢀ[V]
V
SD
ꢀ[V]
C
=f(
V
DS
);ꢀ
V
GS
=0ꢀV;ꢀ
f
=1ꢀMHz
I
F
=f(
V
SD
);ꢀparameter:ꢀ
T
j
Final Data Sheet
7
Rev.ꢀ2.1,ꢀꢀ2019-09-02
OptiMOS
TMꢀ
5ꢀPower-Transistor,ꢀ80ꢀV
IPA040N08NM5S
Diagramꢀ13:ꢀAvalancheꢀcharacteristics
Diagramꢀ14:ꢀTyp.ꢀgateꢀcharge
10
2
10
16 V
40 V
64 V
25 °C
8
6
4
2
0
10
1
100 °C
150 °C
10
0
10
-1
10
0
10
1
10
2
10
3
0
10
20
30
40
50
60
70
80
t
AV
ꢀ[µs]
Q
gate
ꢀ[nC]
I
AS
=f(
t
AV
);ꢀ
R
GS
=25ꢀ
Ω
;ꢀparameter:ꢀ
T
j,start
V
GS
=f(
Q
gate
),ꢀ
I
D
=38ꢀAꢀpulsed,ꢀ
T
j
=25ꢀ°C;ꢀparameter:ꢀ
V
DD
Diagramꢀ15:ꢀDrain-sourceꢀbreakdownꢀvoltage
Diagram Gate charge waveforms
88
86
84
82
80
78
76
-80
-40
0
40
80
120
160
200
T
j
ꢀ[°C]
V
BR(DSS)
=f(
T
j
);ꢀ
I
D
=1ꢀmA
Final Data Sheet
8
Rev.ꢀ2.1,ꢀꢀ2019-09-02
OptiMOS
TMꢀ
5ꢀPower-Transistor,ꢀ80ꢀV
IPA040N08NM5S
5ꢀꢀꢀꢀꢀPackageꢀOutlines
1
2
3
MILLIMETERS
MIN.
DIMENSIONS
MAX.
4.90
2.80
2.86
0.90
1.38
1.50
1.38
1.50
0.63
16.15
9.83
10.65
DOCUMENT NO.
Z8B00181328
A
A1
A2
b
4.50
2.34
2.42
0.65
0.95
1.20
0.65
1.20
0.40
15.67
8.97
10.00
REVISION
03
b1
b2
b3
b4
c
ISSUE DATE
23.07.2018
SCALE 5:1
0
1
2
3
4
5mm
D
D1
E
e
2.54
EUROPEAN PROJECTION
H
28.70
12.78
2.83
29.75
13.75
3.45
L
L1
øP
Q
3.00
3.38
3.15
3.50
Figureꢀ1ꢀꢀꢀꢀꢀOutlineꢀPG-TOꢀ220ꢀFullPAK,ꢀdimensionsꢀinꢀmm/inches
Final Data Sheet
9
Rev.ꢀ2.1,ꢀꢀ2019-09-02
OptiMOS
TMꢀ
5ꢀPower-Transistor,ꢀ80ꢀV
IPA040N08NM5S
RevisionꢀHistory
IPA040N08NM5S
Revision:ꢀ2019-09-02,ꢀRev.ꢀ2.1
Previous Revision
Revision Date
Subjects (major changes since last revision)
2.0
2.1
Release of final version
Update package outline
2019-07-23
2019-09-02
Trademarks
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©ꢀ2019ꢀInfineonꢀTechnologiesꢀAG
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LegalꢀDisclaimer
Theꢀinformationꢀgivenꢀinꢀthisꢀdocumentꢀshallꢀinꢀnoꢀeventꢀbeꢀregardedꢀasꢀaꢀguaranteeꢀofꢀconditionsꢀorꢀcharacteristicsꢀ
(“Beschaffenheitsgarantie”)ꢀ.
Withꢀrespectꢀtoꢀanyꢀexamples,ꢀhintsꢀorꢀanyꢀtypicalꢀvaluesꢀstatedꢀhereinꢀand/orꢀanyꢀinformationꢀregardingꢀtheꢀapplicationꢀofꢀthe
product,ꢀInfineonꢀTechnologiesꢀherebyꢀdisclaimsꢀanyꢀandꢀallꢀwarrantiesꢀandꢀliabilitiesꢀofꢀanyꢀkind,ꢀincludingꢀwithoutꢀlimitation
warrantiesꢀofꢀnon-infringementꢀofꢀintellectualꢀpropertyꢀrightsꢀofꢀanyꢀthirdꢀparty.
Inꢀaddition,ꢀanyꢀinformationꢀgivenꢀinꢀthisꢀdocumentꢀisꢀsubjectꢀtoꢀcustomer’sꢀcomplianceꢀwithꢀitsꢀobligationsꢀstatedꢀinꢀthis
documentꢀandꢀanyꢀapplicableꢀlegalꢀrequirements,ꢀnormsꢀandꢀstandardsꢀconcerningꢀcustomer’sꢀproductsꢀandꢀanyꢀuseꢀofꢀthe
productꢀofꢀInfineonꢀTechnologiesꢀinꢀcustomer’sꢀapplications.
Theꢀdataꢀcontainedꢀinꢀthisꢀdocumentꢀisꢀexclusivelyꢀintendedꢀforꢀtechnicallyꢀtrainedꢀstaff.ꢀItꢀisꢀtheꢀresponsibilityꢀofꢀcustomer’s
technicalꢀdepartmentsꢀtoꢀevaluateꢀtheꢀsuitabilityꢀofꢀtheꢀproductꢀforꢀtheꢀintendedꢀapplicationꢀandꢀtheꢀcompletenessꢀofꢀtheꢀproduct
informationꢀgivenꢀinꢀthisꢀdocumentꢀwithꢀrespectꢀtoꢀsuchꢀapplication.
Information
Forꢀfurtherꢀinformationꢀonꢀtechnology,ꢀdeliveryꢀtermsꢀandꢀconditionsꢀandꢀpricesꢀpleaseꢀcontactꢀyourꢀnearestꢀInfineon
Warnings
Dueꢀtoꢀtechnicalꢀrequirements,ꢀcomponentsꢀmayꢀcontainꢀdangerousꢀsubstances.ꢀForꢀinformationꢀonꢀtheꢀtypesꢀinꢀquestion,
pleaseꢀcontactꢀtheꢀnearestꢀInfineonꢀTechnologiesꢀOffice.
TheꢀInfineonꢀTechnologiesꢀcomponentꢀdescribedꢀinꢀthisꢀDataꢀSheetꢀmayꢀbeꢀusedꢀinꢀlife-supportꢀdevicesꢀorꢀsystemsꢀand/or
automotive,ꢀaviationꢀandꢀaerospaceꢀapplicationsꢀorꢀsystemsꢀonlyꢀwithꢀtheꢀexpressꢀwrittenꢀapprovalꢀofꢀInfineonꢀTechnologies,ꢀifꢀa
failureꢀofꢀsuchꢀcomponentsꢀcanꢀreasonablyꢀbeꢀexpectedꢀtoꢀcauseꢀtheꢀfailureꢀofꢀthatꢀlife-support,ꢀautomotive,ꢀaviationꢀand
aerospaceꢀdeviceꢀorꢀsystemꢀorꢀtoꢀaffectꢀtheꢀsafetyꢀorꢀeffectivenessꢀofꢀthatꢀdeviceꢀorꢀsystem.ꢀLifeꢀsupportꢀdevicesꢀorꢀsystemsꢀare
intendedꢀtoꢀbeꢀimplantedꢀinꢀtheꢀhumanꢀbodyꢀorꢀtoꢀsupportꢀand/orꢀmaintainꢀandꢀsustainꢀand/orꢀprotectꢀhumanꢀlife.ꢀIfꢀtheyꢀfail,ꢀitꢀis
reasonableꢀtoꢀassumeꢀthatꢀtheꢀhealthꢀofꢀtheꢀuserꢀorꢀotherꢀpersonsꢀmayꢀbeꢀendangered.
Final Data Sheet
10
Rev.ꢀ2.1,ꢀꢀ2019-09-02
