Infineon-Technologies-IPB015N08N5

Part #Infineon-Technologies-IPB015N08N5
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Infineon-Technologies-IPB015N08N5
MOSFET  
MetalꢀOxideꢀSemiconductorꢀFieldꢀEffectꢀTransistor  
OptiMOS

TM  

OptiMOS

™

ꢀꢀ5ꢀPower-Transistor,ꢀ80ꢀV  
IPB015N08N5  
DataꢀSheet  
Rev.ꢀ2.1  
Final  
PowerꢀManagementꢀ&ꢀMultimarket  

OptiMOS

ª

ꢀꢀ5ꢀPower-Transistor,ꢀ80ꢀV  
IPB015N08N5  
D²-PAKꢀ7pin  
1ꢀꢀꢀꢀꢀDescription  
Features  
•ꢀIdealꢀforꢀhighꢀfrequencyꢀswitchingꢀandꢀsync.ꢀrec.  
•ꢀOptimizedꢀtechnologyꢀforꢀDC/DCꢀconverters  
•ꢀExcellentꢀgateꢀchargeꢀxꢀ
R

DS(on)

ꢀproductꢀ(FOM)  
•ꢀVeryꢀlowꢀon-resistanceꢀꢀR

DS(on)  

tab  
1
•ꢀN-channel,ꢀnormalꢀlevel  
•ꢀ100%ꢀavalancheꢀtested  
7
•ꢀPb-freeꢀplating;ꢀRoHSꢀcompliant  
•ꢀQualifiedꢀaccordingꢀtoꢀJEDEC

1)

ꢀꢀforꢀtargetꢀapplications  
•ꢀHalogen-freeꢀaccordingꢀtoꢀIEC61249-2-21  
Drain  
Pin 4, tab  
Tableꢀ1ꢀꢀꢀꢀꢀKeyꢀPerformanceꢀParameters  
Parameter  
Value  
Unit  
Gate  
Pin 1  
V

DS  

80  
V
Source  
Pin 2,3,5,6,7  
R

DS(on),max  

I

D  

1.5  
m
Ω
 
A
180  
207  
178  
Q

oss  

nC  
nC  
Q

G

(0V..10V)  
Typeꢀ/ꢀOrderingꢀCode  
Package  
Marking  
RelatedꢀLinks  
IPB015N08N5  
PG-TO263-7  
015N08N5  
–

1)

J-STD20 and JESD22  
Final Data Sheet  
2
Rev.ꢀ2.1,ꢀꢀ2015-10-15  

OptiMOS

ª

ꢀꢀ5ꢀPower-Transistor,ꢀ80ꢀV  
IPB015N08N5  
TableꢀofꢀContents  
Description .
 
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Maximum ratings
 
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4  
Thermal characteristics
 
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Electrical characteristics
 
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
 
5  
Electrical characteristics diagrams
 
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
 
7  
Package Outlines
 
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
 
11  
Revision History
 
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
 
12  
Disclaimer .
 
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
 
12  
Final Data Sheet  
3
Rev.ꢀ2.1,ꢀꢀ2015-10-15  

OptiMOS

ª

ꢀꢀ5ꢀPower-Transistor,ꢀ80ꢀV  
IPB015N08N5  
2ꢀꢀꢀꢀꢀMaximumꢀratings  
atꢀ
T

A

=25ꢀ°C,ꢀunlessꢀotherwiseꢀspecified  
Tableꢀ2ꢀꢀꢀꢀꢀMaximumꢀratings  
Values  
Parameter  
Symbol  
Unit Noteꢀ/ꢀTestꢀCondition  
Min.  
Typ.  
Max.  
–
–
–
–
180  
180  
T

C

=25ꢀ°C  
A
Continuous drain current  
I

D  

T

C

=100ꢀ°C  
Pulsed drain current

1)  

Avalanche energy, single pulse

2)  

Gate source voltage  
I

D,pulse  

E

AS  

–
–
–
–
–
720  
A
T

C

=25ꢀ°C  
–
1230 mJ  
I

D

=100ꢀA,ꢀ
R

GS

=25ꢀ
Ω  
V

GS  

P

tot  

-20  
–
20  
V
–
Power dissipation  
375  
W
T

C

=25ꢀ°C  
IEC climatic category;  
DIN IEC 68-1: 55/175/56  
Operating and storage temperature  
T

j

,ꢀ
T

stg  

-55  
–
175  
°C  
3ꢀꢀꢀꢀꢀThermalꢀcharacteristics  
Tableꢀ3ꢀꢀꢀꢀꢀThermalꢀcharacteristics  
Values  
Typ.  
0.3  
Parameter  
Symbol  
Unit Noteꢀ/ꢀTestꢀCondition  
Min.  
Max.  
Thermal resistance, junction – case  
R

thJC  

R

thJA  

–
0.4  
K/W  
K/W  
–
–
Thermal resistance, junction – ambient,  
minimal footprint  
–
–
–
–
–
–
62  
Thermal resistance, junction – ambient,  
6 cm

2

cooling area

3)  

R

thJA  

T

sold  

40  
K/W  
°C  
–
Soldering temperature and reflow  
soldering is allowed  
260  
Reflow MSL1  

1)

See Diagram 3 for more detailed information  

2)

See Diagram 13 for more detailed information  

3)

Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm

2

(one layer, 70 µm thick) copper area for drain connection.  
PCB is vertical in still air.  
Final Data Sheet  
4
Rev.ꢀ2.1,ꢀꢀ2015-10-15  

OptiMOS

ª

ꢀꢀ5ꢀPower-Transistor,ꢀ80ꢀV  
IPB015N08N5  
4ꢀꢀꢀꢀꢀElectricalꢀcharacteristics  
Tableꢀ4ꢀꢀꢀꢀꢀStaticꢀcharacteristics  
Values  
Parameter  
Symbol  
Unit Noteꢀ/ꢀTestꢀCondition  
Min.  
80  
Typ.  
Max.  
–
Drain-source breakdown voltage  
Gate threshold voltage  
V

(BR)DSS  

V

GS(th)  

–
V
V
V

GS

=0ꢀV,ꢀ
I

D

=1ꢀmA  
2.2  
3
3.8  
V

DS

=
V

GS

,ꢀ
I

D

=279ꢀµA  
–
–
0.1  
10  
1
100  
V

DS

=80ꢀV,ꢀ
V

GS

=0ꢀV,ꢀ
T

j

=25ꢀ°C  
V

DS

=80ꢀV,ꢀ
V

GS

=0ꢀV,ꢀ
T

j

=125ꢀ°C  
Zero gate voltage drain current  
Gate-source leakage current  
Drain-source on-state resistance  
I

DSS  

µA  
nA  
I

GSS  

–
1
100  
V

GS

=20ꢀV,ꢀ
V

DS

=0ꢀV  
–
–
1.1  
1.5  
1.5  
1.8  
V

GS

=10ꢀV,ꢀ
I

D

=100ꢀA  
V

GS

=6ꢀV,ꢀ
I

D

=50ꢀA  
R

DS(on)  

m
Ω  
Gate resistance

1)  

Transconductance  
R

G  

g

fs  

–
1.5  
2.3  
–
Ω
–
123  
245  
S
|
V

DS

|>2|
I

D

|
R

DS(on)max

,ꢀ
I

D

=100ꢀA  
Tableꢀ5ꢀꢀꢀꢀꢀDynamicꢀcharacteristics

1)

ꢀ  
Values  
Typ.  
Parameter  
Symbol  
Unit Noteꢀ/ꢀTestꢀCondition  
Min.  
Max.  
Input capacitance  
C

iss  

C

oss  

C

rss  

–
–
–
13000 16900 pF  
2000 2600 pF  
V

GS

=0ꢀV,ꢀ
V

DS

=40ꢀV,ꢀ
f
=1ꢀMHz  
V

GS

=0ꢀV,ꢀ
V

DS

=40ꢀV,ꢀ
f
=1ꢀMHz  
V

GS

=0ꢀV,ꢀ
V

DS

=40ꢀV,ꢀ
f
=1ꢀMHz  
Output capacitance  
Reverse transfer capacitance  
86  
33  
150  
–
pF  
ns  
V

DD

=40ꢀV,ꢀ
V

GS

=10ꢀV,ꢀ
I

D

=100ꢀA,  
R

G,ext

=1.6ꢀ
Ω  
Turn-on delay time  
Rise time  
t

d(on)  

t

r  

t

d(off)  

t

f  

–
–
–
–
V

DD

=40ꢀV,ꢀ
V

GS

=10ꢀV,ꢀ
I

D

=100ꢀA,  
R

G,ext

=1.6ꢀ
Ω  
32  
83  
28  
–
–
–
ns  
ns  
ns  
V

DD

=40ꢀV,ꢀ
V

GS

=10ꢀV,ꢀ
I

D

=100ꢀA,  
R

G,ext

=1.6ꢀ
Ω  
Turn-off delay time  
Fall time  
V

DD

=40ꢀV,ꢀ
V

GS

=10ꢀV,ꢀ
I

D

=100ꢀA,  
R

G,ext

=1.6ꢀ
Ω  
Tableꢀ6ꢀꢀꢀꢀꢀGateꢀchargeꢀcharacteristics

2)

ꢀ  
Values  
Typ.  
56  
Parameter  
Symbol  
Unit Noteꢀ/ꢀTestꢀCondition  
Min.  
Max.  
Gate to source charge  
Gate to drain charge

1)  

Switching charge  
Q

gs  

–
–
–
–
–
–
–
–
nC  
nC  
nC  
nC  
V
V

DD

=40ꢀV,ꢀ
I

D

=100ꢀA,ꢀ
V

GS

=0ꢀtoꢀ10ꢀV  
V

DD

=40ꢀV,ꢀ
I

D

=100ꢀA,ꢀ
V

GS

=0ꢀtoꢀ10ꢀV  
V

DD

=40ꢀV,ꢀ
I

D

=100ꢀA,ꢀ
V

GS

=0ꢀtoꢀ10ꢀV  
V

DD

=40ꢀV,ꢀ
I

D

=100ꢀA,ꢀ
V

GS

=0ꢀtoꢀ10ꢀV  
V

DD

=40ꢀV,ꢀ
I

D

=100ꢀA,ꢀ
V

GS

=0ꢀtoꢀ10ꢀV  
V

DS

=0.1ꢀV,ꢀ
V

GS

=0ꢀtoꢀ10ꢀV  
Q

gd  

37  
56  
Q

sw  

58  
–
Gate charge total

1)  

Q

g  

178  
4.5  
222  
Gate plateau voltage  
Gate charge total, sync. FET  
Output charge

1)  

V

plateau  

Q

g(sync)  

Q

oss  

–
153  
207  
–
nC  
nC  
276  
V

DD

=40ꢀV,ꢀ
V

GS

=0ꢀV  

1)

Defined by design. Not subject to production test.  

2)

See
″
Gate charge waveforms
″
for parameter definition  
Final Data Sheet  
5
Rev.ꢀ2.1,ꢀꢀ2015-10-15  

OptiMOS

ª

ꢀꢀ5ꢀPower-Transistor,ꢀ80ꢀV  
IPB015N08N5  
Tableꢀ7ꢀꢀꢀꢀꢀReverseꢀdiode  
Values  
Parameter  
Symbol  
Unit Noteꢀ/ꢀTestꢀCondition  
Min.  
Typ.  
–
Max.  
180  
720  
1.2  
Diode continous forward current  
Diode pulse current  
I

S  

–
–
–
–
–
A
T

C

=25ꢀ°C  
I

S,pulse  

V

SD  

t

rr  

–
A
T

C

=25ꢀ°C  
Diode forward voltage  
0.86  
94  
V
V

GS

=0ꢀV,ꢀ
I

F

=100ꢀA,ꢀ
T

j

=25ꢀ°C  
V

R

=40ꢀV,ꢀ
I

F

=100ꢀA,ꢀd
i

F

/d
t
=100ꢀA/µs  
V

R

=40ꢀV,ꢀ
I

F

=100ꢀA,ꢀd
i

F

/d
t
=100ꢀA/µs  
Reverse recovery time

1)  

Reverse recovery charge

1)  

188  
492  
ns  
nC  
Q

rr  

246  

1)

Defined by design. Not subject to production test.  
Final Data Sheet  
6
Rev.ꢀ2.1,ꢀꢀ2015-10-15  

OptiMOS

ª

ꢀꢀ5ꢀPower-Transistor,ꢀ80ꢀV  
IPB015N08N5  
5ꢀꢀꢀꢀꢀElectricalꢀcharacteristicsꢀdiagrams  
Diagramꢀ1:ꢀPowerꢀdissipation  
Diagramꢀ2:ꢀDrainꢀcurrent  
400  
200  
180  
160  
140  
120  
100  
80  
350  
300  
250  
200  
150  
100  
50  
60  
40  
20  
0
0
0
50  
100  
150  
200  
0
50  
100  
150  
200  
T

C

ꢀ[°C]  
T

C

ꢀ[°C]  
P

tot

=f(
T

C

)  
I

D

=f(
T

C

);ꢀ
V

GS

≥
10ꢀV  
Diagramꢀ3:ꢀSafeꢀoperatingꢀarea  
Diagramꢀ4:ꢀMax.ꢀtransientꢀthermalꢀimpedance  
10

3  

10

0  

1 µs  
10 µs  
100 µs  
1 ms  
10

2  

10

1  

10

0  

10

-1  

0.5  
10 ms  
10

-1  

0.2  
DC  
0.1  
0.05  
0.02  
0.01  
single pulse  
10

-2  

10

-1  

10

0  

10

1  

10

2  

10

-5  

10

-4  

10

-3  

10

-2  

10

-1  

10

0  

V

DS

ꢀ[V]  
t

p

ꢀ[s]  
I

D

=f(
V

DS

);ꢀ
T

C

=25ꢀ°C;ꢀ
D
=0;ꢀparameter:ꢀ
t

p  

Z

thJC

=f(
t

p

);ꢀparameter:ꢀ
D
=
t

p

/
T  
Final Data Sheet  
7
Rev.ꢀ2.1,ꢀꢀ2015-10-15  

OptiMOS

ª

ꢀꢀ5ꢀPower-Transistor,ꢀ80ꢀV  
IPB015N08N5  
Diagramꢀ5:ꢀTyp.ꢀoutputꢀcharacteristics  
Diagramꢀ6:ꢀTyp.ꢀdrain-sourceꢀonꢀresistance  
720  
5
6 V  
5.5 V  
7 V  
5 V  
10 V  
4.5 V  
680  
640  
600  
560  
520  
480  
440  
400  
360  
320  
280  
240  
200  
160  
120  
80  
4
3
2
1
0
5.5 V  
5 V  
6 V  
7 V  
10 V  
4.5 V  
40  
0
0
1
2
3
4
5
0
50  
100 150 200 250 300 350 400 450  
V

DS

ꢀ[V]  
I

D

ꢀ[A]  
I

D

=f(
V

DS

);ꢀ
T

j

=25ꢀ°C;ꢀparameter:ꢀ
V

GS  

R

DS(on)

=f(
I

D

);ꢀ
T

j

=25ꢀ°C;ꢀparameter:ꢀ
V

GS  

Diagramꢀ7:ꢀTyp.ꢀtransferꢀcharacteristics  
Diagramꢀ8:ꢀTyp.ꢀforwardꢀtransconductance  
300  
300  
250  
200  
150  
250  
200  
150  
100  
50  
100  
150 °C  
25 °C  
50  
0
0
0
2
4
6
8
0
40  
80  
120  
160  
V

GS

ꢀ[V]  
I

D

ꢀ[A]  
I

D

=f(
V

GS

);ꢀ|
V

DS

|>2|
I

D

|
R

DS(on)max

;ꢀparameter:ꢀ
T

j  

g

fs

=f(
I

D

);ꢀ
T

j

=25ꢀ°C  
Final Data Sheet  
8
Rev.ꢀ2.1,ꢀꢀ2015-10-15  

OptiMOS

ª

ꢀꢀ5ꢀPower-Transistor,ꢀ80ꢀV  
IPB015N08N5  
Diagramꢀ9:ꢀDrain-sourceꢀon-stateꢀresistance  
Diagramꢀ10:ꢀTyp.ꢀgateꢀthresholdꢀvoltage  
4
4.0  
3.5  
2790 µA  
3
3.0  
279 µA  
2.5  
2
2.0  
1.5  
1.0  
0.5  
0.0  
max  
typ  
1
0
-60  
-20  
20  
60  
100  
140  
180  
-60  
-20  
20  
60  
100  
140  
180  
T

j

ꢀ[°C]  
T

j

ꢀ[°C]  
R

DS(on)

=f(
T

j

);ꢀ
I

D

=100ꢀA;ꢀ
V

GS

=10ꢀV  
V

GS(th)

=f(
T

j

);ꢀ
V

GS

=
V

DS

;ꢀparameter:ꢀ
I

D  

Diagramꢀ11:ꢀTyp.ꢀcapacitances  
Diagramꢀ12:ꢀForwardꢀcharacteristicsꢀofꢀreverseꢀdiode  
10

5  

10

3  

25 °C  
175 °C  
25 °C, max  
175 °C, max  
Ciss  
10

4  

10

3  

10

2  

10

1  

10

2  

10

1  

10

0  

Coss  
Crss  
0
20  
40  
60  
80  
0.0  
0.5  
1.0  
1.5  
2.0  
V

DS

ꢀ[V]  
V

SD

ꢀ[V]  
C
=f(
V

DS

);ꢀ
V

GS

=0ꢀV;ꢀ
f
=1ꢀMHz  
I

F

=f(
V

SD

);ꢀparameter:ꢀ
T

j  

Final Data Sheet  
9
Rev.ꢀ2.1,ꢀꢀ2015-10-15  

OptiMOS

ª

ꢀꢀ5ꢀPower-Transistor,ꢀ80ꢀV  
IPB015N08N5  
Diagramꢀ13:ꢀAvalancheꢀcharacteristics  
Diagramꢀ14:ꢀTyp.ꢀgateꢀcharge  
10

3  

10  
8
25 °C  
40 V  
10

2  

10

1  

10

0  

6
100 °C  
150 °C  
60 V  
20 V  
4
2
0
10

0  

10

1  

10

2  

10

3  

0
50  
100  
150  
200  
t

AV

ꢀ[µs]  
Q

gate

ꢀ[nC]  
I

AS

=f(
t

AV

);ꢀ
R

GS

=25ꢀ
Ω
;ꢀparameter:ꢀ
T

j(start)  

V

GS

=f(
Q

gate

);ꢀ
I

D

=100ꢀAꢀpulsed;ꢀparameter:ꢀ
V

DD  

Diagramꢀ15:ꢀDrain-sourceꢀbreakdownꢀvoltage  
Gate charge waveforms  
90  
85  
80  
75  
70  
-60  
-20  
20  
60  
100  
140  
180  
T

j

ꢀ[°C]  
V

BR(DSS)

=f(
T

j

);ꢀ
I

D

=1ꢀmA  
Final Data Sheet  
10  
Rev.ꢀ2.1,ꢀꢀ2015-10-15  

OptiMOS

ª

ꢀꢀ5ꢀPower-Transistor,ꢀ80ꢀV  
IPB015N08N5  
6ꢀꢀꢀꢀꢀPackageꢀOutlines  
Figureꢀ1ꢀꢀꢀꢀꢀOutlineꢀPG-TO263-7,ꢀdimensionsꢀinꢀmm/inches  
Final Data Sheet  
11  
Rev.ꢀ2.1,ꢀꢀ2015-10-15  

OptiMOS

ª

ꢀꢀ5ꢀPower-Transistor,ꢀ80ꢀV  
IPB015N08N5  
RevisionꢀHistory  
IPB015N08N5  
Revision:ꢀ2015-10-15,ꢀRev.ꢀ2.1  
Previous Revision  
Revision Date  
Subjects (major changes since last revision)  
2.0  
2.1  
Release of final version  
Update package Outline  
2014-12-11  
2015-10-15  
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Final Data Sheet  
12  
Rev.ꢀ2.1,ꢀꢀ2015-10-15