Infineon-Technologies-IPD50N04S3-09
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IPD50N04S3-09
OptiMOS
®
-T
Power-Transistor
Product Summary
V
DS
40
9
V
R
DS(on),max
I
D
m
Ω
A
50
Features
• N-channel – Enhancement mode
PG-TO252-3-11
• Automotive AEC Q101 qualified
• MSL1 up to 260°C peak reflow
• 175°C operating temperature
• Green package (RoHS compliant)
• 100% Avalanche tested
Type
Package
Marking
IPD50N04S3-09
PG-TO252-3-11 3N0409
Maximum ratings,
at
T
j
=25 °C, unless otherwise specified
Value
Parameter
Symbol
Conditions
Unit
T
C
=25 °C,
V
GS
=10 V
1)
I
D
Continuous drain current
50
A
T
C
=100 °C,
V
43
GS
=10 V
2)
Pulsed drain current
2)
I
D,pulse
E
AS
T
C
=25 °C
I
D
=25 A
200
140
Avalanche energy, single pulse
2)
Avalanche current, single pulse
Gate source voltage
mJ
A
I
AS
50
V
GS
±20
V
P
tot
T
C
=25 °C
Power dissipation
63
W
°C
T
j
,
T
stg
Operating and storage temperature
IEC climatic category; DIN IEC 68-1
-55 … +175
55/175/56
Rev. 1.1
page 1
2009-11-03
IPD50N04S3-09
Values
Parameter
Symbol
Conditions
Unit
min.
typ.
max.
Thermal characteristics
2)
R
thJC
R
thJA
Thermal resistance, junction – case
SMD version, device on PCB
–
–
–
–
–
–
2.4
62
40
K/W
minimal footprint
6 cm
2
cooling area
3)
Electrical characteristics,
at
T
j
=25 °C, unless otherwise specified
Static characteristics
V
(BR)DSS
V
GS(th)
V
V
GS
=0 V,
I
D
= 1 mA
DS
=
V
GS
,
I
D
=28 µA
Drain-source breakdown voltage
Gate threshold voltage
40
–
–
V
2.1
3.0
4.0
V
DS
=40 V,
V
GS
=0 V,
I
DSS
Zero gate voltage drain current
–
–
–
–
1
µA
T
j
=25 °C
V
DS
=40 V,
V
GS
=0 V,
100
T
j
=125 °C
2)
I
GSS
V
V
GS
=20 V,
V
DS
=0 V
GS
=10 V,
I
D
=50 A
Gate-source leakage current
–
–
–
100 nA
R
DS(on)
Drain-source on-state resistance
7.5
9.0
m
Ω
Rev. 1.1
page 2
2009-11-03
IPD50N04S3-09
Values
Parameter
Symbol
Conditions
Unit
min.
typ.
max.
Dynamic characteristics
2)
Input capacitance
Output capacitance
Reverse transfer capacitance
Turn-on delay time
Rise time
C
iss
C
oss
C
rss
t
d(on)
t
r
–
–
–
–
–
–
–
1350
720
55
11
7
1750 pF
940
V
GS
=0 V,
V
DS
=25 V,
f
=1 MHz
85
–
–
–
–
ns
V
DD
=20 V,
V
GS
=10 V,
I
D
=50 A,
R
G
=3.5
Ω
t
d(off)
t
f
Turn-off delay time
Fall time
16
6
Gate Charge Characteristics
2)
Gate to source charge
Gate to drain charge
Gate charge total
Q
gs
–
–
–
–
8
5
11
8
nC
Q
gd
V
V
DD
=32 V,
I
D
=50 A,
GS
=0 to 10 V
Q
g
20
5.8
26
–
V
plateau
Gate plateau voltage
V
A
Reverse Diode
Diode continous forward current
2)
Diode pulse current
2)
I
S
–
–
–
–
50
T
C
=25 °C
I
S,pulse
200
V
GS
=0 V,
I
F
=50 A,
V
SD
Diode forward voltage
–
0.9
1.3
V
T
j
=25 °C
Reverse recovery time
2)
Reverse recovery charge
2)
t
rr
–
–
30
32
–
–
ns
V
R
=20 V,
I
F
=
I
S
,
d
i
F
/d
t
=100 A/µs
Q
rr
nC
1)
Current is limited by bondwire; with an
R
thJC
= 2.4K/W the chip is able to carry 61A at 25°C.
2)
Defined by design. Not subject to production test.
3)
Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm
2
(one layer, 70 µm thick) copper area for drain
connection. PCB is vertical in still air.
Rev. 1.1
page 3
2009-11-03
IPD50N04S3-09
1 Power dissipation
2 Drain current
P
tot
= f(
T
C
);
V
GS
≥
6 V
I
D
= f(
T
C
);
V
GS
≥
6 V
70
60
50
40
30
20
10
0
60
40
20
0
0
50
100
150
200
0
50
100
150
200
T
C
[°C]
T
C
[°C]
3 Safe operating area
4 Max. transient thermal impedance
thJC
= f(
t
p
)
I
D
= f(
V
DS
);
T
C
= 25 °C;
D
= 0
parameter:
t
p
Z
parameter:
D
=
t
p
/
T
10
1
1000
100
10
0.5
1 µs
10 µs
10
0
0.1
100 µs
0.05
1 ms
10
-1
0.01
single pulse
10
-2
1
10
-3
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
0.1
1
10
100
V
DS
[V]
t
p
[s]
Rev. 1.1
page 4
2009-11-03
IPD50N04S3-09
5 Typ. output characteristics
I
D
= f(
V
DS
);
T
j
= 25 °C
parameter:
V
GS
6 Typ. drain-source on-state resistance
DS(on)
= f(
I
D
);
T
j
= 25 °C
R
parameter:
V
GS
200
25
23
21
19
17
15
13
11
9
6 V
5.5 V
6.5 V
7 V
160
120
80
40
0
10 V
6.5 V
6 V
7 V
5.5 V
5 V
10 V
7
5
0
20
40
60
D
[A]
80
100
120
0
2
4
6
8
I
V
DS
[V]
7 Typ. transfer characteristics
I
D
= f(
V
GS
);
V
DS
= 6V
parameter:
T
j
8 Typ. drain-source on-state resistance
R
DS(on)
= f(
T
j
);
I
D
= 50 A;
V
GS
= 10 V
200
160
120
80
15
14
13
12
11
10
9
25 °C
-55 °C
175 °C
8
40
7
6
0
5
2
3
4
5
6
7
8
-60
-20
20
60
T
j
[°C]
100
140
180
V
GS
[V]
Rev. 1.1
page 5
2009-11-03
IPD50N04S3-09
9 Typ. gate threshold voltage
GS(th)
= f(
T
j
);
V
GS
=
V
DS
10 Typ. capacitances
V
C
= f(
V
DS
);
V
GS
= 0 V;
f
= 1 MHz
parameter:
I
D
4
10
4
10
3
10
2
10
1
3.5
3
Ciss
150 µA
Coss
30 µA
2.5
2
Crss
1.5
1
0
5
10
15
20
25
30
-60
-20
20
60
T
j
[°C]
100
140
180
V
DS
[V]
11 Typical forward diode characteristicis
12 Typ. avalanche characteristics
A S
= f(
t
AV
IF = f(V
SD
)
I
)
parameter:
T
j
parameter: T
j(start)
10
3
10
2
10
1
100
25 °C
100 °C
150 °C
10
25 °C
175 °C
10
0
1
1
0
0.2
0.4
0.6
0.8
1
1.2
1.4
10
100
1000
V
SD
[V]
t
AV
[µs]
Rev. 1.1
page 6
2009-11-03
IPD50N04S3-09
13 Typical avalanche energy
AS
= f(
T
j
)
14 Typ. drain-source breakdown voltage
E
V
BR(DSS)
= f(
T
j
);
I
D
= 1 mA
parameter:
I
D
55
300
12.5 A
250
200
150
100
50
50
45
40
35
30
25 A
50 A
0
-60
-20
20
60
100
140
180
25
75
125
175
T
j
[°C]
T
j
[°C]
15 Typ. gate charge
GS
= f(
Q
gate
);
I
D
= 50 A pulsed
16 Gate charge waveforms
V
parameter:
V
DD
12
V
GS
8 V
32 V
Q
g
10
8
6
V
g
s(th)
4
2
Q
g
(
t
h)
Q
sw
Q
g
d
Q
g
ate
Q
g
s
0
0
10
20
30
Q
gate
[nC]
Rev. 1.1
page 7
2009-11-03
IPD50N04S3-09
Published by
Infineon Technologies AG
81726 Munich, Germany
©
Infineon Technologies AG 2008
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions
or characteristics. With respect to any examples or hints given herein,
any typical values stated herein and/or any information regarding the application of the device,
Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including
without limitation warranties of non
‑
infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please
Warnings
Due to technical requirements components may contain dangerous substances. For information
on the types in question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the
express written approval of Infineon Technologies, if a failure of such components can reasonably
be expected to cause the failure of that life-support device or system, or to affect the safety or
effectiveness of that device or system. Life support devices or systems are intended to be
implanted in the human body, or to support and/or maintain and sustain and/or protect human life.
If they fail, it is reasonable to assume that the health of the user or other persons may be
endangered.
Rev. 1.1
page 8
2009-11-03
IPD50N04S3-09
Revision History
Version
Date
Changes
Update of SOA diagram for 1ms
03.10.2009 curve
Rev. 1.1
Rev. 1.1
page 9
2009-11-03
