Infineon-Technologies-IPD50P04P413ATMA1
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IPD50P04P4-13
OptiMOS
®
-P2 Power-Transistor
Product Summary
V
DS
R
DS(on)
I
D
-40
12.6
-50
V
m
W
A
Features
• P-channel – Normal Level – Enhancement mode
• AEC qualified
PG-TO252-3-313
Tab
• MSL1 up to 260°C peak reflow
• 175°C operating temperature
• Green package (RoHS compliant)
• 100% Avalanche tested
1
3
Source
pin 3
Gate
pin 1
Type
Package
Marking
Drain
pin 2/Tab
IPD50P04P4-13
PG-TO252-3-313 4P0413
Maximum ratings,
at
T
j
=25 °C, unless otherwise specified
Value
Parameter
Symbol
Conditions
Unit
T
C
=25°C,
V
GS
=-10V
Continuous drain current
1)
I
D
-50
A
T
C
=100°C,
V
GS
=-10V
2)
-45
Pulsed drain current
2)
I
D,pulse
E
AS
I
AS
T
C
=25°C
-200
18
Avalanche energy, single pulse
2)
Avalanche current, single pulse
Gate source voltage
I
D
=-25A
mJ
A
–
-50
±20
58
V
GS
P
tot
–
V
T
C
=25 °C
Power dissipation
W
°C
T
j
,
T
stg
–
Operating and storage temperature
IEC climatic category; DIN IEC 68-1
–
–
-55 … +175
55/175/56
Rev. 1.3
page 1
2019-07-16
IPD50P04P4-13
Values
Parameter
Symbol
Conditions
Unit
min.
typ.
max.
Thermal characteristics
2)
R
thJC
R
thJA
Thermal resistance, junction – case
SMD version, device on PCB
–
–
–
–
–
–
–
2.6
62
40
K/W
minimal footprint
6 cm
2
cooling area
3)
Electrical characteristics,
at
T
j
=25 °C, unless otherwise specified
Static characteristics
V
(BR)DSS
V
GS
=0V,
I
D
= -1mA
V
GS(th)
V
DS
=
V
GS
,
I
D
=-85µA
Drain-source breakdown voltage
Gate threshold voltage
-40
–
–
V
-2.0
-3.0
-4.0
V
DS
=-32V,
V
GS
=0V,
T
j
=25°C
I
DSS
Zero gate voltage drain current
–
–
-0.05
-20
-1
µA
V
DS
=-32V,
V
GS
=0V,
T
j
=125°C
2)
-200
I
GSS
V
GS
=-20V,
V
DS
=0V
Gate-source leakage current
–
–
–
-100 nA
R
DS(on)
V
GS
=-10V,
I
D
=-50A
Drain-source on-state resistance
9.2
12.6
m
W
Rev. 1.3
page 2
2019-07-16
IPD50P04P4-13
Values
Parameter
Symbol
Conditions
Unit
min.
typ.
max.
Dynamic characteristics
2)
Input capacitance
Output capacitance
Reverse transfer capacitance
Turn-on delay time
Rise time
C
iss
C
oss
C
rss
t
d(on)
t
r
–
–
–
–
–
–
–
2820
1000
30
3670 pF
1500
V
GS
=0V,
V
DS
=-25V,
f
=1MHz
60
17
–
–
–
–
ns
V
DD
=-20V,
V
GS
=-10V,
I
D
=-50A,
R
G
=3.5
W
10
t
d(off)
t
f
Turn-off delay time
Fall time
22
28
Gate Charge Characteristics
2)
Gate to source charge
Gate to drain charge
Gate charge total
Q
gs
–
–
–
–
14
7
19
14
51
–
nC
Q
gd
V
DD
=-32V,
I
D
=-50A,
V
GS
=0 to -10V
Q
g
39
5.4
V
plateau
Gate plateau voltage
V
A
Reverse Diode
Diode continous forward current
2)
Diode pulse current
2)
I
S
–
–
–
–
-50
T
C
=25°C
I
S,pulse
-200
V
GS
=0V,
I
F
=-50A,
T
j
=25°C
V
SD
Diode forward voltage
–
-1
-1.3
V
Reverse recovery time
2)
t
rr
–
–
39
32
–
–
ns
V
R
=-20V,
I
F
=-50A,
d
i
F
/d
t
=-100A/µs
Reverse recovery charge
2)
Q
rr
nC
1)
Current is limited by bondwire; with an
R
thJC
= 2.6K/W the chip is able to carry -55A at 25°C.
2)
Defined by design. Not subject to production test.
3)
Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm
2
(one layer, 70 µm thick) copper area for drain
connection. PCB is vertical in still air.
Rev. 1.3
page 3
2019-07-16
IPD50P04P4-13
1 Power dissipation
2 Drain current
P
tot
= f(
T
C
);
V
GS
= -10V
I
D
= f(
T
C
);
V
GS
= -10V
80
60
40
20
0
60
40
20
0
0
50
100
150
200
0
50
100
150
200
T
C
[
°
C]
T
C
[
°
C]
3 Safe operating area
4 Max. transient thermal impedance
Z
thJC
= f(
t
p
)
I
D
= f(
V
DS
);
T
C
= 25 °C;
D
= 0
parameter:
t
p
parameter:
D
=
t
p
/
T
10
1
1000
1 µs
10
0
10 µs
100
100 µs
0.1
1 ms
10
-1
0.05
0.01
10
single pulse
10
-2
10
-3
1
0.1
1
10
100
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
-V
DS
[V]
t
p
[s]
Rev. 1.3
page 4
2019-07-16
IPD50P04P4-13
5 Typ. output characteristics
I
D
= f(
V
DS
);
T
j
= 25 °C
parameter: –
V
GS
6 Typ. drain-source on-state resistance
R
DS(on)
= (
I
D
);
T
j
= 25 °C
parameter: –
V
GS
40
200
5V
35
30
25
20
15
10
8V
10V
150
100
50
7V
6V
6V
7V
8V
10V
5V
5
0
0
25
50
0
2
4
6
-I
D
[A]
-V
DS
[V]
7 Typ. transfer characteristics
I
D
= f(
V
GS
);
V
DS
= -6V
parameter:
T
j
8 Typ. drain-source on-state resistance
R
DS(on)
= f(
T
j
);
I
D
= -50 A;
V
GS
= -10 V
200
150
100
16
14
12
10
8
50
175 °C
-55 °C
25 °C
6
0
-60
-20
20
60
100
140
180
2
3
4
5
6
7
8
T
j
[
°
C]
-V
GS
[V]
Rev. 1.3
page 5
2019-07-16
IPD50P04P4-13
9 Typ. gate threshold voltage
V
GS(th)
= f(
T
j
);
V
GS
=
V
DS
parameter: –
I
D
10 Typ. capacitances
C
= f(
V
DS
);
V
GS
= 0 V;
f
= 1 MHz
10
4
10
3
10
2
10
1
4
3.5
3
Ciss
850µA
Coss
85µA
2.5
2
1.5
1
Crss
0
5
10
15
20
25
30
-60
-20
20
60
100
140
180
T
j
[
°
C]
-V
DS
[V]
11 Typical forward diode characteristicis
12 Drain-source breakdown voltage
IF = f(V
SD
)
V
BR(DSS)
= f(
T
j
);
I
D
= -1 mA
parameter:
T
j
10
3
44
43
42
41
40
39
38
37
10
2
5 °C
175 °C
10
1
10
0
0
0.4
0.8
-V
SD
[V]
1.2
1.6
-60
-20
20
60
100
140
180
T
j
[
°
C]
Rev. 1.3
page 6
2019-07-16
IPD50P04P4-13
13 Typ. gate charge
V
GS
= f(
Q
gate
);
I
D
= -50 A pulsed
parameter:
V
DD
14 Gate charge waveforms
10
9
8
7
6
5
4
3
2
1
0
V
GS
-8V
Q
g
-32V
Q
gate
Q
gd
Q
gs
0
10
20
30
40
Q
gate
[nC]
Rev. 1.3
page 7
2019-07-16
IPD50P04P4-13
Published by
Infineon Technologies AG
81726 Munich, Germany
©
Infineon Technologies AG 2019
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions
or characteristics. With respect to any examples or hints given herein, any typical values stated
herein and/or any information regarding the application of the device, Infineon Technologies hereby
disclaims any and all warranties and liabilities of any kind, including without limitation, warranties
of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact
Warnings
Due to technical requirements, components may contain dangerous substances.
For information on the types in question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the
express written approval of Infineon Technologies, if a failure of such components can reasonably be
expected to cause the failure of that life-support device or system or to affect the safety or
effectiveness of that device or system. Life support devices or systems are intended to be implanted
in the human body or to support and/or maintain and sustain and/or protect human life.
If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Rev. 1.3
page 8
2019-07-16
IPD50P04P4-13
Revision History
Version
Date
Changes
1.0 14.03.2011
1.1 21.12.2012
1.2 09.12.2013
1.3 16.07.2019
Final Data Sheet
Update of diagram 8
Update of Idpuls and SOA
graphs corrected
Rev. 1.3
page 9
2019-07-16
