Infineon-Technologies-IPP033N04NF2S
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IPP033N04NF2S
MOSFET
StrongIRFET
TM
2ꢀPower-Transistor
PG-TO220-3
tab
Features
•ꢀOptimizedꢀforꢀwideꢀrangeꢀofꢀapplications
•ꢀN-channel,ꢀnormalꢀlevel
•ꢀ100%ꢀavalancheꢀtested
•ꢀPb-freeꢀleadꢀplating;ꢀRoHSꢀcompliant
•ꢀHalogen-freeꢀaccordingꢀtoꢀIEC61249-2-21
Productꢀvalidation
QualifiedꢀaccordingꢀtoꢀJEDECꢀStandard
Drain
Pin 2, Tab
Tableꢀ1ꢀꢀꢀꢀꢀKeyꢀPerformanceꢀParameters
Parameter
Value
Unit
Gate
Pin 1
V
DS
40
V
R
DS(on),max
I
D
3.3
113
49
m
Ω
A
Source
Pin 3
Q
oss
nC
nC
Q
Gꢀ
(0V..10V)
45
Typeꢀ/ꢀOrderingꢀCode
Package
Marking
RelatedꢀLinks
IPP033N04NF2S
PG-TO220-3
033N04NS
–
Final Data Sheet
1
Rev.ꢀ2.0,ꢀꢀ2022-06-07
StrongIRFET
TM
2ꢀPower-Transistor
IPP033N04NF2S
TableꢀofꢀContents
Description .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Maximum ratings
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
Thermal characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
Electrical characteristics diagrams
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
Package Outlines
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
Revision History
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
Trademarks .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
Disclaimer .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
Final Data Sheet
2
Rev.ꢀ2.0,ꢀꢀ2022-06-07
StrongIRFET
TM
2ꢀPower-Transistor
IPP033N04NF2S
1ꢀꢀꢀꢀꢀMaximumꢀratings
atꢀ
T
A
=25ꢀ°C,ꢀunlessꢀotherwiseꢀspecified
Tableꢀ2ꢀꢀꢀꢀꢀMaximumꢀratings
Values
Typ.
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Max.
V
GS
=10ꢀV,ꢀ
T
C
=25ꢀ°C
V
GS
=10ꢀV,ꢀ
T
C
=100ꢀ°C
–
–
–
–
–
–
113
87
25
Continuous drain current
1)
I
D
A
V
GS
=10ꢀV,ꢀ
T
A
=25ꢀ°C,
R
THJA
=40ꢀ°C/W
2)
Pulsed drain current
3)
Avalanche energy, single pulse
4)
I
D,pulse
E
AS
–
–
–
–
452
71
A
T
A
=25ꢀ°C
–
mJ
V
I
D
=70ꢀA,ꢀ
R
GS
=25ꢀ
Ω
Gate source voltage
V
GS
-20
20
–
–
–
–
–
107
3.8
T
C
=25ꢀ°C
Power dissipation
P
tot
W
T
A
=25ꢀ°C,ꢀ
R
THJA
=40ꢀ°C/W
2)
Operating and storage temperature
T
j
,ꢀ
T
stg
-55
–
175
°C
–
2ꢀꢀꢀꢀꢀThermalꢀcharacteristics
Tableꢀ3ꢀꢀꢀꢀꢀThermalꢀcharacteristics
Values
Typ.
–
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Max.
Thermal resistance, junction – case
R
thJC
R
thJA
–
1.4
°C/W –
°C/W –
Thermal resistance, junction – ambient,
6 cm² cooling area
2)
–
–
–
–
40
62
Thermal resistance, junction – ambient,
minimal footprint
R
thJA
°C/W –
1)
Rating refers to the product only with datasheet specified absolute maximum values, maintaining case temperature
as specified. For other case temperatures please refer to Diagram 2. De-rating will be required based on the actual
environmental conditions.
2)
Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm
2
(one layer, 70 µm thick) copper area for drain
connection. PCB is vertical in still air.
3)
See Diagram 3 for more detailed information
4)
See Diagram 13 for more detailed information
Final Data Sheet
3
Rev.ꢀ2.0,ꢀꢀ2022-06-07
StrongIRFET
TM
2ꢀPower-Transistor
IPP033N04NF2S
3ꢀꢀꢀꢀꢀElectricalꢀcharacteristics
atꢀ
T
j
=25ꢀ°C,ꢀunlessꢀotherwiseꢀspecified
Tableꢀ4ꢀꢀꢀꢀꢀStaticꢀcharacteristics
Values
Typ.
–
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
40
Max.
–
Drain-source breakdown voltage
Gate threshold voltage
V
(BR)DSS
V
GS(th)
V
V
V
GS
=0ꢀV,ꢀ
I
D
=1ꢀmA
V
DS
=
V
GS
,ꢀ
I
D
=53ꢀµA
2.1
2.8
3.4
–
–
0.1
10
1
100
V
DS
=40ꢀV,ꢀ
V
GS
=0ꢀV,ꢀ
T
j
=25ꢀ°C
V
DS
=40ꢀV,ꢀ
V
GS
=0ꢀV,ꢀ
T
j
=125ꢀ°C
Zero gate voltage drain current
Gate-source leakage current
Drain-source on-state resistance
1)
I
DSS
µA
nA
I
GSS
–
10
100
V
GS
=20ꢀV,ꢀ
V
DS
=0ꢀV
–
–
2.6
3.0
3.3
4.2
V
GS
=10ꢀV,ꢀ
I
D
=70ꢀA
V
GS
=6ꢀV,ꢀ
I
D
=35ꢀA
R
DS(on)
m
Ω
Gate resistance
Transconductance
2)
R
G
g
fs
–
2.5
–
–
–
Ω
–
105
S
|
V
DS
|
≥
2|
I
D
|
R
DS(on)max
,ꢀ
I
D
=70ꢀA
Tableꢀ5ꢀꢀꢀꢀꢀDynamicꢀcharacteristics
Values
Typ.
3200
1160
69
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Max.
Input capacitance
C
iss
C
oss
C
rss
–
–
–
–
–
–
pF
pF
pF
V
GS
=0ꢀV,ꢀ
V
DS
=20ꢀV,ꢀ
f
=1ꢀMHz
V
GS
=0ꢀV,ꢀ
V
DS
=20ꢀV,ꢀ
f
=1ꢀMHz
V
GS
=0ꢀV,ꢀ
V
DS
=20ꢀV,ꢀ
f
=1ꢀMHz
Output capacitance
Reverse transfer capacitance
V
DD
=20ꢀV,ꢀ
V
GS
=10ꢀV,ꢀ
I
D
=70ꢀA,
R
G,ext
=1.6ꢀ
Ω
Turn-on delay time
Rise time
t
d(on)
t
r
t
d(off)
t
f
–
–
–
–
14
9
–
–
–
–
ns
ns
ns
ns
V
DD
=20ꢀV,ꢀ
V
GS
=10ꢀV,ꢀ
I
D
=70ꢀA,
R
G,ext
=1.6ꢀ
Ω
V
DD
=20ꢀV,ꢀ
V
GS
=10ꢀV,ꢀ
I
D
=70ꢀA,
R
G,ext
=1.6ꢀ
Ω
Turn-off delay time
Fall time
26
10
V
DD
=20ꢀV,ꢀ
V
GS
=10ꢀV,ꢀ
I
D
=70ꢀA,
R
G,ext
=1.6ꢀ
Ω
Tableꢀ6ꢀꢀꢀꢀꢀGateꢀchargeꢀcharacteristics
3)
ꢀ
Values
Typ.
13.9
8.8
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Max.
Gate to source charge
Gate charge at threshold
Gate to drain charge
Switching charge
Q
gs
–
–
–
–
–
–
–
–
–
nC
nC
nC
nC
nC
V
V
DD
=20ꢀV,ꢀ
I
D
=70ꢀA,ꢀ
V
GS
=0ꢀtoꢀ10ꢀV
V
DD
=20ꢀV,ꢀ
I
D
=70ꢀA,ꢀ
V
GS
=0ꢀtoꢀ10ꢀV
V
DD
=20ꢀV,ꢀ
I
D
=70ꢀA,ꢀ
V
GS
=0ꢀtoꢀ10ꢀV
V
DD
=20ꢀV,ꢀ
I
D
=70ꢀA,ꢀ
V
GS
=0ꢀtoꢀ10ꢀV
V
DD
=20ꢀV,ꢀ
I
D
=70ꢀA,ꢀ
V
GS
=0ꢀtoꢀ10ꢀV
V
DD
=20ꢀV,ꢀ
I
D
=70ꢀA,ꢀ
V
GS
=0ꢀtoꢀ10ꢀV
V
DS
=0.1ꢀV,ꢀ
V
GS
=0ꢀtoꢀ10ꢀV
Q
g(th)
Q
gd
–
8.6
–
Q
sw
13.7
45
–
Gate charge total
2)
Q
g
68
–
Gate plateau voltage
Gate charge total, sync. FET
Output charge
V
plateau
Q
g(sync)
Q
oss
4.4
40
–
nC
nC
49
–
V
DS
=20ꢀV,ꢀ
V
GS
=0ꢀV
1)
R
DS(on)
is specified at a distance of 1.8 mm distance to the package body; mounting at a larger distance increases the overall
package resistance of approximately 0.04 mOhm/mm per leg.
2)
Defined by design. Not subject to production test.
3)
See
″
Gate charge waveforms
″
for parameter definition
Final Data Sheet
4
Rev.ꢀ2.0,ꢀꢀ2022-06-07
StrongIRFET
TM
2ꢀPower-Transistor
IPP033N04NF2S
Tableꢀ7ꢀꢀꢀꢀꢀReverseꢀdiode
Values
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Typ.
–
Max.
86
452
1.1
–
Diode continuous forward current
Diode pulse current
I
S
–
–
–
–
–
A
T
C
=25ꢀ°C
I
S,pulse
V
SD
t
rr
–
A
T
C
=25ꢀ°C
Diode forward voltage
0.90
26
89
V
V
GS
=0ꢀV,ꢀ
I
F
=70ꢀA,ꢀ
T
j
=25ꢀ°C
V
R
=20ꢀV,ꢀ
I
F
=70ꢀA,ꢀd
i
F
/d
t
=500ꢀA/µs
V
R
=20ꢀV,ꢀ
I
F
=70ꢀA,ꢀd
i
F
/d
t
=500ꢀA/µs
Reverse recovery time
Reverse recovery charge
ns
nC
Q
rr
–
Final Data Sheet
5
Rev.ꢀ2.0,ꢀꢀ2022-06-07
StrongIRFET
TM
2ꢀPower-Transistor
IPP033N04NF2S
4ꢀꢀꢀꢀꢀElectricalꢀcharacteristicsꢀdiagrams
Diagramꢀ1:ꢀPowerꢀdissipation
Diagramꢀ2:ꢀDrainꢀcurrent
120
120
100
80
60
40
20
0
100
80
60
40
20
0
0
25
50
75
100
125
150
175
0
25
50
75
100
125
150
175
T
C
ꢀ[°C]
T
C
ꢀ[°C]
P
tot
=f(
T
C
)
I
D
=f(
T
C
);ꢀ
V
GS
≥
10ꢀV
Diagramꢀ3:ꢀSafeꢀoperatingꢀarea
Diagramꢀ4:ꢀMax.ꢀtransientꢀthermalꢀimpedance
10
3
10
2
single pulse
0.01
1 µs
0.02
0.05
0.1
0.2
0.5
10 µs
10
2
10
1
10
1
100 µs
1 ms
10
0
10
-1
10
-2
10
-3
10 ms
DC
10
0
10
-1
10
-2
10
-1
10
0
10
1
10
2
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
V
DS
ꢀ[V]
t
p
ꢀ[s]
I
D
=f(
V
DS
);ꢀ
T
C
=25ꢀ°C;ꢀ
D
=0;ꢀparameter:ꢀ
t
p
Z
thJC
=f(
t
p
);ꢀparameter:ꢀ
D
=
t
p
/
T
Final Data Sheet
6
Rev.ꢀ2.0,ꢀꢀ2022-06-07
StrongIRFET
TM
2ꢀPower-Transistor
IPP033N04NF2S
Diagramꢀ5:ꢀTyp.ꢀoutputꢀcharacteristics
Diagramꢀ6:ꢀTyp.ꢀdrain-sourceꢀonꢀresistance
450
6.5
7 V
400
6.0
6 V
4.5 V
5.5 V
10 V
350
300
250
5.5
5 V
5.0
4.5
4.0
3.5
5 V
200
150
100
50
5.5 V
6 V
3.0
7 V
4.5 V
10 V
2.5
2.0
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0
50
100
150
200
250
V
DS
ꢀ[V]
I
D
ꢀ[A]
I
D
=f(
V
DS
),ꢀ
T
j
=25ꢀ°C;ꢀparameter:ꢀ
V
GS
R
DS(on)
=f(
I
D
),ꢀ
T
j
=25ꢀ°C;ꢀparameter:ꢀ
V
GS
Diagramꢀ7:ꢀTyp.ꢀtransferꢀcharacteristics
Diagramꢀ8:ꢀTyp.ꢀdrain-sourceꢀonꢀresistance
450
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
400
350
300
250
200
150
100
175 °C
50
25 °C
175 °C
25 °C
0
1
2
3
4
5
6
3
6
9
12
15
V
GS
ꢀ[V]
V
GS
ꢀ[V]
I
D
=f(
V
GS
),ꢀ|
V
DS
|>2|
I
D
|
R
DS(on)max
;ꢀparameter:ꢀ
T
j
R
DS(on)
=f(
V
GS
),ꢀ
I
D
=70ꢀA;ꢀparameter:ꢀ
T
j
Final Data Sheet
7
Rev.ꢀ2.0,ꢀꢀ2022-06-07
StrongIRFET
TM
2ꢀPower-Transistor
IPP033N04NF2S
Diagramꢀ9:ꢀNormalizedꢀdrain-sourceꢀonꢀresistance
Diagramꢀ10:ꢀTyp.ꢀgateꢀthresholdꢀvoltage
1.8
3.5
1.6
1.4
1.2
1.0
0.8
0.6
3.0
2.5
2.0
1.5
1.0
530 µA
53 µA
-75 -50 -25
0
25 50 75
100 125 150 175 200
-75 -50 -25
0
25 50 75
100 125 150 175 200
T
j
ꢀ[°C]
T
j
ꢀ[°C]
R
DS(on)
=f(
T
j
),ꢀ
I
D
=70ꢀA,ꢀ
V
GS
=10ꢀV
V
GS(th
=f(
T
j
),ꢀ
V
GS
=
V
DS
;ꢀparameter:ꢀ
I
D
Diagramꢀ11:ꢀTyp.ꢀcapacitances
Diagramꢀ12:ꢀTyp.ꢀforwardꢀcharacteristicsꢀofꢀreverseꢀdiode
10
4
10
3
25 °C
175 °C
Ciss
10
3
10
2
10
1
10
2
10
1
10
0
Coss
Crss
0
10
20
30
40
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
V
DS
ꢀ[V]
V
SD
ꢀ[V]
C
=f(
V
DS
);ꢀ
V
GS
=0ꢀV;ꢀ
f
=1ꢀMHz
I
F
=f(
V
SD
);ꢀparameter:ꢀ
T
j
Final Data Sheet
8
Rev.ꢀ2.0,ꢀꢀ2022-06-07
StrongIRFET
TM
2ꢀPower-Transistor
IPP033N04NF2S
Diagramꢀ13:ꢀAvalancheꢀcharacteristics
Diagramꢀ14:ꢀTyp.ꢀgateꢀcharge
10
2
10
8 V
20 V
32 V
9
8
25 °C
7
6
5
4
3
2
1
0
10
1
100 °C
150 °C
10
0
10
-1
10
-1
10
0
10
1
10
2
10
3
0
10
20
30
40
50
t
AV
ꢀ[µs]
Q
gate
ꢀ[nC]
I
AS
=f(
t
AV
);ꢀ
R
GS
=25ꢀ
Ω
;ꢀparameter:ꢀ
T
j,start
V
GS
=f(
Q
gate
),ꢀ
I
D
=70ꢀAꢀpulsed,ꢀ
T
j
=25ꢀ°C;ꢀparameter:ꢀ
V
DD
Diagramꢀ15:ꢀDrain-sourceꢀbreakdownꢀvoltage
Diagram Gate charge waveforms
45
44
43
42
41
40
39
38
37
-75 -50 -25
0
25 50 75
100 125 150 175 200
T
j
ꢀ[°C]
V
BR(DSS)
=f(
T
j
);ꢀ
I
D
=1ꢀmA
Final Data Sheet
9
Rev.ꢀ2.0,ꢀꢀ2022-06-07
StrongIRFET
TM
2ꢀPower-Transistor
IPP033N04NF2S
5ꢀꢀꢀꢀꢀPackageꢀOutlines
PACKAGE – GROUP
NUMBER:
PG-TO220-3-U05
REVISION: 02
DATE: 15.12.2020
MILLIMETERS
DIMENSIONS
MIN.
4.25
1.14
2.47
0.71
1.14
0.36
14.32
8.39
11.89
9.90
8.10
MAX.
4.75
1.40
2.92
0.97
1.78
0.61
15.80
9.20
12.80
10.67
8.74
A
A1
A2
b
b1
c
D
D1
D2
E
E1
e
2.54
3
N
H
6.00
13.00
3.56
3.54
2.54
6.70
14.40
4.06
3.90
2.94
L
L1
øP
Q
Figureꢀ1ꢀꢀꢀꢀꢀOutlineꢀPG-TO220-3,ꢀdimensionsꢀinꢀmm
Final Data Sheet
10
Rev.ꢀ2.0,ꢀꢀ2022-06-07
StrongIRFET
TM
2ꢀPower-Transistor
IPP033N04NF2S
RevisionꢀHistory
IPP033N04NF2S
Revision:ꢀ2022-06-07,ꢀRev.ꢀ2.0
Previous Revision
Revision Date
Subjects (major changes since last revision)
Release of final version
2.0
2022-06-07
Trademarks
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Publishedꢀby
InfineonꢀTechnologiesꢀAG
81726ꢀMünchen,ꢀGermany
©ꢀ2022ꢀInfineonꢀTechnologiesꢀAG
AllꢀRightsꢀReserved.
LegalꢀDisclaimer
Theꢀinformationꢀgivenꢀinꢀthisꢀdocumentꢀshallꢀinꢀnoꢀeventꢀbeꢀregardedꢀasꢀaꢀguaranteeꢀofꢀconditionsꢀorꢀcharacteristicsꢀ
(“Beschaffenheitsgarantie”)ꢀ.
Withꢀrespectꢀtoꢀanyꢀexamples,ꢀhintsꢀorꢀanyꢀtypicalꢀvaluesꢀstatedꢀhereinꢀand/orꢀanyꢀinformationꢀregardingꢀtheꢀapplicationꢀofꢀthe
product,ꢀInfineonꢀTechnologiesꢀherebyꢀdisclaimsꢀanyꢀandꢀallꢀwarrantiesꢀandꢀliabilitiesꢀofꢀanyꢀkind,ꢀincludingꢀwithoutꢀlimitation
warrantiesꢀofꢀnon-infringementꢀofꢀintellectualꢀpropertyꢀrightsꢀofꢀanyꢀthirdꢀparty.
Inꢀaddition,ꢀanyꢀinformationꢀgivenꢀinꢀthisꢀdocumentꢀisꢀsubjectꢀtoꢀcustomer’sꢀcomplianceꢀwithꢀitsꢀobligationsꢀstatedꢀinꢀthis
documentꢀandꢀanyꢀapplicableꢀlegalꢀrequirements,ꢀnormsꢀandꢀstandardsꢀconcerningꢀcustomer’sꢀproductsꢀandꢀanyꢀuseꢀofꢀthe
productꢀofꢀInfineonꢀTechnologiesꢀinꢀcustomer’sꢀapplications.
Theꢀdataꢀcontainedꢀinꢀthisꢀdocumentꢀisꢀexclusivelyꢀintendedꢀforꢀtechnicallyꢀtrainedꢀstaff.ꢀItꢀisꢀtheꢀresponsibilityꢀofꢀcustomer’s
technicalꢀdepartmentsꢀtoꢀevaluateꢀtheꢀsuitabilityꢀofꢀtheꢀproductꢀforꢀtheꢀintendedꢀapplicationꢀandꢀtheꢀcompletenessꢀofꢀtheꢀproduct
informationꢀgivenꢀinꢀthisꢀdocumentꢀwithꢀrespectꢀtoꢀsuchꢀapplication.
Information
Forꢀfurtherꢀinformationꢀonꢀtechnology,ꢀdeliveryꢀtermsꢀandꢀconditionsꢀandꢀpricesꢀpleaseꢀcontactꢀyourꢀnearestꢀInfineon
TechnologiesꢀOfficeꢀ(www.infineon.com).
Warnings
Dueꢀtoꢀtechnicalꢀrequirements,ꢀcomponentsꢀmayꢀcontainꢀdangerousꢀsubstances.ꢀForꢀinformationꢀonꢀtheꢀtypesꢀinꢀquestion,
pleaseꢀcontactꢀtheꢀnearestꢀInfineonꢀTechnologiesꢀOffice.
TheꢀInfineonꢀTechnologiesꢀcomponentꢀdescribedꢀinꢀthisꢀDataꢀSheetꢀmayꢀbeꢀusedꢀinꢀlife-supportꢀdevicesꢀorꢀsystemsꢀand/or
automotive,ꢀaviationꢀandꢀaerospaceꢀapplicationsꢀorꢀsystemsꢀonlyꢀwithꢀtheꢀexpressꢀwrittenꢀapprovalꢀofꢀInfineonꢀTechnologies,ꢀifꢀa
failureꢀofꢀsuchꢀcomponentsꢀcanꢀreasonablyꢀbeꢀexpectedꢀtoꢀcauseꢀtheꢀfailureꢀofꢀthatꢀlife-support,ꢀautomotive,ꢀaviationꢀand
aerospaceꢀdeviceꢀorꢀsystemꢀorꢀtoꢀaffectꢀtheꢀsafetyꢀorꢀeffectivenessꢀofꢀthatꢀdeviceꢀorꢀsystem.ꢀLifeꢀsupportꢀdevicesꢀorꢀsystemsꢀare
intendedꢀtoꢀbeꢀimplantedꢀinꢀtheꢀhumanꢀbodyꢀorꢀtoꢀsupportꢀand/orꢀmaintainꢀandꢀsustainꢀand/orꢀprotectꢀhumanꢀlife.ꢀIfꢀtheyꢀfail,ꢀitꢀis
reasonableꢀtoꢀassumeꢀthatꢀtheꢀhealthꢀofꢀtheꢀuserꢀorꢀotherꢀpersonsꢀmayꢀbeꢀendangered.
Final Data Sheet
11
Rev.ꢀ2.0,ꢀꢀ2022-06-07
