Infineon-Technologies-IRF135SA204
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Strong
IR
FET™
IRF135SA204
HEXFET
®
Power MOSFET
Application
Brushed Motor drive applications
BLDC Motor drive applications
Battery powered circuits
V
DSS
135V
Half-bridge and full-bridge topologies
Synchronous rectifier applications
Resonant mode power supplies
OR-ing and redundant power switches
DC/DC and AC/DC converters
DC/AC Inverters
R
DS(on)
typ.
max
4.7m
5.9m
I
D (Silicon Limited)
160A
D
S
Benefits
S
S
Improved Gate,
Avalanche and Dynamic dV/dt Ruggedness
Fully Characterized Capacitance and Avalanche SOA
Enhanced body diode dV/dt and dI/dt Capability
Lead-Free, RoHS Compliant, Halogen-Free
S
S
S
G
D
2
PAK-7Pin
IRF135SA204
G
D
S
Gate
Drain
Source
Standard Pack
Base part number
Package Type
Form
Orderable Part Number
Quantity
IRF135SA204
D
2
PAK-7Pin
Tape and Reel
800
IRF135SA204
200
150
100
50
30
25
20
15
10
5
I
= 96A
D
T =
125°C
J
T =
25°C
J
0
4
0
8
12
16
20
25
50
75
100
125
150
175
V
, Gate-to-Source Voltage (V)
GS
T
, CaseTemperature (°C)
C
Fig 1.
Typical On– Resistance vs. Gate Voltage
Fig 2.
Maximum Drain Current vs. Case Temperature
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IRG5K50P5K50PM06E
IRF135SA204
Absolute Maximum Rating
Symbol
Parameter
Max.
160
Units
I
D
@ T
C
= 25°C
Continuous Drain Current, V
GS
@ 10V
I
D
@ T
C
= 100°C
Continuous Drain Current, V
GS
@ 10V
113
A
I
DM
Pulsed Drain Current
Maximum Power Dissipation
Linear Derating Factor
608
500
3.3
P
D
@T
C
= 25°C
W
W/°C
V
V
GS
Gate-to-Source Voltage
± 20
T
J
T
STG
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds (1.6mm from case)
-55 to
+ 175
300
°C
Avalanche Characteristics
E
AS (Thermally limited)
670
Single Pulse Avalanche Energy
mJ
E
AS (Thermally limited)
1280
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
I
AR
E
AR
A
mJ
See Fig 15, 16, 23a, 23b
Thermal Resistance
Symbol
Parameter
Typ.
–––
–––
Max.
0.3
Units
Junction-to-Case
R
JC
R
JA
°C/W
Junction-to-Ambient (PCB Mount)
40
Static @ T
J
= 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ.
Max. Units
Conditions
V
(BR)DSS
Drain-to-Source Breakdown Voltage
135 ––– –––
V
V
GS
= 0V, I
D
= 250µA
Breakdown Voltage Temp. Coefficient
––– 0.14 –––
V/°C Reference
to 25°C, I
D
= 5mA
V
(BR)DSS
/
T
J
R
DS(on)
V
GS(th)
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
–––
2.0
––– –––
4.7
3.0
5.9
4.0
20
V
GS
= 10V, I
D
= 96A
V
DS
= V
GS
, I
D
= 250µA
V
DS
=135 V, V
GS
= 0V
m
V
I
DSS
Drain-to-Source Leakage Current
µA
––– ––– 250
––– ––– 100
––– –––
-100
V
V
V
DS
= 135V,V
GS
= 0V,T
J
=125°C
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Gate Resistance
GS
= 20V
GS
= -20V
I
GSS
R
G
nA
–––
2.2
–––
Notes:
Repetitive rating; pulse width limited by max. junction temperature.
Limited by T
Jmax
, starting T
J
= 25°C, L = 146µH, R
G
= 50
, I
AS
= 96A, V
GS
=10V.
I
SD
96A, di/dt
2200A/µs, V
DD
V
(BR)DSS
, T
J
175°C.
Pulse width
400µs; duty cycle
2%.
C
oss
eff. (TR) is a fixed capacitance that gives the same charging time as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
C
oss
eff. (ER) is a fixed capacitance that gives the same energy as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
R
is measured at T
J
approximately 90°C.
When mounted on 1 inch square
PCB (FR-4). Please refer to AN-994 for more details:
Limited by T
Jmax
, starting T
J
= 25°C, L = 1.0mH, R
G
= 50
, I
AS
= 49A, V
GS
=10V.
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IRG5K50P5K50PM06E
IRF135SA204
Dynamic Electrical
Characteristics @ T
J
= 25°C (unless otherwise specified)
Symbol
gfs
Parameter
Forward Transconductance
Total Gate Charge
Min.
270
–––
–––
–––
–––
–––
–––
Typ. Max.
Units
Conditions
–––
210
54
–––
315
–––
–––
–––
–––
–––
S
V
DS
= 10V, I
D
= 96A
Q
g
I
D
= 96A
Q
gs
Gate-to-Source Charge
Gate-to-Drain Charge
Total Gate Charge Sync. (Qg– Qgd)
Turn-On Delay Time
V
DS
= 68V
V
GS
= 10V
nC
Q
gd
57
Q
sync
t
d(on)
t
r
153
20
V
DD
= 81V
I
D
= 96A
Rise Time
56
ns
t
d(off)
t
f
Turn-Off Delay Time
Fall Time
–––
–––
140
56
–––
–––
R
G
= 2.7
V
GS
= 10V
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
––– 11690 –––
V
GS
= 0V
–––
–––
650
290
–––
–––
V
DS
= 50V
ƒ = 1.0MHz,
See Fig.7
pF
Effective Output Capacitance
(Energy Related)
C
oss eff.(ER)
C
oss eff.(TR)
–––
–––
630
845
–––
–––
V
GS
= 0V, VDS = 0V to 108V
V
GS
= 0V, VDS = 0V to 108V
Output Capacitance (Time Related)
Diode Characteristics
Symbol
Parameter
Min.
Typ. Max.
Units
Conditions
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
MOSFET symbol
showing the
integral reverse
p-n junction diode.
D
I
S
–––
–––
160
A
G
S
I
SM
–––
–––
–––
–––
608
1.3
V
SD
Diode Forward Voltage
V
T
J
= 25°C,I
S
= 96A,V
GS
= 0V
dv/dt
Peak Diode Recovery dv/dt
–––
–––
–––
–––
–––
22
85
––– V/ns
T
J
= 175°C,I
S
=96A,V
DS
= 135V
–––
–––
–––
–––
T
J
= 25°C
V
DD
= 115V
I
F
= 96A,
t
rr
Reverse Recovery Time
ns
98
T
J
= 125°C
315
430
T
J
= 25°C
di/dt = 100A/µs
Q
rr
Reverse Recovery Charge
Reverse Recovery Current
nC
A
T
J
= 125°C
T
J
= 25°C
I
RRM
–––
6.6
–––
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IRG5K50P5K50PM06E
IRF135SA204
1000
1000
100
10
VGS
15V
VGS
15V
10V
6.0V
5.5V
5.0V
4.5V
4.3V
4.0V
TOP
TOP
10V
6.0V
5.5V
5.0V
4.5V
4.3V
4.0V
BOTTOM
BOTTOM
100
4.0V
4.0V
1
60µs PULSE WIDTH
Tj = 175°C
60µs PULSE WIDTH
Tj = 25°C
10
1
0.1
1
10
100
0.1
10
100
V
, Drain-to-Source Voltage (V)
DS
V
, Drain-to-Source Voltage (V)
DS
Fig 4.
Typical Output Characteristics
Fig 3.
Typical Output Characteristics
3.5
3.0
2.5
2.0
1.5
1.0
0.5
1000
I
= 96A
D
V
= 10V
GS
100
10
1
T =
175°C
J
T =
25°C
J
V
= 50V
DS
60µs PULSE WIDTH
0.1
2.0
3.0
4.0
5.0
6.0
-60 -40 -20
0
20 40 60 80
100 120 140 160 180
V
, Gate-to-Source Voltage (V)
GS
T ,
Junction Temperature (°C)
J
Fig 6.
Normalized On-Resistance vs. Temperature
Fig 5.
Typical Transfer Characteristics
100000
10000
1000
14
V
= 0V,
= C
f = 1 MHZ
GS
I =
96A
D
V
V
V
= 108V
DS
C
C
C
+ C
, C
SHORTED
iss
gs
gd
ds
12
10
8
= C
= 68V
rss
oss
gd
= C
+ C
DS
27V
ds
gd
DS=
Ciss
6
4
Coss
Crss
2
0
100
0
50
100
150
200
250
300
1
10
100
1000
Q
Total Gate Charge (nC)
G
V
, Drain-to-Source Voltage (V)
DS
Fig 7.
Typical Capacitance vs. Drain-to-Source Voltage
Fig 8.
Typical Gate Charge vs.Gate-to-Source Voltage
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IRG5K50P5K50PM06E
IRF135SA204
1000
1000
100
10
100µsec
10msec
T =
175°C
J
100
10
1
1msec
T =
25°C
J
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
1
DC
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
GS
0.1
0.1
0.1
1
10
100
0.2
0.4
0.6
0.8
1.0
1.2
V
, Drain-toSource
Voltage (V)
DS
V
, Source-to-Drain Voltage (V)
SD
Fig 10.
Maximum Safe Operating Area
Fig 9.
Typical Source-Drain Diode Forward Voltage
170
6.0
5.0
4.0
3.0
2.0
1.0
0.0
Id = 5.0mA
160
150
140
130
0
20
V
40
60
80
100
120
140
-60 -40 -20
0
20 40 60 80
100120140160180
Drain-to-Source Voltage (V)
T ,
Temperature ( °C )
DS,
J
Fig 11.
Drain-to-Source Breakdown Voltage
Fig 12.
Typical C
oss
Stored Energy
16.0
V
V
V
V
V
= 4.5V
= 5.5V
= 6.0V
= 8.0V
= 10V
GS
GS
GS
GS
GS
12.0
8.0
4.0
0
50
100
150
200
I ,
Drain Current (A)
D
Fig 13.
Typical On–Resistance vs. Drain Current
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IRG5K50P5K50PM06E
IRF135SA204
1
0.1
D = 0.50
0.20
0.10
0.05
0.01
0.02
0.01
0.001
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
1E-006
1E-005
0.0001
0.001
0.01 0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 14.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Allowed avalanche Current vs avalanche
Duty Cycle = Single Pulse
pulsewidth, tav, assuming
Tstart =25°C (Single Pulse)
Tj = 150°C and
100
0.01
0.05
0.10
10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
Tstart = 150°C.
j = 25°C and
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15.
Avalanche Current vs. Pulse Width
700
600
500
400
300
200
100
0
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1.Avalanche failures assumption:
TOP
BOTTOM 1.0%
Duty Cycle
= 96A
Single Pulse
I
D
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T
jmax
. This is validated for every
part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is not
exceeded.
3. Equation below based on circuit and waveforms shown in Figures
23a, 23b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage
increase during avalanche).
6. I
av
= Allowable avalanche current.
7.
T = Allowable rise in junction temperature, not to exceed T
jmax
(assumed as 25°C in Figure 14, 15).
t
av
= Average time in avalanche.
D = Duty cycle in avalanche =
tav ·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 14)
25
50
75
100
125
150
175
Starting T
, Junction Temperature (°C)
PD (ave) = 1/2 ( 1.3·BV·I
av
) =
T/ Z
thJC
J
I
av
= 2
T/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)· av
t
Fig 16.
Maximum Avalanche Energy vs. Temperature
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IRG5K50P5K50PM06E
IRF135SA204
40
4.0
3.5
3.0
2.5
2.0
1.5
1.0
I =
64A
F
V
= 115V
R
T =
25°C
J
T =
125°C
J
30
20
10
0
I
= 250µA
= 1.0mA
= 10mA
= 1.0A
D
I
D
I
D
I
D
-75 -50 -25
0
25 50 75
100 125 150 175
0
200
400
600
800
1000
T ,
Temperature ( °C )
di /dt
(A/µs)
J
F
Fig 17.
Threshold Voltage vs. Temperature
Fig 18.
Typical Recovery Current vs. dif/dt
1400
1200
1000
800
600
400
200
0
40
I
= 96A
I
= 64A
F
F
V
= 115V
V
= 115V
R
R
T =
25°C
J
T =
125°C
J
T =
25°C
J
T =
125°C
J
30
20
10
0
0
200
400
600
800
1000
0
200
400
600
800
1000
di /dt
(A/µs)
di /dt
(A/µs)
F
F
Fig 19.
Typical Recovery Current vs. dif/dt
Fig 20.
Typical Stored Charge vs. dif/dt
1400
I
= 96A
F
1200
1000
800
600
400
200
0
V
= 115V
R
T =
25°C
J
T =
125°C
J
0
200
400
600
800
1000
di /dt
(A/µs)
F
Fig 21.
Typical Stored Charge vs. dif/dt
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IRG5K50P5K50PM06E
IRF135SA204
Fig 22.
Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET
®
Power MOSFETs
V
(BR)DSS
t
p
15V
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
–
I
A
20V
I
0.01
t
p
AS
Fig 23a.
Unclamped Inductive Test Circuit
Fig 23b.
Unclamped Inductive Waveforms
Fig 24a.
Switching Time Test Circuit
Fig 24b.
Switching Time Waveforms
Id
Vds
Vgs
VDD
Vgs(th)
Qgs1
Qgs2
Qgd
Qgodr
Fig 25b.
Gate Charge Waveform
Fig 25a.
Gate Charge Test Circuit
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IRG5K50P5K50PM06E
IRF135SA204
Qualification Information
†
Qualification Level
Industrial
(per JEDEC JESD47F)
††
D
2
PAK-7Pin
MSL1
Yes
Moisture Sensitivity Level
RoHS Compliant
† Qualification
standards can be found at International Rectifier’s web site:
http://www.irf.com/product-info/reliability/
†† Applicable version of JEDEC standard at the time of product release.
Revision History
Date
Comments
Corrected package picture added “s” on pin number 2 – page 1.
Changed datasheet with Infineon logo – all pages.
Added disclaimer on last page
05/12/2017
Published by
Infineon Technologies AG
81726 München, Germany
©
Infineon Technologies AG 2015
All Rights Reserved.
IMPORTANT NOTICE
The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples, hints or any typical values stated herein and/or any
information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and
liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third
party.
In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this
document and any applicable legal requirements, norms and standards concerning customer’s products and any use of
the product of Infineon Technologies in customer’s applications.
The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of
customer’s technical departments to evaluate the suitability of the product for the intended application and the
completeness of the product information given in this document with respect to such application.
For further information on the product, technology, delivery terms and conditions and prices please contact your nearest
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Due to technical requirements products may contain dangerous substances. For information on the types in question
please contact your nearest Infineon Technologies office.
Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized
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2017-05-12
