Infineon-Technologies-IRF3808STRRPBF
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IRF3808SPbF
IRF3808LPbF
HEXFET
®
Power MOSFET
Typical Applications
Industrial Motor Drive
D
V
DSS
= 75V
Benefits
Advanced Process Technology
Ultra Low On-Resistance
Dynamic dv/dt Rating
175°C Operating Temperature
Fast Switching
R
DS(on)
= 0.007
Ω
G
I
D
= 106A
S
Repetitive Avalanche Allowed up to Tjmax
Lead-Free
Description
This Advanced Planar Stripe HEXFET ® Power MOSFET
utilizes the latest processing techniques to achieve
extremely low on-resistance per silicon area. Additional
features of this HEXFET power MOSFET are a 175°C
junction operating temperature, low R
θ
JC, fast switching
speed and improved repetitive avalanche rating. This
combination makes the design an extremely efficient and
reliable choice for use in
a wide variety of
applications.
D
2
Pak
IRF3808SPbF
TO-262
IRF3808LPbF
Standard Pack
Form
Tube
Base Part
Number
IRF3808LPbF
Package Type
Orderable Part Number
Quantity
50
50
800
TO-262
IRF3808LPbF
IRF3808SPbF
IR
F
3808STRLPbF
IR
F
3808STRRPbF
Tube
D
2
Pak
IRF3808SPbF
Tape and Reel Left
Tape and Reel Right
800
Absolute Maximum Ratings
Parameter
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
Max.
106
75
550
200
1.3
Units
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
DM
A
P
D
@T
C
= 25°C
Power Dissipation
W
W/°C
V
Linear Derating Factor
V
GS
E
AS
I
AR
Gate-to-Source Voltage
± 20
430
82
Single Pulse Avalanche Energy
Avalanche Current
mJ
A
E
AR
dv/dt
T
J
Repetitiv
e
A
valanch
e
E
nergy
Peak Diode Recovery dv/dt
Operating Junction and
See Fig.12a, 12b, 15, 16
5.5
mJ
V/ns
-55 to
+ 175
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
°C
300 (1.6mm from case )
Thermal Resistance
Parameter
Typ.
–––
Max.
0.75
Units
°C/W
R
θ
JC
R
θ
JA
Junction-to-Case
Junction-to-Ambient
(PCB Mounted, Steady State)
–––
40
1
N
ovember 01, 2013
IRF3808S/LPbF
Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
75 –––
–––
Conditions
V
GS
= 0V, I
D
= 250
μ
A
V
(BR)DSS
Drain-to-Source Breakdown Voltage
V
Δ
V
(BR)DSS
/
Δ
T
J
Breakdown Voltage Temp. Coefficient
––– 0.086
––– V/°C
Reference to 25°C, I
D
= 1mA
R
DS(on)
V
GS(th)
g
fs
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
–––
2.0
5.9 7.0
––– 4.0
m
Ω
V
GS
= 10V, I
D
= 82A
V
S
V
DS
= 10V, I
D
= 250
μ
A
V
DS
= 25V, I
D
= 82A
V
DS
= 75V, V
GS
= 0V
V
DS
= 60V, V
GS
= 0V, T
J
= 150°C
V
GS
= 20V
Forward Transconductance
100 –––
–––
––– ––– 20
––– –––
250
––– –––
200
––– –––
-200
––– 150
220
I
DSS
Drain-to-Source Leakage Current
μ
A
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
I
GSS
nA
V
GS
= -20V
Q
g
I
D
= 82A
Q
gs
Q
gd
t
d(on)
t
r
Gate-to-Source Charge
Gate-to-Drain (“Miller”) Charge
Turn-On Delay Time
Rise Time
–––
–––
–––
31
50
47
76
nC V
DS
= 60V
V
GS
= 10V
V
DD
= 38V
16 –––
––– 140
–––
––– 68
–––
––– 120
–––
I
D
= 82A
ns
t
d(off)
t
f
Turn-Off Delay Time
Fall Time
R
G
= 2.5
Ω
V
GS
= 10V
D
S
Between lead,
4.5
L
D
L
S
Internal Drain Inductance
Internal Source Inductance
–––
–––
–––
–––
6mm (0.25in.)
nH
G
from package
7.5
and center of die contact
C
iss
Input Capacitance
––– 5310
–––
––– 890
–––
––– 130
–––
––– 6010
–––
––– 570
–––
––– 1140
–––
V
GS
= 0V
C
oss
Output Capacitance
pF
V
DS
= 25V
C
rss
Reverse Transfer Capacitance
Output Capacitance
ƒ = 1.0MHz, See Fig. 5
C
oss
V
GS
= 0V,
V
DS
= 1.0V,
ƒ = 1.0MHz
V
GS
= 0V,
V
DS
= 60V,
ƒ = 1.0MHz
V
GS
= 0V, V
DS
= 0V to 60V
C
oss
Output Capacitance
C
oss
eff.
Effective Output Capacitance
ꢀ
Source-Drain Ratings and Characteristics
Parameter
Continuous Source Current
(Body Diode)
Min. Typ. Max. Units
Conditions
MOSFET symbol
D
I
S
––– –––
106
showing the
A
G
I
SM
Pulsed Source Current
(Body Diode)
integral reverse
––– –––
550
S
p-n junction diode.
V
SD
t
rr
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
––– ––– 1.3
––– 93 140
––– 340 510
V
T
J
= 25°C, I
S
= 82A, V
GS
= 0V
ns
T
J
= 25°C, I
F
= 82A
Q
rr
nC di/dt
= 100A/
μ
s
t
on
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
+L
D
)
Notes:
Repetitive rating;
pulse width limited by
max. junction temperature. (See fig. 11).
Starting T
J
= 25°C, L = 0.130mH
R
G
= 25
Ω
, I
AS
= 82A. (See Figure 12).
I
SD
≤
82A, di/dt
≤
310A/
μ
s, V
DD
≤
V
(BR)DSS
T
J
≤
175°C
ꢀ
C
oss
eff. is a fixed capacitance that gives the same charging time
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
Limited by T
Jmax
, see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
When mounted on 1″ square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to
application note #AN-994.
,
Pulse width
≤
400
μ
s; duty cycle
≤
2%.
2
N
ovember 01, 2013
IRF3808S/LPbF
1000
100
10
1000
100
10
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
TOP
TOP
BOTTOM
BOTTOM
4.5V
4.5V
20
μ
s PULSE WIDTH
20
μ
s PULSE WIDTH
°
°
T =
25
C
J
T =
175
J
C
1
1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
DS
V
, Drain-to-Source Voltage (V)
DS
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
3.0
1000.00
100.00
10.00
137A
=
I
D
2.5
2.0
1.5
1.0
0.5
0.0
T =
175°C
J
T =
25°C
J
V
= 15V
DS
20
μ
s PULSE WIDTH
V
= 10V
GS
-60 -40 -20
0
20 40 60 80
100 120 140 160 180
°
1.0
3.0
5.0
7.0
9.0
11.0
13.0
15.0
T ,
Junction Temperature
( C)
J
V
, Gate-to-Source Voltage (V)
GS
Fig 3.
Typical Transfer Characteristics
Fig 4.
Normalized On-Resistance
Vs. Temperature
3
N
ovember 01, 2013
IRF3808S/LPbF
12
10
8
100000
10000
1000
D
I
=
82A
V
C
= 0V,
f = 1 MHZ
GS
V
V
V
= 60V
= 37V
= 15V
DS
DS
DS
= C
+ C
,
C
SHORTED
iss
gs
gd
ds
C
= C
rss
gd
C
= C
+ C
oss
ds gd
Ciss
6
4
Coss
2
Crss
0
100
0
40
80
120
160
1
10
100
Q
, Total Gate Charge (nC)
G
V
, Drain-to-Source Voltage (V)
DS
Fig 6.
Typical Gate Charge Vs.
Fig 5.
Typical Capacitance Vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
1000.00
100.00
10.00
1.00
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
T
= 175°C
J
100
μ
sec
T
= 25°C
J
1msec
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
10msec
100
GS
1
0.10
1
10
1000
0.0
0.5
1.0
1.5
2.0
V
, Drain-toSource Voltage (V)
V
, Source-toDrain Voltage (V)
DS
SD
Fig 8.
Maximum Safe Operating Area
Fig 7.
Typical Source-Drain Diode
Forward Voltage
4
N
ovember 01, 2013
IRF3808S/LPbF
120
100
80
60
40
20
0
R
D
V
DS
V
GS
D.U.T.
R
G
+
V
DD
–
10V
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
Fig 10a.
Switching Time Test Circuit
V
DS
90%
25
50
75
100
125
150
175
T
, Case Temperature (°C)
C
10%
V
GS
Fig 9.
Maximum Drain Current Vs.
t
t
r
t
t
f
d(on)
d(off)
Case Temperature
Fig 10b.
Switching Time Waveforms
1
D = 0.50
0.20
0.1
0.10
0.05
P
DM
t
1
0.02
t
2
SINGLE PULSE
0.01
(THERMAL RESPONSE)
Notes:
1. Duty factor D =
t /
t
1
2
2. Peak T
= P
x Z
+ T
J
DM
thJC
C
0.01
0.00001
0.0001
0.001
0.01
0.1
1
10
t ,
Rectangular Pulse Duration (sec)
1
Fig 11.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
5
N
ovember 01, 2013
IRF3808S/LPbF
800
640
480
320
160
0
15V
I
D
TOP
34A
58A
82A
DRIVER
+
BOTTOM
L
V
DS
D.U.T
AS
R
G
V
DD
–
I
A
20V
0.01
Ω
t
p
Fig 12a.
Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
25
50
75
100
125
150
°
( C)
Starting Tj, Junction Temperature
I
AS
Fig 12c.
Maximum Avalanche Energy
Fig 12b.
Unclamped Inductive Waveforms
Vs. Drain Current
Q
G
10 V
Q
Q
3.5
GS
GD
V
G
3.0
2.5
2.0
1.5
1.0
I
= 250
μ
A
D
Charge
Fig 13a.
Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.
T
.
50K
Ω
.2
μ
F
12V
.3
μ
F
+
V
DS
D.U.
T
.
–
-75 -50 -25
0
25 50 75
100 125 150 175 200
V
GS
T ,
Temperature ( °C )
3mA
J
I
I
D
G
Current Sampling Resistors
Fig 14.
Threshold Voltage Vs. Temperature
Fig 13b.
Gate Charge Test Circuit
6
N
ovember 01, 2013
IRF3808S/LPbF
10000
1000
100
10
Allowed avalanche Current vs
avalanche pulsewidth, tav
Duty Cycle = Single Pulse
0.01
assuming
Tj = 25°C due to
Δ
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
0.05
0.10
1
0.1
1.0E-07
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15.
Typical Avalanche Current Vs.Pulsewidth
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T
jmax
. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
500
TOP
BOTTOM 10%
Duty Cycle
= 140A
Single Pulse
I
400
300
200
100
0
D
4. P
D (ave)
= Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. I
av
= Allowable avalanche current.
7.
Δ
T
=
Allowable rise in junction temperature, not to exceed
T
jmax
(assumed as 25°C in Figure 15, 16).
t
av =
Average time in avalanche.
25
50
75
100
125
150
175
D = Duty cycle in avalanche =
t
av
·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see figure 11)
Starting T
, Junction Temperature (°C)
J
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
D
T/ Z
thJC
I
av
= 2
D
T/ [1.3·BV·Z
th
]
Fig 16.
Maximum Avalanche Energy
E
AS (AR)
= P
D (ave)
·t
av
Vs. Temperature
7
N
ovember 01, 2013
IRF3808S/LPbF
Peak Diode Recovery dv/dt Test Circuit
+
–
Circuit Layout Considerations
•
Low Stray Inductance
•
Ground Plane
•
Low Leakage Inductance
Current T
r
a
nsformer
D.U.T
*
+
–
–
+
R
G
•
dv/dt controlled by R
G
•
I
SD
controlled by Duty Factor “D”
•
D.U.T. – Device Under Test
+
–
V
DD
V
GS
*
Reverse Polarity of D.U.T for P-Channel
Driver Gate Drive
P
.
W.
Period
Period
D =
P.W.
V
[
=10V
] ***
GS
D.U.
T
. I
W
aveform
SD
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.
T
. V
W
aveform
DS
Diode Recovery
dv/dt
V
DD
]
[
Re-Applied
Voltage
Body Diode
Forward Drop
Inductor Curent
I
[
]
SD
Ripple
≤
5%
***
V
GS
= 5.0V for Logic Level and 3V Drive Devices
Fig 17.
For N-channel
HEXFET
®
power MOSFETs
8
November 01, 2013
IRF3808S/LPbF
D
2
Pak (TO-263AB) Package Outline
Dimensions are shown in millimeters (inches)
D
2
Pak (TO-263AB) Part Marking Information
T
H
IS IS
A
N
I
RF530S
W
I
TH
P
A
R
T NU
M
B
ER
L
O
T CO
D
E 8024
IN
T
ERN
A
T
I
O
NAL
RE
C
T
I
F
I
ER
L
O
GO
A
S
SE
M
B
LED
O
N W
W
0
2, 2000
IN THE
A
S
SE
M
B
LY LI
N
E “L”
F
5
30S
DAT E
CO
D
E
Y
E
A
R 0 =
2
000
W
E
E K
02
A
S
SE
M
B
LY
L
O
T CODE
LI
N
E L
OR
P
A
R
T NU
M
B
ER
IN
T
ERN
A
T
I
O
NAL
RE
C
T
I
F
I
ER
L
O
GO
F
5
30S
DAT E
CO
D
E
P =
DES I
G
NAT
E
S
LE
A
D – F
R
EE
PR
O
D
U
C
T (O
P
T
I
O
N
A
L
)
Y
E
A
R 0 =
2
000
A
S
SE
M
B
LY
L
O
T CO
D
E
W
E
EK 02
A =
A
S S
E
M
B
LY S IT E
C
ODE
9
N
ovember 01, 2013
IRF3808S/LPbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
EX
A
M
P
L
E
: T
H
IS
IS
A
N
I
RL
3
103L
LOT
C
ODE 1789
P
A
R
T NU
M
B
ER
IN
T
E
R
N
A
T
I
O
NAL
RE
C
T
IFIER
L
O
GO
A
S
SE
M
B
LED
O
N WW 19, 1997
IN
T
H
E
A
S
SE
M
B
LY LINE “
C
”
D
A
T
E
C
ODE
Y
E
A
R 7 =
1
997
W
E
EK 19
Note: “
P
” in
a
s
s
e
mb
l
y li
n
e
pos
i
tion indi
c
ates
“L ead
–
F ree”
A
S
SE
M
B
LY
L
O
T CODE
LINE C
OR
P
A
R
T NU
M
B
E
R
INTERN
A
T
I
O
NAL
RE
C
T
IFIER
L
O
GO
D
A
T
E
C
ODE
P =
DE S IGNAT
E
S
LE
A
D-
F
REE
PR
O
D
U
C
T (O
P
TI
O
NA
L
)
YE
A
R 7 =
1
997
A
S
SE
M
B
LY
L
O
T CODE
W
E
EK 19
A =
A
S
SE
M
B
LY SITE
C
ODE
10
N
ovember 01, 2013
IRF3808S/LPbF
D
2
Pak
T
a
pe & Reel Information
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
0.368 (.0145)
0.342 (.0135)
FEED DIRECTION
TRL
11.60 (.457)
11.40 (.449)
1.85 (.073)
1.65 (.065)
24.30 (.957)
23.90 (.941)
15.42 (.609)
15.22 (.601)
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
NOTES :
1. COMFORMS
TO EIA-418.
2. CONTROLLING
DIMENSION: MILLIMETER.
3. DIMENSION
MEASURED @ HUB.
4. INCLUDES
FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
4
3
11
N
ovember 01, 2013
IRF3808S/LPbF
Qualification information
†
I
n
d
u
s
t
r
i
a
l
Qualification le
v
e
l
(
p
er
J
E
D
E
C
JES
D
47
F
††
g
u
i
d
e
l
in
e
s
)
TO-262 PAK
D2-PAK
N/A
MS L 1
Moisture Sensitivity Level
RoHS
c
o
m
pliant
(
p
er
J
E
D
E
C J-S T
D
-020D
††
Yes
)
†
Qualification standards can be found at International Rectifier’s web site:
http://www.irf.com/product-info/reliability
††
Applicable version of JEDEC standard at the time of product release
Revision History
Date
Comments
•
•
•
•
•
Updated datasheet with New IR corporate template
Removed note6 because update package ID from “75A” to “106A”-page 1 & 2
Added Odering information table-page 1
Corrected fig9-page 5
Added Qualification information table-page 12
11/1/2013
IR WORLD HEADQUARTERS:
101 N. Sepulveda Blvd., El Segundo, California 90245, USA
12
N
ovember 01, 2013
