Infineon-Technologies-IRF40H210

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Infineon-Technologies-IRF40H210
Strong
IR
FET™  
IRF40H210  
HEXFET

®

Power MOSFET  
Application  

Brushed Motor drive applications  

BLDC Motor drive applications  

Battery powered circuits  

Half-bridge and full-bridge topologies  

Synchronous rectifier applications  

Resonant mode power supplies  

OR-ing and redundant power switches  

DC/DC and AC/DC converters  

DC/AC Inverters  
V

DSS  

R

DS(on)

typ.  
max  
40V  
1.4m
  
1.7m
  
I

D (Silicon Limited)  

I

D (Package Limited)  

201A
 
100A  
Benefits  

Improved Gate,
 
Avalanche and Dynamic dV/dt Ruggedness  

Fully Characterized Capacitance and Avalanche SOA  

Enhanced body diode dV/dt and dI/dt Capability  

Lead-Free, RoHS Compliant  
PQFN 5 x 6 mm  
Base part number  
Package Type  
Standard Pack  
Form  
Orderable Part Number  
Quantity  
IRF40H210  
PQFN 5mm x 6mm  
Tape and Reel  
4000  
IRF40H210  
225  
200  
175  
150  
125  
100  
75  
6
5
4
3
2
1
0
I
= 100A  
D
Limited by package  
T
T
= 125°C  
= 25°C  
J
50  
25  
J
0
25  
50  
75  
100  
125  
150  
2
4
6
8
10 12 14 16 18 20  
T
, Case Temperature (°C)  
C
V
Gate -to -Source Voltage
 
(V)  
GS,  
Fig 2.
 
Maximum Drain Current vs. Case Temperature  
Fig 1.
 
Typical On-Resistance vs. Gate Voltage  
1
© 2015 International Rectifier  
April 1, 2015  

IRF40H210  
Absolute Maximum Rating  
Symbol  
I

D

@ T

C(Bottom)

= 25°C
 
Continuous Drain Current, V

GS

@ 10V  
Parameter  
Max.  
201
 
127
  
Units  
I

D

@ T

C(Bottom)

= 100°C Continuous Drain Current, V

GS

@ 10V  
A
I

D

@ T

C(Bottom)

= 25°C
 
Continuous Drain Current, V

GS

@ 10V(Wire Bond Limited)  
100  
400*  
125  
1.0  
I

DM  

Pulsed Drain Current
  
Maximum Power Dissipation  
Linear Derating Factor  
P

D

@T

C

= 25°C  
W
W/°C  
V
V

GS  

Gate-to-Source Voltage  
± 20  
T

J  

T

STG  

Operating Junction and  
Storage Temperature Range  
-55 to
 
+ 150  
°C  
Avalanche Characteristics  
E

AS (Thermally limited)  

E

AS (Thermally limited)  

I

AR  

E

AR  

149  
370  
Single Pulse Avalanche Energy
  
Single Pulse Avalanche Energy
 
  
Avalanche Current
  
mJ  
A
mJ  
See Fig 15, 16, 23a, 23b  
Repetitive Avalanche Energy
  
Thermal Resistance  
Symbol  
R

JC

(Bottom)  
R

JC

(Top)  
Parameter  
Junction-to-Case
  
Typ.  
–––  
–––  
–––  
–––  
Max.  
1.0  
18  
Units  
Junction-to-Case
  
°C/W  
Junction-to-Ambient
  
Junction-to-Ambient
  
R

JA  

33  
R

JA

(<10s)  
20  
Static @ T

J

= 25°C (unless otherwise specified)  
Symbol  
V

(BR)DSS  

Parameter  
Drain-to-Source Breakdown Voltage  
Breakdown Voltage Temp. Coefficient  
Min. Typ.
 
Max. Units  
Conditions  
V

GS

= 0V, I

D

= 250µA  
––– mV/°C
 
Reference to 25°C, I

D

= 1mA
  
40  
––– –––  
V
–––  
42  
V

(BR)DSS

/
T

J  

R

DS(on)  

Static Drain-to-Source On-Resistance  
–––  
–––  
2.2 –––  
––– –––  
––– ––– 150  
––– ––– 100  
––– –––
 
-100  
1.4  
2.3  
1.7  
–––  
3.7  
1.0  
V

GS

= 10V, I

D

= 100A
  
m
  
V
V

GS

= 6.0V, I

D

= 50A
  
V

GS(th)  

I

DSS  

Gate Threshold Voltage  
Drain-to-Source Leakage Current  
V

DS

= V

GS

, I

D

= 150µA  
V

DS

= 40 V, V

GS

= 0V  
µA  
V

DS

= 40V,V

GS

= 0V,T

J

=125°C  
V

GS

= 20V  

GS

= -20V  
I

GSS  

Gate-to-Source Forward Leakage  
Gate-to-Source Reverse Leakage  
Gate Resistance  
nA  
V
R

G  

–––  
2.6  
–––  
  
Notes:  
Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 100A  
by source bonding technology. Note that current limitations arising from heating of the device leads may occur with  
some lead mounting arrangements. (Refer to AN-1140)  
Repetitive rating; pulse width limited by max. junction temperature.  
Limited by T

Jmax

, starting T

J

= 25°C, L = 0.030mH, R

G

= 50
, I

AS

= 100A, V

GS

=10V.  
I

SD

100A, di/dt
1117A/µs, V

DD

V

(BR)DSS

, T

J


150°C.  
Pulse width
400µs; duty cycle
2%.  
C

oss

eff. (TR) is a fixed capacitance that gives the same charging time as C

oss

while V

DS

is rising from 0 to 80% V

DSS  

.
C

oss

eff. (ER) is a fixed capacitance that gives the same energy as C

oss

while V

DS

is rising from 0 to 80% V

DSS  

.
R

is measured at T

J

approximately 90°C.  
When mounted on 1 inch square
 
PCB (FR-4). Please refer to AN-994 for more details:  
Limited by T

Jmax

, starting T

J

= 25°C, L = 1mH, R

G

= 50
, I

AS

= 27A, V

GS

=10V.  
Pulse drain current is limited by source bonding technology.  
*
2
© 2015 International Rectifier  
April 1, 2015  

IRF40H210  
Dynamic Electrical
 
Characteristics @ T

J

= 25°C (unless otherwise specified)  
Symbol  
gfs  
Parameter  
Forward Transconductance  
Total Gate Charge  
Min.  
113  
–––  
–––  
–––  
–––  
–––  
–––  
Typ. Max.
 
Units  
Conditions  
–––  
101  
30  
–––  
152  
–––  
–––  
–––  
–––  
–––  
S
V

DS

= 10V, I

D

= 100A  
Q

g  

I

D

= 100A  
V

DS

= 20V  
V

GS

= 10V  
Q

gs  

Gate-to-Source Charge  
Gate-to-Drain Charge  
Total Gate Charge Sync. (Qg – Qgd)  
Turn-On Delay Time  
nC  
Q

gd  

31  
Q

sync  

t

d(on)  

t

r  

70  
9.2  
25  
V

DD

= 20V  
I

D

= 30A  
Rise Time  
ns  
t

d(off)  

t

f  

Turn-Off Delay Time  
Fall Time  
–––  
–––  
–––  
–––  
–––  
65  
34  
–––  
–––  
–––  
–––  
–––  
R

G

= 2.7
  
V

GS

= 10V
  
C

iss  

C

oss  

C

rss  

Input Capacitance  
Output Capacitance  
Reverse Transfer Capacitance  
5406  
805  
518  
V

GS

= 0V  
V

DS

= 25V  
ƒ = 1.0MHz,
 
See Fig.7  
pF  
Effective Output Capacitance  
(Energy Related)  
C

oss eff.(ER)  

–––  
–––  
962  
–––  
–––  
V

GS

= 0V, VDS = 0V to 32V
  
V

GS

= 0V, VDS = 0V to 32V
  
C

oss eff.(TR)  

Output Capacitance (Time Related)  
1179  
Diode Characteristics  
Symbol  
Parameter  
Min.  
Typ. Max.
 
Units  
Conditions  
D
Continuous Source Current  
(Body Diode)  
Pulsed Source Current  
(Body Diode)
  
MOSFET symbol  
showing the  
integral reverse  
p-n junction diode.  
I

S  

–––  
––– 100
  
G
A
S
I

SM  

–––  
–––  
–––  
0.8  
400*  
1.2  
V

SD  

Diode Forward Voltage  
V
T

J

= 25°C,I

S

= 100A,V

GS

= 0V
  
dv/dt  
Peak Diode Recovery dv/dt
  
–––  
–––  
–––  
–––  
–––  
6.2  
21  
22  
32  
38  
––– V/ns
 
T

J

= 150°C,I

S

= 100A,V

DS

= 40V  
–––  
–––  
–––  
–––  
T

J

= 25°C  
V

R

= 34V,  
I

F

= 100A  
di/dt = 100A/µs
  
t

rr  

Reverse Recovery Time  
ns  
T

J

= 125°C  
T

J

= 25°C
 
Q

rr  

Reverse Recovery Charge  
Reverse Recovery Current  
nC  
A
T

J

= 125°C  
T

J

= 25°C
 
  
I

RRM  

–––  
1.0  
–––  
3
© 2015 International Rectifier  
April 1, 2015  

IRF40H210  
10000  
1000  
100  
10  
10000  
1000  
100  
10  
VGS  
15V  
10V  
8.0V  
7.0V  
6.0V  
5.0V  
4.5V  
4.25V  
VGS  
15V  
10V  
8.0V  
7.0V  
6.0V  
5.0V  
4.5V  
4.25V  
TOP  
TOP  
BOTTOM  
BOTTOM  
4.25V  
4.25V  
60µs  
1
60µs  
PULSE WIDTH  
PULSE WIDTH  
Tj = 150°C  
Tj = 25°C  
1
0.1  
0.1  
1
10  
100  
0.1  
1
10  
100  
V
, Drain-to-Source Voltage (V)  
V
, Drain-to-Source Voltage (V)  
DS  
DS  
Fig 4.
 
Typical Output Characteristics  
Fig 3.
 
Typical Output Characteristics  
2.0  
1.6  
1.2  
0.8  
0.4  
10000  
1000  
100  
10  
I
= 100A  
= 10V  
D
V
GS  
T
= 150°C  
J
T
= 25°C  
J
1
V
= 10V  
DS  
60µs PULSE WIDTH  
0.1  
2
4
6
8
10  
-60 -40 -20  
T
0
20 40 60 80
 
100 120 140 160  
, Junction Temperature (°C)  
J
V
, Gate-to-Source Voltage (V)  
GS  
Fig 6.
 
Normalized On-Resistance vs. Temperature  
Fig 5.
 
Typical Transfer Characteristics  
100000  
10000  
1000  
14.0  
V
C
= 0V,  
f = 1 MHZ  
GS  
I
= 100A  
= C
 
+ C
 
, C
 
SHORTED  
D
iss  
gs  
gd ds  
12.0  
10.0  
8.0  
C
= C  
rss  
gd  
V
= 32V  
DS  
C
= C
 
+ C  
oss  
ds  
gd  
VDS= 20V  
C
iss  
C
6.0  
oss  
rss  
C
4.0  
2.0  
100  
0.0  
0.1  
1
10  
100  
0
20  
40  
60  
80  
100 120 140  
V
, Drain-to-Source Voltage (V)  
Q
, Total
 
Gate Charge (nC)  
DS  
G
Fig 8.
 
Typical Gate Charge vs.  
Fig 7.
 
Typical Capacitance vs. Drain-to-Source Voltage  
Gate-to-Source Voltage  
4
© 2015 International Rectifier  
April 1, 2015  

IRF40H210  
10000  
1000  
100  
10  
OPERATION IN THIS AREA  
LIMITED BY R
 
(on)  
1000  
100  
10  
DS  
100µsec  
1msec  
Limited by Package  
T
= 150°C  
J
T
= 25°C  
V
1
J
10msec  
DC  
1
Tc = 25°C  
0.1  
0.01  
= 0V  
Tj = 150°C  
Single Pulse  
GS  
0.1  
0.1  
1
10  
0.1  
0.4  
0.7  
1.0  
1.3  
1.6  
1.9  
V
, Drain-to-Source Voltage (V)  
V
, Source-to-Drain Voltage (V)  
DS  
SD  
Fig 10.
 
Maximum Safe Operating Area  
Fig 9.
 
Typical Source-Drain Diode Forward Voltage  
49  
0.8  
Id = 1.0mA  
47  
45  
43  
41  
39  
37  
0.6  
0.4  
0.2  
0.0  
-60 -40 -20  
0
T
20 40 60 80
 
100 120 140 160  
, Temperature ( °C )  
0
5
10 15 20 25 30 35 40 45  
J
V
Drain-to-Source Voltage (V)  
DS,  
Fig 11.
 
Drain-to-Source Breakdown Voltage  
Fig 12.
 
Typical C

oss

Stored Energy  
14  
VGS = 5.0V  
VGS = 6.0V  
VGS = 7.0V  
VGS = 8.0V  
VGS = 10V  
12  
10  
8
6
4
2
0
0
50  
100  
150  
200  
I
, Drain Current (A)  
D
Fig 13.
 
Typical On-Resistance vs. Drain Current  
© 2015 International Rectifier
 

5
April 1, 2015  

IRF40H210  
10  
1
D = 0.50  
0.20  
0.10  
0.05  
0.1  
0.02  
0.01  
0.01  
0.001  
SINGLE PULSE  
( THERMAL RESPONSE )  
Notes:  
1. Duty Factor D = t1/t2  
2. Peak Tj = P dm x Zthjc + Tc  
1E-006  
1E-005  
0.0001  
0.001  
0.01  
0.1  
1
t
, Rectangular Pulse Duration (sec)  
1
Fig 14.
 
Maximum Effective Transient Thermal Impedance, Junction-to-Case  
1000  
100  
10  
Allowed avalanche Current vs avalanche  
pulsewidth, tav, assuming
Tj = 125°C and  
Tstart =25°C (Single Pulse)  
1
Allowed avalanche Current vs avalanche  
pulsewidth, tav, assuming

j = 25°C and  
Tstart = 125°C.  
0.1  
1.0E-06  
1.0E-05  
1.0E-04  
1.0E-03  
1.0E-02  
1.0E-01  
tav (sec)  
Fig 15.
 
Avalanche Current vs. Pulse Width  
160  
140  
120  
100  
80  
TOP  
Single Pulse  
Notes on Repetitive Avalanche Curves , Figures 15, 16:  
(For further info, see AN-1005 at www.irf.com)  
1.Avalanche failures assumption:  
BOTTOM 1.0%
 
Duty Cycle  
I
= 100A  
D
Purely a thermal phenomenon and failure occurs at a  
temperature far in excess of T

jmax

. This is validated for every  
part type.  
2. Safe operation in Avalanche is allowed as long asT

jmax

is not  
exceeded.  
3. Equation below based on circuit and waveforms shown in Figures  
23a, 23b.  
4. P

D (ave)

= Average power dissipation per single avalanche pulse.  
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage  
increase during avalanche).  
60  
40  
6. I

av

= Allowable avalanche current.  
7.
T = Allowable rise in junction temperature, not to exceed T

jmax  

(assumed as 25°C in Figure 15, 16).  
20  
0
t

av

= Average time in avalanche.  
25  
50  
75  
100  
125  
150  
D = Duty cycle in avalanche =
 
tav ·f  
Z

thJC

(D, t

av

) = Transient thermal resistance, see Figures 13)  
Starting T
 
, Junction Temperature (°C)  
J
PD (ave) = 1/2 ( 1.3·BV·I

av

) =
T/ Z

thJC  

I

av

= 2
T/ [1.3·BV·Z

th

]  
E

AS (AR)

= P

D (ave)· av  

t
Fig 16.
Maximum Avalanche Energy vs. Temperature  
6
© 2015 International Rectifier  
April 1, 2015  

IRF40H210  
4.5  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
10  
8
I
= 60A  
= 34V  
F
V
R
T =
 
25°C  
J
T =
 
125°C  
J
6
4
ID = 150µA  
ID = 250µA  
ID = 1.0mA  
ID = 1.0A  
2
0
-75 -50 -25  
T
0
25 50 75
 
100 125 150  
0
200  
400  
600  
800  
1000  
, Temperature ( °C )  
di /dt
 
(A/µs)  
J
F
Fig 17.
 
Threshold Voltage vs. Temperature  
Fig 18.
 
Typical Recovery Current vs. dif/dt  
10  
250  
I
= 100A  
= 34V  
I
= 60A  
= 34V  
F
F
V
V
R
R
8
6
4
2
0
200  
150  
100  
50  
T =
 
25°C  
T =
 
25°C  
J
J
T =
 
125°C  
J
T =
 
125°C  
J
0
0
200  
400  
600  
800  
1000  
0
200  
400  
600  
800  
1000  
di /dt
 
(A/µs)  
di /dt
 
(A/µs)  
F
F
Fig 19.
 
Typical Recovery Current vs. dif/dt  
Fig 20.
 
Typical Stored Charge vs. dif/dt  
200  
I
= 100A  
F
V
= 34V  
R
T =
 
25°C  
J
150  
100  
50  
T =
 
125°C  
J
0
0
200  
400  
600  
800  
1000  
di /dt
 
(A/µs)  
F
Fig 21.
 
Typical Stored Charge vs. dif/dt  
© 2015 International Rectifier
 

7
April 1, 2015  

IRF40H210  
Fig 22.
Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET

®

Power MOSFETs  
V
(BR)DSS  
15V  
t
p
DRIVER  
+
L
V
DS  
D.U.T  
AS  
R
G
V
DD  
–
I
A
20V  
0.01  
I
t
p
AS  
Fig 23a.
 
Unclamped Inductive Test Circuit  
Fig 23b.
 
Unclamped Inductive Waveforms  
Fig 24a.
 
Switching Time Test Circuit  
Fig 24b.
 
Switching Time Waveforms  
Id  
Vds  
Vgs  
VDD  
Vgs(th)  
Qgs1  
Qgs2  
Qgd  
Qgodr  
Fig 25b.
 
Gate Charge Waveform  
Fig 25a.
 
Gate Charge Test Circuit  
8
© 2015 International Rectifier  
April 1, 2015  

IRF40H210  
PQFN 5×6 Outline “B” Package Details  
For more information on board mounting, including footprint and stencil recommendation, please refer to application note  
For more information on package inspection techniques, please refer to application note AN-1154:  
PQFN 5×6 Part Marking  
INTERNATIONAL  
RECTIFIER LOGO  
DATE CODE  
PART NUMBER  
XXXX  
(“4 or 5 digits”)  
ASSEMBLY  
SITE CODE  
(Per SCOP 200-002)  
MARKING CODE  
XYWWX  
XXXXX  
(Per Marking Spec)  
PIN 1  
IDENTIFIER  
LOT CODE  
(Eng Mode – Min last 4 digits of EATI#)  
(Prod Mode – 4 digits of SPN code)  
Note: For the most current drawing please refer to IR website at

9
© 2015 International Rectifier  
April 1, 2015  

IRF40H210  
PQFN Tape and Reel  
REEL DIMENSIONS  
TAPE DIMENSIONS  
CODE  
Ao  
DESCRIPTION  
Dimension design to accommodate the component width  
Dimension design to accommodate the component lenght  
Dimension design to accommodate the component thickness  
Overall width of the carrier tape  
Bo  
Ko  
W
P
1
Pitch between successive cavity centers  
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE  
Note: All
 
dimension are nominal  
Package  
Type  
Reel  
Diameter  
(Inch)  
QTY  
Reel  
Width  
W1  
Ao  
Bo  
Ko  
P1  
W
Pin 1  
(mm)  
(mm)  
(mm)  
(mm)  
(mm)  
Quadrant  
(mm)  
5 X 6 PQFN  
13  
4000  
12.4  
6.300  
5.300  
1.20  
8.00  
12  
Q1  
Note: For the most current drawing please refer to IR website at

10  
© 2015 International Rectifier  
April 1, 2015  

IRF40H210  
Qualification Information

†  

Qualification Level  
Industrial  
(per JEDEC JESD47F

††

guidelines)  
MSL1  
PQFN 5mm x 6mm  
Moisture Sensitivity Level  
RoHS Compliant  
(per JEDEC J-STD-020D

††)  

Yes  
† Qualification
 
standards can be found at International Rectifier’s web site:

†† Applicable version of JEDEC standard at the time of product release.  
IR WORLD HEADQUARTERS:
101 N. Sepulveda Blvd., El Segundo, California 90245, USA  
To contact International Rectifier, please visit

11  
© 2015 International Rectifier  
April 1, 2015