Infineon-Technologies-IRF4905LPBF
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PD – 97034
IRF4905SPbF
IRF4905LPbF
HEXFET
®
Power MOSFET
Features
O
Advanced Process Technology
Ultra Low On-Resistance
150°C Operating Temperature
Fast Switching
D
O
O
O
O
O
V
DSS
= -55V
R
DS(on)
= 20m
Ω
Repetitive Avalanche Allowed up to Tjmax
Some Parameters Are Differrent from
IRF4905S
G
I
D
= -42A
S
O
Lead-Free
D
D
Description
Features of this design
are a 150°C junction oper-
ating temperature, fast switching speed and im-
proved repetitive avalanche rating . These features
combine to make this design an extremely efficient
and reliable device for use in
a wide variety of other
applications.
S
S
D
D
G
G
D
2
Pak
TO-262
IRF4905LPbF
IRF4905SPbF
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Parameter
Max.
Units
Continuous Drain Current, V
GS
@ 10V
(Silicon Limited)
Continuous Drain Current, V
GS
@ 10V
(Silicon Limited)
Continuous Drain Current, V
GS
@ 10V
(Package Limited)
Pulsed Drain Current
-70
I
I
I
I
@ T
= 25°C
C
D
D
D
-44
@ T
= 100°C
C
A
-42
@ T
= 25°C
C
-280
DM
170
P
@T =
25°C Power
Dissipation
C
W
W/°C
V
D
1.3
Linear Derating Factor
± 20
V
Gate-to-Source Voltage
GS
E
AS (Thermally limited)
140
790
Single Pulse Avalanche Energy
Single Pulse Avalanche Energy Tested Value
Avalanche Current
mJ
E
AS
(Tested )
I
AR
See Fig.12a, 12b, 15, 16
A
E
AR
Repetitive Avalanche Energy
Operating Junction and
mJ
-55 to
+ 150
T
T
J
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting Torque, 6-32 or M3 screw
°C
STG
300 (1.6mm from case )
10 lbf
in (1.1N
m)
Thermal Resistance
Parameter
Typ.
–––
Max.
0.75
40
Units
R
θ
JC
R
θ
JA
Junction-to-Case
Junction-to-Ambient (PCB Mount, steady state)
–––
1
8/5/05
IRF4905S/L
Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
Parameter
Min. Typ. Max.
Units
Conditions
V
GS
= 0V, I
D
= -250µA
V
(BR)DSS
∆
V
(BR)DSS
/
∆
T
J
R
DS(on)
V
GS(th)
Drain-to-Source Breakdown Voltage
-55
–––
–––
V
Reference to 25°C, I
D
= -1mA
Breakdown Voltage Temp. Coefficient
––– -0.054 –––
V/°C
V
GS
= -10V, I
D
= -42A
m
Ω
V
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
–––
-2.0
19
–––
–––
–––
–––
20
V
DS
= V
GS
, I
D
= -250µA
V
DS
= -25V, I
D
= -42A
-4.0
–––
-25
gfs
Forward Transconductance
S
V
V
DS
= -55V, V
GS
= 0V
I
DSS
Drain-to-Source Leakage Current
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
µA
DS
= -44V, V
GS
= 0V, T
J
= 125°C
––– -200
––– 100
––– -100
V
GS
= -20V
GS
= 20V
I
D
= -42A
DS
= -44V
I
GSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
nA
nC
V
Q
g
Q
gs
Q
gd
t
d(on)
t
r
120
32
53
20
99
51
64
7.5
180
–––
–––
–––
–––
–––
–––
–––
V
Gate-to-Source Charge
Gate-to-Drain (“Miller”) Charge
Turn-On Delay Time
V
GS
= -10V
V
DD
= -28V
I
D
= -42A
Rise Time
R
G
= 2.6
Ω
V
GS
= -10V
nH Between
lead,
and center of die contact
V
GS
= 0V
DS
= -25V
t
d(off)
t
f
Turn-Off Delay Time
ns
Fall Time
L
S
Internal Source Inductance
C
iss
C
oss
C
rss
C
oss
C
oss
Input Capacitance
––– 3500 –––
––– 1250 –––
V
Output Capacitance
ƒ = 1.0MHz
Reverse Transfer Capacitance
Output Capacitance
–––
––– 4620 –––
––– 940 –––
––– 1530 –––
450
–––
pF
V
GS
= 0V,
V
DS
= -1.0V,
ƒ = 1.0MHz
V
GS
= 0V,
V
DS
= -44V,
ƒ = 1.0MHz
Output Capacitance
V
GS
= 0V, V
DS
= 0V to -44V
C
oss
eff.
Effective Output Capacitance
Source-Drain Ratings and Characteristics
Parameter
Min. Typ. Max.
Units
Conditions
MOSFET symbol
I
Continuous Source Current
–––
–––
-42
S
showing the
(Body Diode)
A
integral reverse
I
Pulsed Source Current
(Body Diode)
–––
––– -280
SM
p-n junction diode.
T =
25°C, I
= -42A, V
= 0V
V
t
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
–––
–––
–––
–––
61
-1.3
92
V
J
S
GS
SD
T =
25°C, I
= -42A, V
DD
= -28V
ns
nC
J
F
rr
di/dt = -100A/µs
Q
150
220
rr
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
t
on
2
IRF4905S/L
1000
100
10
1000
100
10
VGS
-15V
-10V
-8.0V
-7.0V
-6.0V
-5.5V
-5.0V
-4.5V
VGS
TOP
TOP
-15V
-10V
-8.0V
-7.0V
-6.0V
-5.5V
-5.0V
-4.5V
BOTTOM
BOTTOM
-4.5V
-4.5V
≤
60µs PULSE WIDTH
Tj = 25°C
≤
60µs PULSE WIDTH
Tj = 150°C
1
1
0.1
1
10
100
1000
0.1
1
10
100
1000
-V ,
Drain-to-Source Voltage (V)
-V ,
Drain-to-Source Voltage (V)
DS
DS
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
1000.0
100.0
10.0
1.0
40
T
= 25°C
T
= 25°C
J
J
T
= 150°C
J
30
20
10
0
T
= 150°C
J
V
= -25V
DS
≤
60µs PULSE WIDTH
V
= -10V
DS
380µs PULSE WIDTH
0.1
3
4
5
6
7
8
9
10 11 12 13 14
0
20
40
60
80
-V ,
Gate-to-Source Voltage (V)
GS
-I Drain-to-Source
Current (A)
D,
Fig 3.
Typical Transfer Characteristics
Fig 4.
Typical Forward Transconductance
Vs. Drain Current
3
IRF4905S/L
7000
20
16
12
8
V
C
= 0V,
f = 1 MHZ
GS
I
= -42A
= C
+ C
, C
SHORTED
D
iss
gs
gd ds
6000
5000
4000
3000
2000
1000
0
V
= -44V
C
= C
DS
rss
gd
VDS= -28V
VDS= -11V
C
= C
+ C
oss
ds
gd
Ciss
Coss
Crss
4
0
0
40
80
120
160
200
1
10
100
Q
Total Gate Charge (nC)
G
-V ,
Drain-to-Source Voltage (V)
DS
Fig 6.
Typical Gate Charge Vs.
Fig 5.
Typical Capacitance Vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
1000.0
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
100.0
10.0
1.0
T
= 150°C
100µsec
10msec
J
1msec
LIMITED BY PACKAGE
T
= 25°C
J
DC
Tc = 25°C
Tj = 150°C
Single Pulse
V
= 0V
GS
1.6
1
0.1
0
1
10
100
0.0
0.4
0.8
1.2
2.0
-V
DS
, Drain-toSource Voltage (V)
-V ,
Source-to-Drain Voltage (V)
SD
Fig 8.
Maximum Safe Operating Area
Fig 7.
Typical Source-Drain Diode
Forward Voltage
4
IRF4905S/L
2.0
1.5
1.0
0.5
80
60
40
20
0
I
= -42A
LIMITED BY PACKAGE
D
V
= -10V
GS
25
50
T
75
100
125
150
-60 -40 -20
T
0
20 40 60 80
100 120 140 160
, Case Temperature (°C)
C
, Junction Temperature (°C)
J
Fig 10.
Normalized On-Resistance
Fig 9.
Maximum Drain Current Vs.
Vs. Temperature
Case Temperature
1
D = 0.50
0.20
0.1
0.10
0.05
R
1
R
2
R
2
R
3
R
3
Ri (°C/W)
τ
i (sec)
0.1165 0.000068
R
1
τ
J
τ
J
τ
C
τ
τ
0.02
0.01
τ
1
τ
1
τ
2
τ
2
3
τ
3
0.3734 0.002347
0.2608 0.014811
0.01
Ci=
τ
i
/
Ri
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 11.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
5
IRF4905S/L
L
V
DS
600
500
400
300
200
100
0
I
D.U.T
AS
R
D
G
V
DD
A
TOP
-17A
-30A
-42A
I
DRIVER
-20V
BOTTOM
0.01
t
Ω
p
15V
Fig 12a.
Unclamped Inductive Test Circuit
I
AS
25
50
75
100
125
150
Starting T
, Junction Temperature (°C)
J
t
p
V
(BR)DSS
Fig 12c.
Maximum Avalanche Energy
Fig 12b.
Unclamped Inductive Waveforms
Vs. Drain Current
Q
G
3.6
10V
Q
Q
GD
GS
V
G
3.2
2.8
2.4
2.0
Charge
I
= -250µA
D
Fig 13a.
Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.
T
.
50K
Ω
.2
µ
F
12V
.3
µ
F
–
V
+
DS
D.U.
T
.
V
GS
-75 -50 -25
0
25
50
75 100
125 150
-3mA
T
, Temperature ( °C )
J
I
I
D
G
Current Sampling Resistors
Fig 14.
Threshold Voltage Vs. Temperature
Fig 13b.
Gate Charge Test Circuit
6
IRF4905S/L
1000
100
10
Duty Cycle = Single Pulse
0.01
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming
∆
Tj = 25°C due to
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
0.05
0.10
1
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15.
Typical Avalanche Current Vs.Pulsewidth
160
120
80
40
0
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T
jmax
. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. P
D (ave)
= Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. I
av
= Allowable avalanche current.
TOP
BOTTOM 1%
Duty Cycle
= -42A
Single Pulse
I
D
7.
∆
T
=
Allowable rise in junction temperature, not to exceed
T
jmax
(assumed as 25°C in Figure 15, 16).
t
av =
Average time in avalanche.
25
50
75
100
125
150
D = Duty cycle in avalanche =
t
av
·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see figure 11)
Starting T
, Junction Temperature (°C)
J
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
D
T/ Z
thJC
I
av
= 2
D
T/ [1.3·BV·Z
th
]
Fig 16.
Maximum Avalanche Energy
E
AS (AR)
= P
D (ave)
·t
av
Vs. Temperature
7
IRF4905S/L
Driver Gate Drive
P.W.
P
.
W.
Period
Period
D =
D.U.T
**
+
*
=10V
V
GS
Circuit Layout Considerations
•
Low Stray Inductance
•
Ground Plane
•
Low Leakage Inductance
Current Transformer
–
D.U.
T
. I
W
aveform
SD
+
–
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
–
+
D.U.
T
. V
W
aveform
DS
Diode Recovery
dv/dt
V
DD
V
DD
Re-Applied
Voltage
•
dv/dt controlled by R
G
R
G
+
–
Body Diode
Forward Drop
•
Driver same type as D.U.T.
•
I
SD
controlled by Duty Factor “D”
•
D.U.T. – Device Under Test
Inductor Curent
I
SD
Ripple
≤
5%
**
Reverse Polarity of D.U.T for P-Channel
*
V
GS
= 5V for Logic Level Devices
Fig 17.
Peak Diode Recovery dv/dt Test Circuit
for P-Channel
HEXFET
®
Power MOSFETs
R
D
V
DS
V
GS
D.U.T.
R
G
–
+
V
DD
V
GS
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
Fig 18a.
Switching Time Test Circuit
t
t
r
t
t
f
d(on)
d(off)
V
GS
10%
90%
V
DS
Fig 18b.
Switching Time Waveforms
8
IRF4905S/L
D
2
Pak Package Outline
(Dimensions are shown in millimeters (inches))
D
2
Pak Part Marking Information
THIS IS
A
N
I
RF530S
W
I
T
H
P
A
R
T NU
M
B
ER
L
O
T CODE 8024
IN
T
ER
N
A
T
I
O
N
A
L
RE
C
T
I
FIER
L
O
GO
A
S
SE
M
B
LED
O
N WW
0
2, 2000
IN THE
A
S
SE
M
B
LY LINE “L”
F
5
30S
DA
T
E
C
ODE
Y
E
A
R 0 =
2
000
W
E
EK 02
Note: “P” in
a
s
s
e
mb
l
y line
po
s
i
t
ion indic
a
tes
“
L
e
ad
–
F
r
e
e”
A
S
SE
M
B
LY
L
O
T CODE
LINE L
OR
P
A
R
T NU
M
B
ER
DA
T
E
C
ODE
IN
T
ER
N
A
T
I
O
NAL
RE
C
T
IFIER
L
O
GO
F
5
30S
P =
DE S I
G
N
A
T E S
L E AD
–
F RE E
PR
O
D
U
C
T (O
P
T
I
O
N
A
L
)
Y
E
A
R 0 =
2
000
A
S
SE
M
B
LY
L
O
T CODE
W
E
EK 02
A=
A
S
SE
M
B
LY
SITE
C
ODE
9
IRF4905S/L
TO-262 Package Outline
(Dimensions are shown in millimeters (inches))
IGBT
1- GATE
2- COLLECTOR
3- EMITTER
4- COLLECTOR
TO-262 Part Marking Information
EX
A
M
P
LE: THIS
IS
A
N
I
RL3103L
L
O
T CODE 1789
A
S
SE
M
B
LED
O
N WW 19, 1997
IN THE
A
S
SE
M
B
LY LI
N
E “C”
P
A
R
T NU
M
B
ER
IN
T
ERN
A
T
I
O
NAL
RE
C
T
IFIER
L
O
GO
D
A
T
E
C
ODE
YE
A
R 7 =
1997
WE
E
K
19
Note: “P” in
a
s
s
e
mb
l
y line
pos
i
tion indi
c
ates
“L ead
–
F r
e
e”
AS S E MB
L
Y
L
O
T CODE
LINE C
OR
P
A
R
T NU
M
B
ER
IN
T
ER
N
A
T
I
O
N
A
L
RE
C
T
IFIER
L
O
GO
DA
T
E
C
ODE
P =
DE S IGNAT E S
L E AD-F
R
E E
PR
O
D
U
C
T (O
P
T
I
O
N
A
L
)
Y
E
A
R 7 =
1997
AS S E M
B
L Y
L
O
T CODE
W
E
EK 19
A =
A
S S E MB L Y S
I
T E
C
ODE
10
IRF4905S/L
D
2
Pak
T
a
pe & Reel Information
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
0.368 (.0145)
0.342 (.0135)
FEED DIRECTION
1.85 (.073)
11.60 (.457)
11.40 (.449)
1.65 (.065)
24.30 (.957)
23.90 (.941)
15.42 (.609)
15.22 (.601)
TRL
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
NOTES :
1. COMFORMS
TO EIA-418.
2. CONTROLLING
DIMENSION: MILLIMETER.
3. DIMENSION
MEASURED @ HUB.
4. INCLUDES
FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
4
3
Notes:
ꢀ
Limited by T
Jmax
, see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
Repetitive rating;
pulse width limited by
max. junction temperature. (See fig. 11).
Limited by T
Jmax
, starting T
J
= 25°C, L = 0.16mH
R
G
= 25
Ω
, I
AS
= -42A, V
GS
=-10V. Part not
recommended for use above this value.
Pulse width
≤
1.0ms; duty cycle
≤
2%.
C
oss
eff. is a fixed capacitance that gives the
same charging time as C
oss
while V
DS
is rising
This value determined from sample failure population. 100%
tested to this value in production.
This is applied to D
2
Pak, when mounted on 1″ square PCB (FR-
4 or G-10 Material).
For recommended footprint and soldering
techniques refer to application note #AN-994.
R
θ
is measured at T
J
approximately 90°C
from 0 to 80% V
DSS
.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
11
Note: For
the most current drawings please refer to the IR website at:
