Infineon-Technologies-IRF5210LPBF

Part #Infineon-Technologies-IRF5210LPBF
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Infineon-Technologies-IRF5210LPBF
PD – 97049B  
IRF5210SPbF  
IRF5210LPbF  
HEXFET

®

Power MOSFET  
l
Advanced Process Technology  
l
Ultr
a
L
o
w
O
n-Resistance  
l
150°
C
O
peratin
g
T
emperature  
l
Fast Switching  
l
Repetitive Avalanche Allowed up to Tjmax  
l
Some Parameters are Different from  
IRF5210S/L  
D
V

DSS

= -100V  
R

DS(on)

= 60m
Ω  
G
I

D

= -38A  
S
l
P-Channel  
l
Lead-Free  
D
D
Description  
Features of this design
 
are a 150°C junction  
operating temperature, fast switching speed and  
improve
d
r
epetitiv
e
a
valanch
e
r
atin
g
.
T
hes
e
f
ea-  
tures combine to make this design an extremely  
efficient and reliable device for use in
 
a wide  
variety of other applications.  
S
S
D
D
G
G
D

2

Pak  
TO-262  
IRF5210LPbF  
IRF5210SPbF  
G
D
S
Gate  
Drain  
Source  
Absolute Maximum Ratings  
Parameter  
Max.  
-38  
Units  
A
I
I
I
@ T

C

= 25°C  
@ T

C

= 100°C  
Continuous Drain Current, V

GS

@ -10V  
Continuous Drain Current, VGS @ -10V  
Pulsed Drain Current  
D
D
-24  
-140  
3.1  
DM  
P
P
@T

A

= 25°C  
@T

C

= 25°C  
Maximum Power Dissipation  
W
D
D
Maximum Power Dissipation  
170  
Linear Derating Factor  
Gate-to-Source Voltage  
1.3  
± 20  
W/°C  
V
V
GS  
E

AS  

I

AR  

Single Pulse Avalanche Energy  
Avalanche Current  
120  
-23  
17  
mJ  
A
Repetitive Avalanche Energy  
E

AR  

mJ  
Peak Diode Recovery dv/dt  
Operating Junction and  
dv/dt  
T
J
-7.4  
V/ns  
°C  
-55 to
 
+ 150  
T
Storage Temperature Range  
STG  
Soldering Temperature, for 10 seconds  
300 (1.6mm from case )  
Thermal Resistance  
Parameter  
Typ.  
–––  
Max.  
0.75  
40  
Units  
°C/W  
R

θ
JC  

R

θ
JA  

Junction-to-Case  
–––  
Junction-to-Ambient (PCB Mount, steady state)  
1
08/04/09  

IRF5210S/LPbF  
Electrical Characteristics @ T

J

= 25°C (unless otherwise specified)  
Parameter  
Drain-to-Source Breakdown Voltage  
Min. Typ. Max.
 
Units  
-100 –––
 
–––  
Conditions  
V

GS

= 0V, I

D

= -250µA  
V

(BR)DSS  

∆Β
V

DSS

/
∆
T

J  

R

DS(on)  

V
Breakdown Voltage Temp. Coefficient
 
––– -0.11 ––– V/°C
 
Reference to 25°C, I

D

= -1mA  
Static Drain-to-Source On-Resistance  
Gate Threshold Voltage  
–––  
-2.0  
9.5  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
150  
22  
60  
-4.0  
–––  
-50  
V

GS

= 10V, I

D

= -38A  
V

DS

= V

GS

, I

D

= -250µA  

DS

= -50V, I

D

= -23A  
µA V

DS

= -100V, V

GS

= 0V  

DS

= -80V, V

GS

= 0V, T

J

= 125°C  
nA V

GS

= 20V  

GS

= -20V  
Ω
V
m
V

GS(th)  

gfs  
I

DSS  

Forward Transconductance  
S
V
Drain-to-Source Leakage Current  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
-250  
100  
-100  
230  
33  
V
I

GSS  

Gate-to-Source Forward Leakage  
Gate-to-Source Reverse Leakage  
Total Gate Charge  
V
Q

g  

Q

gs  

Q

gd  

t

d(on)  

t

r  

nC I

D

= -23A  
V

DS

= -80V  
Gate-to-Source Charge  
Gate-to-Drain (“Miller”) Charge  
Turn-On Delay Time  
81  
120  
–––  
–––  
–––  
–––  
–––  
V

GS

= -10V  

DD

= -50V  
14  
ns  
V
Rise Time  
63  
I

D

= -23A  
t

d(off)  

t

f  

Ω
Turn-Off Delay Time  
72  
R

G

= 2.4  
Fall Time  
55  
V

GS

= -10V  
L

D  

Internal Drain Inductance  
4.5  
nH Between
 
lead,  
6mm (0.25in.)  
from package  
L

S  

Internal Source Inductance  
–––  
7.5  
–––  
and center of die contact  
pF V

GS

= 0V  

DS

= -25V  
C

iss  

C

oss  

C

rss  

Input Capacitance  
––– 2780 –––  
Output Capacitance  
–––  
–––  
800  
430  
–––  
–––  
V
Reverse Transfer Capacitance  
ƒ = 1.0MHz, See Fig. 5  
Source-Drain Ratings and Characteristics  
Parameter  
Min. Typ. Max.
 
Units  
Conditions  
MOSFET symbol  
I

S  

Continuous Source Current  
–––  
–––  
-38  
(Body Diode)  
Pulsed Source Current  
A
V
showing the  
integral reverse  
I

SM  

–––  
–––  
-140  
(Body Diode)  
Diode Forward Voltage  
p-n junction diode.  
V

SD  

T =
 
25°C, I
 
= -23A, V
 
= 0V  
–––  
–––  
–––  
170  
-1.6  
260  
J
S
GS  
t

rr  

Q

rr  

T =
 
25°C, I
 
= -23A, V

DD

= -25V  
J F  
di/dt = -100A/µs  
Reverse Recovery Time  
Reverse Recovery Charge  
ns  
nC  
––– 1180
 
1770  
t

on  

Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)  
Forward Turn-On Time  
Notes:  
„
Pulse width
≤
300µs; duty cycle
≤
2%.  

Repetitive rating;
 
pulse width limited by  
max. junction temperature. ( See fig. 11)  
‚
Starting T

J

= 25°C, L = 0.46mH  
R

G

= 25
Ω
, I

AS

= -23A. (See Figure 12)  
ƒ
I

SD

≤
-23A, di/dt
≤
-650A/µs, V

DD

≤
V

(BR)DSS  

T

J

≤
150°C.  
ꢀ
When mounted on 1″ square PCB (FR-4or G-10  
Material). For
 
recommended footprint and soldering  
techniques refer to application note #AN-994.  
,
2

IRF5210S/LPbF  
1000  
100  
10  
1000  
100  
10  
VGS  
-15V  
-10V  
-8.0V  
-7.0V  
-6.0V  
-5.5V  
-5.0V  
VGS  
-15V  
-10V  
-8.0V  
-7.0V  
-6.0V  
-5.5V  
-5.0V  
-4.5V  
TOP  
TOP  
BOTTOM  
-4.5V  
BOTTOM  
-4.5V  
-4.5V  
1
1
60µs PULSE WIDTH  
Tj = 25°C  
60µs PULSE WIDTH  
Tj = 150°C  
≤
≤
0.1  
0.1  
0.1  
1
10  
100  
0.1  
1
10  
100  
-V ,
 
Drain-to-Source Voltage (V)  
DS  
-V ,
 
Drain-to-Source Voltage (V)  
DS  
Fig 1.
 
Typical Output Characteristics  
Fig 2.
 
Typical Output Characteristics  
1000  
100  
10  
2.0  
I
= -38A  
D
V
= -10V  
GS  
T
= 25°C  
T
J
1.5  
1.0  
0.5  
= 150°C  
J
1
V
= -50V  
DS  
≤
60µs PULSE WIDTH  
0.1  
2
4
6
8
10  
12  
14  
-60 -40 -20
 
0 20
 
40 60 80
 
100120140160180  
, Junction Temperature (°C)  
T
J
-V ,
 
Gate-to-Source Voltage (V)  
GS  
Fig 4.
 
Normalized On-Resistance  
Fig 3.
 
Typical Transfer Characteristics  
vs
.
T
emperature  
3

IRF5210S/LPbF  
100000  
12.0  
10.0  
8.0  
V
= 0V,  
= C  
f = 1 MHZ  
GS  
I =
 
-23A  
D
C
C
C
+ C
 
, C  
SHORTED  
ds  
iss  
gs  
gd  
V
V
V
= -80V  
= -50V  
= -20V  
= C  
DS  
DS  
DS  
rss  
oss  
gd  
= C
 
+ C  
ds  
gd  
10000  
1000  
100  
C
C
6.0  
iss  
oss  
4.0  
C
rss  
2.0  
0.0  
1
10  
-V ,
 
Drain-to-Source Voltage (V)  
100  
0
25  
Q
50  
75  
100  
125  
150  
, Total
 
Gate Charge (nC)  
DS  
G
Fig 5.
 
Typical Capacitance vs.  
Fig 6.
 
Typical Gate Charge vs.  
Drain-to-Sourc
e
V
oltage  
Gate-to-Sourc
e
V
oltage  
1000  
100  
10  
1000  
100  
10  
OPERATION IN THIS AREA  
LIMITED BY R  
(on)  
DS  
T
= 150°C  
J
T
= 25°C  
J
100µsec  
1
1msec  
Tc = 25°C  
Tj = 150°C  
Single Pulse  
10msec  
V
= 0V  
GS  
0.1  
1
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8  
1
10  
100  
1000  
-V ,
 
Source-to-Drain Voltage (V)  
SD  
-V ,
 
Drain-to-Source Voltage (V)  
DS  
Fig 7.
 
Typical Source-Drain Diode  
Fig 8.
 
Maximum Safe Operating Area  
Forward Voltage  
4

IRF5210S/LPbF  
R

D  

V

DS  

40  
35  
30  
25  
20  
15  
10  
5
V

GS  

D.U.T.  
R

G  

–
+
V

DD  

-10V  
Pulse Width
≤ 1
µs  
Duty Factor
≤ 0.1 %  
Fig 10a.
 
Switching Time Test Circuit  
t
t
r
t
t
f
d(on)  
d(off)  
V
GS  
10%  
0
25  
50  
T
75  
100  
125  
150  
, Case Temperature (°C)  
C
90%  
V
DS  
Fig 10b.
 
Switching Time Waveforms  
Fig 9.
 
Maximum Drain Current vs.  
Cas
e
T
emperature  
1
D = 0.50  
0.20  
0.10  
0.1  
0.01  
R

1  

R

1  

R

2  

R

2  

R

3  

R

3  

τι
(sec)  
Ri (°C/W)  
τ

J

τ

J  

τ
τ
0.05  

C

τ  
0.128309 0.000069  
0.377663 0.001772  
0.244513 0.010024  
τ

1

τ

1  

τ

2

τ

2  

3

τ

3  

0.02  
0.01  
Ci=
τ
i
/
Ri  
Ci=
τ
i
/
Ri  
SINGLE PULSE  
( THERMAL RESPONSE )  
Notes:  
1. Duty Factor D = t1/t2  
2. Peak Tj = P dm x Zthjc + Tc  
0.001  
1E-006  
1E-005  
0.0001  
0.001  
0.01  
0.1  
1
t
, Rectangular Pulse Duration (sec)  
1
Fig 11.
 
Maximum Effective Transient Thermal Impedance, Junction-to-Case  
5

IRF5210S/LPbF  
L
V
DS  
500  
450  
400  
350  
300  
250  
200  
150  
100  
50  
I
D.U.T  
AS  
R
D
G
V
DD  
A
TOP  
-8.7A  
-14A  
BOTTOM -23A  
I
DRIVER  
-20V  
0.01  
Ω
t
p
15V  
Fig 12a.
 
Unclamped Inductive Test Circuit  
I
AS  
0
25  
50  
75  
100  
125  
150  
Starting T
 
, Junction Temperature (°C)  
J
Fig 13.
 
Maximum Avalanche Energy  
vs
.
D
rai
n
C
urrent  
t
p
V
(BR)DSS  
Fig 12b.
 
Unclamped Inductive Waveforms  
Current Regulator  
Same Type as D.U.
T
.  
50K
Ω  
Q
G
.2
µ
F  
12V  
.3
µ
F  
-10V  
–
V
+
DS  
Q
Q
GD  
D.U.
T
.  
GS  
V
GS  
V
G
-3mA  
I
I
D
G
Charge  
Current Sampling Resistors  
Fig 14b.
 
Gate Charge Test Circuit  
Fig 14a.
 
Basic Gate Charge Waveform  
6

IRF5210S/LPbF  
Peak Diode Recovery dv/dt Test Circuit  
Circuit Layout Considerations  
•
Low Stray Inductance  
•
Ground Plane  
•
Low Leakage Inductance  
Current Transformer  
D.U.T
*  
+
ƒ
–
+
‚
„
–
+
–

+
–
R

G  

•
dv/dt controlled by R

G  

•
I

SD

controlled by Duty Factor “D”  
•
D.U.T. – Device Under Test  
V

DD  

V

GS  

*
Reverse Polarity of D.U.T for P-Channel  
Driver Gate Drive  
P
.
W.  
Period  
Period  
D =  
P.W.  
[
] ***  
=10V  
V
GS  
D.U.
T
. I
 
W
aveform  
SD  
Reverse  
Recovery  
Current  
Body Diode Forward  
Current  
di/dt  
D.U.
T
. V
 
W
aveform  
DS  
Diode Recovery  
dv/dt  
V
DD  
[
]
Re-Applied  
Voltage  
Body Diode  
Forward Drop  
Inductor Curent  
I
SD  
Ripple
≤
5%  
[
]
***
V

GS

= 5.0V for Logic Level and 3V Drive Devices  
Fi
g
1
5.
Fo
r
P
-Channe
l
H
EXFETS  
7

IRF5210S/LPbF  
D

2

Pak (TO-263AB) Package Outline  
Dimensions are shown in millimeters (inches)  
D

2

Pak (TO-263AB) Part Marking Information  
8

IRF5210S/LPbF  
TO-262 Package Outline  
Dimensions are shown in millimeters (inches)  
TO-262 Part Marking Information  
9

IRF5210S/LPbF  
D

2

Pak (TO-263AB)
T
a
pe & Reel Information  
Dimensions are shown in millimeters (inches)  
TRR  
1.60 (.063)  
1.50 (.059)  
1.60 (.063)  
1.50 (.059)  
4.10 (.161)  
3.90 (.153)  
0.368 (.0145)  
0.342 (.0135)  
FEED DIRECTION  
TRL  
11.60 (.457)  
11.40 (.449)  
1.85 (.073)  
1.65 (.065)  
24.30 (.957)  
23.90 (.941)  
15.42 (.609)  
15.22 (.601)  
1.75 (.069)  
1.25 (.049)  
10.90 (.429)  
10.70 (.421)  
4.72 (.136)  
4.52 (.178)  
16.10 (.634)  
15.90 (.626)  
FEED DIRECTION  
13.50 (.532)  
12.80 (.504)  
27.40 (1.079)  
23.90 (.941)  
4
330.00  
(14.173)  
MAX.  
60.00 (2.362)  
MIN.  
30.40 (1.197)  
MAX.  
NOTES :  
1. COMFORMS
 
TO EIA-418.  
2. CONTROLLING
 
DIMENSION: MILLIMETER.  
3. DIMENSION
 
MEASURED @ HUB.  
4. INCLUDES
 
FLANGE DISTORTION @ OUTER EDGE.  
26.40 (1.039)  
24.40 (.961)  
4
3
Data and specifications subject to change without notice.  
This product has been designed and qualified for the Industrial market.  
Qualification Standards can be found on IR’s Web site.  
IR WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105  
TAC Fax: (310) 252-7903  
10