Infineon-Technologies-IRF540ZLPBF
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PD – 95531A
IRF540ZPbF
IRF540ZSPbF
IRF540ZLPbF
Features
HEXFET
®
Power MOSFET
Advanced Process Technology
D
Ultra Low On-Resistance
175°C Operating Temperature
Fast Switching
V
DSS
= 100V
Repetitive Avalanche Allowed up to Tjmax
Lead-Free
R
DS(on)
= 26.5m
Ω
G
I
D
= 36A
Description
S
Thi
s
H
EXFET
®
Powe
r
M
OSFE
T
u
tilize
s
t
h
e
l
atest
processing techniques to achieve extremely low
on-resistanc
e
p
e
r
s
ilico
n
a
rea. Additiona
l
f
eatures
of this design
are a 175°C junction operating
temperature, fast switching speed and improved
repetitive avalanche rating.These features
combin
e
t
o
m
ak
e
t
hi
s
d
esig
n
a
n
e
xtremel
y
e
fficient
and reliable device for use in a wide variety of
applications.
D
2
Pak
IRF540ZSPbF IRF540ZLPbF
TO-262
TO-220AB
IRF540ZPbF
Absolute Maximum Ratings
Parameter
Max.
36
Units
A
(Silicon Limited)
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
I
I
I
@ T
= 25°C
C
D
D
@ T
= 100°C
C
25
140
92
DM
P
@T =
25°C
Power Dissipation
C
W
D
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
0.61
± 20
W/°C
V
V
GS
E
AS (Thermally limited)
83
120
mJ
Single Pulse Avalanche Energy Tested Value
Avalanche Current
E
AS
(Tested )
I
AR
See Fig.12a, 12b, 15, 16
A
Repetitive Avalanche Energy
E
AR
mJ
T
J
Operating Junction and
-55 to
+ 175
T
Storage Temperature Range
°C
STG
Soldering Temperature, for 10 seconds
Mounting Torque, 6-32 or M3 screw
300 (1.6mm from case )
10 lbf
in (1.1N m)
Thermal Resistance
Parameter
Typ.
–––
Max.
1.64
–––
62
Units
°C/W
R
θ
JC
CS
JA
JA
Junction-to-Case
R
θ
R
θ
R
θ
0.50
–––
Case-to-Sink, Flat Greased Surface
Junction-to-Ambient
–––
40
Junction-to-Ambient (PCB Mount)
1
07/23/10
IRF540Z/S/LPbF
Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage
Min. Typ. Max.
Units
100 ––– –––
Conditions
V
GS
= 0V, I
D
= 250µA
V
(BR)DSS
V
∆
V
∆
(BR)DSS
/ T
J
Breakdown Voltage Temp. Coefficient
––– 0.093 –––
V/°C Reference
to 25°C, I
D
= 1mA
Ω
m
R
DS(on)
V
GS(th)
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
–––
2.0
21
–––
–––
–––
–––
–––
–––
42
26.5
4.0
V
GS
= 10V, I
D
= 22A
V
V
DS
= V
GS
, I
D
= 250µA
V
DS
= 25V, I
D
= 22A
gfs
Forward Transconductance
36
–––
20
V
I
DSS
Drain-to-Source Leakage Current
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
µA V
DS
= 100V, V
GS
= 0V
V
DS
= 100V, V
GS
= 0V, T
J
= 125°C
nA V
GS
= 20V
V
GS
= -20V
250
200
-200
63
I
GSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Q
g
Q
gs
Q
gd
t
d(on)
t
r
I
D
= 22A
Gate-to-Source Charge
Gate-to-Drain (“Miller”) Charge
Turn-On Delay Time
9.7
15
–––
–––
–––
–––
–––
–––
–––
nC V
DS
= 80V
V
GS
= 10V
15
V
DD
= 50V
Rise Time
51
I
D
= 22A
t
d(off)
t
f
Ω
ns R
G
= 12
Turn-Off Delay Time
43
Fall Time
39
V
GS
= 10V
L
D
D
S
Internal Drain Inductance
4.5
Between lead,
nH 6mm
(0.25in.)
from package
G
L
S
Internal Source Inductance
–––
7.5
–––
and center of die contact
C
iss
Input Capacitance
––– 1770 –––
V
GS
= 0V
C
oss
C
rss
C
oss
C
oss
Output Capacitance
–––
–––
–––
–––
–––
180
100
730
110
170
–––
–––
–––
–––
–––
V
DS
= 25V
Reverse Transfer Capacitance
Output Capacitance
pF ƒ
= 1.0MHz
V
GS
= 0V,
V
DS
= 1.0V,
ƒ = 1.0MHz
V
GS
= 0V,
V
DS
= 80V,
ƒ = 1.0MHz
V
GS
= 0V, V
DS
= 0V to 80V
Output Capacitance
C
oss
eff.
Effective Output Capacitance
Source-Drain Ratings and Characteristics
Parameter
Min. Typ. Max.
Units
Conditions
I
Continuous Source Current
–––
–––
36
MOSFET symbol
S
(Body Diode)
A
showing the
I
Pulsed Source Current
–––
–––
140
integral reverse
SM
(Body Diode)
p-n junction diode.
V
t
Diode Forward Voltage
–––
–––
–––
–––
33
1.3
50
62
V
T =
25°C, I
= 22A, V
= 0V
SD
J
S
GS
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
ns T
= 25°C, I
= 22A, V
DD
= 50V
J F
rr
di/dt = 100A/µs
Q
t
41
nC
rr
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
on
2
IRF540Z/S/LPbF
1000
100
10
1000
100
10
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
TOP
TOP
BOTTOM
BOTTOM
4.5V
4.5V
60µs PULSE WIDTH
Tj = 175°C
60µs PULSE WIDTH
Tj = 25°C
1
1
0.1
1
10
100
0.1
1
1
10
1
100
1
0
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
80
1000
100
T
= 175°C
J
60
40
20
0
T
= 175°C
J
T =
25°C
J
10
1
T
= 25°C
J
V
= 25V
DS
V
= 10V
DS
380µs PULSE WIDTH
60µs PULSE WIDTH
4.0
5.0
6.0 7.0
0
10
20
30
40
50
V
, Gate-to-Source Voltage (V)
GS
I
Drain-to-Source Current (A)
D,
Fig 3.
Typical Transfer Characteristics
Fig 4.
Typical Forward Transconductance
Vs. Drain Current
3
IRF540Z/S/LPbF
3000
20
16
12
8
V
= 0V,
= C
f = 1 MHZ
GS
I =
22A
D
C
C
C
+ C
, C
SHORTED
ds
iss
gs
gd
V
= 80V
= C
DS
2500
2000
1500
1000
500
rss
oss
gd
= C
+ C
VDS= 50V
VDS= 20V
ds
gd
Ciss
4
Coss
Crss
FOR TEST CIRCUIT
SEE FIGURE 13
0
0
0
10
20
30
40
50
60
1
10
, Drain-to-Source Voltage (V)
100
Q
Total Gate Charge (nC)
G
V
DS
Fig 6.
Typical Gate Charge Vs.
Fig 5.
Typical Capacitance Vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
1000.0
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
100.0
10.0
1.0
T
= 175°C
J
100µsec
1
T
= 25°C
J
1msec
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
10msec
GS
0.1
0.1
0.2
0.4
V
0.6
0.8
1.0
1.2
1.4
1
10
100
1000
, Source-toDrain Voltage (V)
V
, Drain-toSource Voltage (V)
SD
DS
Fig 8.
Maximum Safe Operating Area
Fig 7.
Typical Source-Drain Diode
Forward Voltage
4
IRF540Z/S/LPbF
3.0
2.5
2.0
1.5
1.0
0.5
40
30
20
10
0
I
= 22A
= 10V
D
V
GS
-60 -40 -20
T
0
20 40 60 80
100 120 140 160 180
25
50
75
100
125
150
175
, Junction Temperature (°C)
T
, Junction Temperature (°C)
J
J
Fig 10.
Normalized On-Resistance
Fig 9.
Maximum Drain Current Vs.
Vs. Temperature
Case Temperature
10
1
D = 0.50
0.20
0.10
0.1
0.05
0.02
0.01
0.01
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 11.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
5
IRF540Z/S/LPbF
180
160
140
120
100
80
15V
I
D
TOP
8.3A
14A
BOTTOM 20A
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
–
I
A
2
V
0
G
V
S
Ω
0.01
t
p
60
Fig 12a.
Unclamped Inductive Test Circuit
40
V
(BR)DSS
t
p
20
0
25
50
75
100
125
150
175
Starting T
, Junction Temperature (°C)
J
I
AS
Fig 12c.
Maximum Avalanche Energy
Fig 12b.
Unclamped Inductive Waveforms
Vs. Drain Current
Q
G
10 V
Q
Q
4.0
3.5
3.0
2.5
2.0
1.5
GS
GD
V
G
I
= 250µA
D
Charge
Fig 13a.
Basic Gate Charge Waveform
L
VCC
DUT
0
1K
-75 -50 -25
0
25 50 75
100 125 150 175
T ,
Temperature ( °C )
J
Fig 14.
Threshold Voltage Vs. Temperature
Fig 13b.
Gate Charge Test Circuit
6
IRF540Z/S/LPbF
1000
100
10
Duty Cycle = Single Pulse
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming
∆
Tj = 25°C due to
avalanche losses
0.01
0.05
0.10
1
0.1
1.0E-08
1.0E-07
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15.
Typical Avalanche Current Vs.Pulsewidth
100
90
80
70
60
50
40
30
20
10
0
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T
jmax
. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
TOP
BOTTOM 10%
Duty Cycle
= 20A
Single Pulse
I
D
4. P
D (ave)
= Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. I
av
= Allowable avalanche current.
7.
∆
T
=
Allowable rise in junction temperature, not to exceed
T
jmax
(assumed as 25°C in Figure 15, 16).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche =
t
av
·f
25
50
75
100
125
150
175
Z
thJC
(D, t
av
) = Transient thermal resistance, see figure 11)
Starting T
, Junction Temperature (°C)
J
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
D
T/ Z
thJC
Fig 16.
Maximum Avalanche Energy
I
av
= 2
D
T/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
Vs. Temperature
7
IRF540Z/S/LPbF
Driver Gate Drive
P.W.
P
.
W.
Period
Period
D =
D.U.T
+
*
=10V
V
GS
Circuit Layout Considerations
•
Low Stray Inductance
•
Ground Plane
•
Low Leakage Inductance
Current Transformer
–
D.U.
T
. I
W
aveform
SD
+
–
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
–
+
D.U.
T
. V
W
aveform
DS
Diode Recovery
dv/dt
V
DD
V
DD
Re-Applied
Voltage
•
dv/dt controlled by R
G
R
G
+
–
Body Diode
Forward Drop
•
Driver same type as D.U.T.
•
I
SD
controlled by Duty Factor “D”
•
D.U.T. – Device Under Test
Inductor Curent
I
SD
Ripple
≤
5%
*
V
GS
= 5V for Logic Level Devices
Fig 17.
Peak Diode Recovery dv/dt Test Circuit
for N-Channel
HEXFET
®
Power MOSFETs
R
D
V
DS
V
GS
D.U.T.
R
G
+
V
DD
–
10V
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
Fig 18a.
Switching Time Test Circuit
V
DS
90%
10%
V
GS
t
t
r
t
t
f
d(on)
d(off)
Fig 18b.
Switching Time Waveforms
8
IRF540Z/S/LPbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220A
B
P
ar
t
M
arkin
g
I
nformation
EX
A
M
P
LE: THIS
IS
A
N
I
RF1010
P
A
R
T NU
M
B
ER
L
O
T CO
D
E 1789
IN
T
ER
N
A
T
I
O
NAL
RE
C
T
IFIER
L
O
GO
A
S
SE
M
B
LED
O
N WW 19, 2000
IN THE
A
S
SE
M
B
LY LI
N
E “C”
DAT E
CODE
Y
E
A
R 0 =
2
000
W
E
EK
1
9
Note: “P” in
a
s
s
e
mbly l
i
n
e
p
o
s
i
t
ion
indic
a
tes “L
ead – F
r
e
e”
A
S
SE
M
B
LY
L
O
T CO
D
E
LINE C
TO-220AB package is not recommended for Surface Mount Application
Notes:
9
IRF540Z/S/LPbF
D
2
Pak (TO-263AB) Package Outline
Dimensions are shown in millimeters (inches)
D
2
Pak (TO-263AB) Part Marking Information
T
H
IS IS
A
N IR
F
5
30S WI
T
H
P
A
R
T NUMBER
LOT
C
ODE 8024
IN
T
ER
N
A
T
I
ON
A
L
RE
C
T
I
F
I
E
R
L
O
GO
AS S E MB L
E
D
O
N WW 02, 2000
IN
T
HE
A
S
SE
M
B
LY LI
N
E “
L
”
F530S
D
A
T
E
C
ODE
Y
E
A
R 0 =
2000
W
E
EK 02
AS S E MB L Y
L
O
T CODE
LINE L
OR
P
A
R
T
N
U
M
B
ER
IN
T
ER
N
A
T
I
O
N
A
L
RE
C
T
I
F
I
E
R
L
O
GO
F530S
DA
T
E
C
ODE
P = DESI
G
NA
T
ES LE
A
D
–
F
REE
PR
O
D
U
C
T (OP
T
I
ON
A
L
)
AS S E MB L Y
LOT
C
ODE
YE
A
R 0 =
2000
W
E
EK 02
A =
A
S S E M
B
L Y S IT E
C
ODE
Notes:
10
IRF540Z/S/LPbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
EX
A
M
P
LE: THIS
IS
A
N
I
RL3103L
L
O
T CODE 1789
P
A
R
T NU
M
B
E
R
IN
T
ER
N
A
T
I
O
NAL
RE
C
T
I
F
I
ER
L
O
GO
AS S
E
M
B L
E
D
O
N WW 19, 1997
IN
T
H
E
A
S
SE
M
B
LY LI
N
E “
C
”
DA
T
E
C
O
D
E
YE
A
R 7 =
1
9
97
W
E
E K 19
Note: “P” in
a
s
s
e
mbly l
i
ne
pos
i
tion in
d
i
c
ates “
L
e
ad
–
Fr
e
e”
A
S
SE
M
B
LY
L
O
T CODE
LINE C
OR
P
A
R
T NU
M
B
ER
IN
T
ER
N
A
T
I
O
NAL
RE
C
T
I
F
I
ER
L
O
GO
DA
T
E
C
O
D
E
P =
D
E
SI
G
NA
T
ES LE
A
D
-FREE
PR
O
D
U
C
T (O
P
TI
O
N
AL)
YE
A
R 7 =
1
9
97
A
S
SE
M
B
LY
L
O
T CODE
W
E
E K 19
A =
AS S
E
M
BL Y S ITE
C
ODE
Notes:
11
IRF540Z/S/LPbF
D
2
Pak Tape & Reel Infomation
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
0.368 (.0145)
0.342 (.0135)
FEED DIRECTION
TRL
11.60 (.457)
11.40 (.449)
1.85 (.073)
1.65 (.065)
24.30 (.957)
23.90 (.941)
15.42 (.609)
15.22 (.601)
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
NOTES :
1. COMFORMS
TO EIA-418.
2. CONTROLLING
DIMENSION: MILLIMETER.
3. DIMENSION
MEASURED @ HUB.
4. INCLUDES
FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
4
3
Notes:
ꢀ
Limited by T
Jmax
, see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
Repetitive rating;
pulse width limited by
max. junction temperature. (See fig. 11).
Limited by T
Jmax
, starting T
= 25°C, L = 0.46mH
This value determined from sample failure population. 100%
tested to this value in production.
J
R
G
= 25
Ω
, I
AS
= 20A, V
GS
=10V. Part not
recommended for use above this value.
Pulse width
≤
1.0ms; duty cycle
≤
2%.
C
oss
eff. is a fixed capacitance that gives the
same charging time as C
oss
while V
DS
is rising
This is only applied to TO-220AB pakcage.
This is applied to D
2
Pak, when mounted on 1″ square PCB (FR-
4 or G-10 Material).
For recommended footprint and soldering
techniques refer to application note #AN-994.
from 0 to 80% V
DSS
.
TO-220AB package is not recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
12
