Infineon-Technologies-IRF6717MTRPBF
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PD – 97345C
IRF6717MPbF
IRF6717MTRPbF
DirectFET
Power MOSFET
Typical values (unless otherwise specified)
l
RoHs Compliant and Halgen Free
l
Low Profile (<0.7 mm)
V
DSS
V
GS
R
DS(on)
R
DS(on)
25V max
±20V max
0.95m
@ 10V
1.6m
@ 4.5V
l
Dual Sided Cooling Compatible
l
Ultra Low Package Inductance
Q
g tot
Q
gd
Q
gs2
Q
rr
Q
oss
V
gs(th)
l
Optimized for High Frequency Switching
l
Ideal for CPU Core DC-DC Converters
l
Optimized for Sync. FET socket of Sync. Buck Converter
l
Low Conduction and Switching Losses
46nC
14nC
6.6nC
31nC
35nC
1.8V
l
Compatible with existing Surface Mount
T
e
chniques
l
100% Rg tested
DirectFET
ISOMETRIC
MX
Applicable DirectFET Outline and
Substrate Outline (see p.7,8 for details)
SQ
SX
ST
MQ
MT
MP
MX
Description
The IRF6717MPbF combines the latest HEXFET® Power MOSFET Silicon technology with the advanced DirectFET
TM
packaging to achieve
the lowest on-state resistance in a package that has the footprint of a SO-8 and only 0.7 mm profile.
The DirectFET package is compatible
with existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infra-red or convection soldering
techniques, when application note AN-1035 is followed regarding the manufacturing methods and processes. The DirectFET package allows
dual sided cooling to maximize thermal transfer in power systems, improving previous best thermal resistance by 80%.
The IRF6717MPbF balances both low resistance and low charge along with ultra low package inductance to reduce both conduction and
switching losses. The reduced total losses make this product ideal for high efficiency DC-DC converters that power the latest generation of
processors operating at higher frequencies.
The IRF6717MPbF has been optimized for parameters that are critical in synchronous buck
including Rds(on), gate charge and Cdv/dt-induced turn on immunity. The IRF6717MPbF offers particularly low Rds(on) and high Cdv/dt
immunity for synchronous FET applications
.
Absolute Maximum Ratings
Max.
25
Parameter
Units
V
V
DS
Drain-to-Source Voltage
±20
38
V
Gate-to-Source Voltage
GS
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
I
I
I
I
@ T
A
= 25°C
D
D
D
30
A
@ T
A
= 70°C
@ T
C
= 25°C
220
300
290
30
DM
E
AS
I
AR
Single Pulse Avalanche Energy
Avalanche Current
mJ
A
6
5
4
3
2
1
0
14.0
12.0
10.0
8.0
I
= 30A
I =
30A
D
D
V
= 20V
= 13V
DS
V
DS
6.0
T
= 125°C
J
4.0
2.0
T =
25°C
J
0.0
2
4
6
8
10 12 14 16 18 20
0
20
40
60
80
100
120
Q
Total Gate Charge (nC)
G
V
Gate -to -Source Voltage
(V)
GS,
Fig 1.
Typical On-Resistance vs. Gate Voltage
Fig 2.
Typical Total
Gate Charge vs Gate-to-Source Voltage
Notes:
T
C
measured with thermocouple mounted to top (Drain) of part.
ꢀ
Repetitive rating;
pulse width limited by max. junction temperature.
Starting T
J
= 25°C, L = 0.64mH, R
G
= 25
, I
AS
= 30A.
Click on this section to link to the appropriate technical paper.
Click on this section to link to the DirectFET Website.
Surface mounted on 1 in. square Cu board, steady state.
1
06/01/12
IRF6717MPbF
Static @ T
J
= 25°C (unless otherwise specified)
Conditions
V
GS
= 0V, I
D
= 250
μ
A
Reference to 25°C, I
= 1mA
Parameter
Min. Typ. Max.
Units
BV
DSS
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
25
–––
–––
–––
1.35
–––
–––
–––
–––
–––
140
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
V
V
/ T
J
DSS
18
––– mV/°C
D
V
GS
= 10V, I
D
= 38A
R
DS(on)
0.95 1.25
m
V
GS
= 4.5V, I
D
= 30A
1.6
1.8
-6.7
–––
–––
–––
–––
–––
46
2.1
V
DS
= V
GS
, I
D
= 150
μ
A
V
GS(th)
Gate Threshold Voltage
2.35
V
V
/ T
GS(th)
Gate Threshold Voltage Coefficient
Drain-to-Source Leakage Current
––– mV/°C
J
V
DS
= 20V, V
GS
= 0V
I
DSS
1.0
150
100
-100
–––
69
μ
A
nA
S
V
DS
= 20V, V
GS
= 0V, T
J
= 125°C
V
GS
= 20V
I
GSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Forward Transconductance
Total Gate Charge
V
GS
= -20V
V
DS
= 13V, I
D
=30A
gfs
Q
g
V
DS
= 13V
Q
gs1
Pre-Vth Gate-to-Source Charge
Post-Vth Gate-to-Source Charge
Gate-to-Drain Charge
Gate Charge Overdrive
Switch Charge (Q
gs2
+ Q
gd
)
Output Charge
14
–––
–––
–––
–––
–––
–––
2.2
V
GS
= 4.5V
I
D
= 30A
Q
gs2
Q
gd
6.6
14
nC
Q
godr
11
See Fig. 15
Q
sw
20.6
35
V
DS
= 16V, V
GS
= 0V
Q
oss
R
G
nC
Gate Resistance
1.3
25
V
DD
= 13V, V
GS
= 4.5V
I
D
= 30A
t
d(on)
t
r
t
d(off)
t
f
Turn-On Delay Time
–––
–––
–––
–––
Rise Time
37
R =
1.8
Turn-Off Delay Time
19
ns
G
Fall Time
15
V
GS
= 0V
DS
= 13V
C
iss
C
oss
C
rss
Input Capacitance
––– 6750 –––
––– 1700 –––
V
Output Capacitance
pF
ƒ = 1.0MHz
Reverse Transfer Capacitance
–––
730
–––
Diode Characteristics
Conditions
Parameter
Min. Typ. Max.
Units
I
S
MOSFET symbol
Continuous Source Current
–––
–––
–––
–––
120
300
showing the
(Body Diode)
A
I
SM
integral reverse
Pulsed Source Current
(Body Diode)
p-n junction diode.
T
J
= 25°C, I
S
= 30A, V
GS
= 0V
T
J
= 25°C, I
F
=30A
di/dt = 175A/
μ
s
V
SD
t
rr
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
–––
–––
–––
–––
27
1.0
41
47
V
ns
nC
Q
rr
31
Notes:
ꢀ
Repetitive rating;
pulse width limited by max. junction temperature.
Pulse width
400
μ
s; duty cycle
2%.
2
IRF6717MPbF
Absolute Maximum Ratings
Max.
Parameter
Units
2.8
Power Dissipation
Power Dissipation
Power Dissipation
W
P
P
P
@T
A
= 25°C
@T
A
= 70°C
@T
C
= 25°C
D
D
D
P
J
1.8
96
270
T
T
T
Peak Soldering Temperature
Operating Junction and
°C
-40 to
+ 150
Storage Temperature Range
STG
Thermal Resistance
Parameter
Typ.
–––
12.5
20
Max.
45
Units
°C/W
W/°C
R
JA
Junction-to-Ambient
R
JA
Junction-to-Ambient
Junction-to-Ambient
Junction-to-Case
–––
–––
1.3
R
JA
R
JC
–––
1.0
R
J-PCB
Junction-to-PCB Mounted
Linear Derating Factor
–––
0.022
100
10
D = 0.50
0.20
0.10
0.05
Ri (°C/W)
i (sec)
0.0116
0.0289
0.2249
0.3032
0.7515
2.7510
17.682
23.053
0.000007
3.55E-06
0.000076
0.006892
0.001645
0.009995
38.19138
1.05185
1
0.02
0.01
R
1
R
1
R
2
R
2
R
3
R
3
R
4
R
4
R
5
R
5
R
6
R
6
R
7
R
7
R
8
R
8
J
A
J
1
A
2
3
4
5
6
7
0.1
1
2
3
4
5
6
7
Ci=
i
Ri
Ci=
i
Ri
0.01
0.001
Notes:
SINGLE PULSE
( THERMAL RESPONSE )
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthja + Tc
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
10
100
1000
t
, Rectangular Pulse Duration (sec)
1
Fig 3.
Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
Notes:
R
is measured at
T
J
of approximately 90°C.
Used double sided cooling, mounting pad with large heatsink.
Mounted on minimum footprint full size board with metalized
back and with small clip heatsink.
Mounted on minimum
footprint full size board with
metalized back and with small
clip heatsink (still air)
Mounted to a PCB
with
small clip heatsink (still air)
Surface mounted on 1 in. square Cu
(still air).
3
IRF6717MPbF
1000
1000
100
10
VGS
10V
VGS
10V
60
μ
s PULSE WIDTH
Tj = 25°C
60
μ
s PULSE WIDTH
Tj = 150°C
TOP
TOP
5.0V
4.5V
3.5V
3.3V
3.0V
2.8V
2.5V
5.0V
4.5V
3.5V
3.3V
3.0V
2.8V
2.5V
100
10
1
BOTTOM
BOTTOM
2.5V
2.5V
1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 4.
Typical Output Characteristics
Fig 5.
Typical Output Characteristics
1000
100
10
2.0
1.5
1.0
0.5
V
= 15V
I
= 38A
DS
D
60
μ
s PULSE WIDTH
V
V
= 10V
GS
GS
= 4.5V
T =
150°C
J
T =
25°C
J
T =
-40°C
J
1
0.1
1
2
3
4
5
-60 -40 -20
0
20 40 60 80
100 12
0
1
40 160
T
J
, Junction Temperature (°C)
V
, Gate-to-Source Voltage (V)
GS
Fig 7.
Normalized On-Resistance vs. Temperature
Fig 6.
Typical Transfer Characteristics
6
100000
10000
1000
V
= 0V,
= C
f = 1 MHZ
GS
T
= 25°C
J
C
C
C
+ C
, C
SHORTED
ds
iss
gs
gd
Vgs = 3.5V
Vgs = 4.0V
Vgs = 4.5V
Vgs = 5.0V
Vgs = 10V
= C
5
4
3
2
1
0
rss
oss
gd
= C
+ C
ds
gd
C
iss
C
oss
C
rss
100
0
50
100
150
200
1
10
, Drain-to-Source Voltage (V)
100
V
DS
I ,
Drain Current (A)
D
Fig 9.
Typical On-Resistance vs.
Drain Current and Gate Voltage
Fig 8.
Typical Capacitance vs.Drain-to-Source Voltage
4
IRF6717MPbF
1000
100
10
1000
100
10
OPERATION IN THIS AREA LIMITED
BY R
(on)
DS
100
μ
sec
1msec
200
μ
sec
DC
10msec
T
T
T
= 150°C
= 25°C
= -40°C
J
J
J
1
1
Ta = 25°C
Tj = 150°C
Single Pulse
V
= 0V
GS
0.1
0
0.01
0.1
1
10
100
0.0
0.5
SD
1.0
1.5
2.0
2.5
V
, Drain-toSource Voltage (V)
V
, Source-to-Drain Voltage (V)
DS
Fig 10.
Typical Source-Drain Diode Forward Voltage
Fig11.
Maximum Safe Operating
Area
2.5
240
200
160
120
80
2.0
I
= 150
μ
A
D
1.5
1.0
0.5
40
0
-75 -50 -25
0
25 50 75
100 125 150
25
50
T
75
100
125
150
T
, Temperature ( °C )
, Case Temperature (°C)
J
C
Fig 13.
Typical Threshold Voltage vs. Junction
Fig 12.
Maximum Drain Current vs. Case Temperature
Temperature
1200
I
D
TOP
19A
24A
1000
800
600
400
200
0
BOTTOM 30A
25
50
75
100
125
150
Starting T
, Junction Temperature (°C)
J
Fig 14.
Maximum Avalanche Energy vs. Drain Current
5
IRF6717MPbF
Id
Vds
Vgs
L
VCC
DUT
0
1K
Vgs(th)
Qgs1
Qgs2
Qgd
Qgodr
Fig 15a.
Gate Charge Test Circuit
Fig 15b.
Gate Charge Waveform
V
(BR)DSS
15V
t
p
DRIVER
L
V
DS
V
GS
D.U.T
AS
R
G
+
–
V
DD
I
A
20V
t
0.01
p
I
AS
Fig 16b.
Unclamped Inductive Waveforms
Fig 16a.
Unclamped Inductive Test Circuit
R
D
V
DS
V
DS
90%
V
GS
D.U.T.
R
G
+
V
DD
–
10%
V
GS
V
GS
Pulse Width
µs
Duty Factor
t
d(on)
t
d(off)
t
r
t
f
Fig 17a.
Switching Time Test Circuit
Fig 17b.
Switching Time Waveforms
6
IRF6717MPbF
Driver Gate Drive
P.W.
P
.
W.
D =
D.U.T
Period
Period
+
–
*
=10V
V
GS
Circuit Layout Considerations
Low Stray Inductance
Ground Plane
Low Leakage Inductance
Current Transformer
D.U.
T
. I
W
aveform
SD
+
–
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
–
+
D.U.
T
. V
W
aveform
DS
Diode Recovery
dv/dt
V
DD
V
DD
di/dt controlled by R
G
Re-Applied
Voltage
R
G
+
–
Driver same type as D.U.T.
Body Diode
Inductor Current
Forward Drop
I
SD
controlled by Duty Factor “D”
D.U.T. – Device Under Test
I
SD
Ripple
5%
*
V
GS
= 5V for Logic Level Devices
Fig 18.
Diode Reverse Recovery Test Circuit
for N-Channel
HEXFET
®
Power MOSFETs
DirectFET
Board Footprint, MX Outline
(Medium Size Can, X-Designation).
Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET.
This includes all recommendations for stencil and
substrate designs.
G = GATE
D = DRAIN
S = SOURCE
D
D
D
D
S
S
G
7
IRF6717MPbF
DirectFET
Outline Dimension, MX Outline
(Medium Size Can, X-Designation).
Please see AN-1035 for DirectFET assembly details and stencil and substrate design recommendations
DIMENSIONS
METRIC
IMPERIAL
CODE MIN
MAX
MIN
MAX
0.250
0.201
0.156
0.018
0.028
0.028
0.056
0.033
0.017
0.040
0.095
0.028
0.003
0.007
A
B
C
D
E
F
6.25 6.35
4.80 5.05
3.85 3.95
0.35 0.45
0.68 0.72
0.68 0.72
0.246
0.189
0.152
0.014
0.027
0.027
0.054
0.031
0.015
0.035
0.090
0.023
0.001
0.003
G
H
J
1.38
1.42
0.80 0.84
0.38 0.42
0.88 1.02
2.28 2.42
0.59 0.70
0.03 0.08
0.08 0.17
K
L
M
N
P
DirectFET
Part Marking
GATE MARKING
LOGO
PART NUMBER
BATCH NUMBER
DATE CODE
Line above the last character of
the date code indicates “Lead-Free”
8
IRF6717MPbF
DirectFET
T
a
pe & Reel Dimension (Showing component orientation).
NOTE: Controlling dimensions in mm
Std reel quantity is 4800 parts. (ordered as IRF6717MTRPBF). For 1000 parts on 7″
reel, order
IRF6717MTR1PBF
REEL DIMENSIONS
STANDARD OPTION
(QTY 4800)
METRIC IMPERIAL
TR1 OPTION
(QTY 1000)
METRIC IMPERIAL
CODE
MIN
12.992
0.795
0.504
0.059
3.937
N.C
MIN
6.9
MAX
N.C
N.C
0.50
N.C
N.C
0.53
N.C
N.C
MIN
MAX
N.C
N.C
13.2
N.C
N.C
18.4
14.4
15.4
MAX
N.C
MIN
MAX
N.C
A
B
C
D
E
F
330.0
20.2
12.8
1.5
177.77
19.06
13.5
1.5
0.75
0.53
0.059
2.31
N.C
N.C
N.C
0.520
N.C
12.8
N.C
100.0
N.C
58.72
N.C
N.C
N.C
0.724
0.567
0.606
13.50
12.01
12.01
G
H
0.488
0.469
0.47
0.47
12.4
11.9
11.9
11.9
LOADED TAPE FEED DIRECTION
DIMENSIONS
METRIC
IMPERIAL
NOTE: CONTROLLING
DIMENSIONS IN MM
MIN
CODE
MAX
0.319
0.161
0.484
0.219
0.209
0.264
N.C
MIN
7.90
3.90
11.90
5.45
5.10
6.50
1.50
1.50
MAX
8.10
4.10
12.30
5.55
5.30
6.70
N.C
0.311
0.154
0.469
0.215
0.201
0.256
0.059
0.059
A
B
C
D
E
F
G
H
1.60
0.063
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
9
