Infineon-Technologies-IRF7779L2TRPBF
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IRF7779L2PbF
Typical values (unless otherwise specified)
l
Lead-Free (Qualified up to 260°C Reflow)
l
Ideal for High Performance Isolated Converter
Primary Switch Socket
l
Optimized for Synchronous Rectification
V
DSS
V
GS
R
DS(on)
9.0m
Ω
@ 10V
V
gs(th)
150V min
±20V max
Q
g tot
Q
gd
l
Low Conduction Losses
97nC
33nC
4.0V
l
High Cdv/dt Immunity
l
Low Profile (<0.7mm)
l
Industrial Qualified
S
S
S
S
S
S
S
S
G
D
D
DirectFET
ISOMETRIC
L8
SB
SC
M2
M4
L4
L6
L8
Description
The IRF7779L2TR/TR1PbF combines the latest HEXFET® Power MOSFET Silicon technology with the advanced DirectFET
TM
packaging to
achieve the lowest on-state resistance in a package that has a footprint smaller than a D
2
PAK and only 0.7 mm profile.
The DirectFET package is
compatible with existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infra-red or convection soldering
techniques, when application note AN-1035 is followed regarding the manufacturing methods and processes. The DirectFET package allows dual
sided cooling to maximize thermal transfer in power systems.
The IRF7779L2TR/TR1PbF is optimized for high frequency switching and synchronous rectification applications. The reduced total losses in
the device coupled with the high level of thermal performance enables high efficiency and low temperatures, which are key for system reliability
improvements, and makes this device ideal for high performance power converters.
Standard Pack
Form
Tape and Reel
Tape and Reel
Orderable part number
Package Type
Note
Quantity
4000
1000
IRF7779L2TRPbF
I
R
F7779L2TR1PbF
DirectFET2 Large Can
DirectFET2 Large Can
“TR” suffix
“
T
R1″ suffix EOL notice # 264
Absolute Maximum Ratings
Max.
150
±20
67
47
11
375
270
270
40
Parameter
Units
V
Drain-to-Source Voltage
Gate-to-Source Voltage
V
DS
V
GS
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
D
@ T
A
= 25°C
I
D
@ T
C
= 25°C
I
DM
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
Continuous Drain Current, V
GS
@ 10V (Package Limited)
Pulsed Drain Current
A
Single Pulse Avalanche Energy
mJ
A
E
AS
Avalanche Current
I
AR
20.00
16.00
12.00
8.00
50.00
40.00
30.00
20.00
10.00
0.00
T =
25°C
C
I
= 40A
D
V
V
V
V
= 7.0V
GS
GS
GS
GS
= 8.0V
= 10V
= 15V
T
= 125°C
= 25°C
J
T
J
4.0
6.0
V
8.0
10.0 12.0 14.0 16.0
50
70
90
110
, Gate-to-Source Voltage (V)
GS
I ,
Drain Current (A)
D
Fig 1.
Typical On-Resistance vs. Gate Voltage
Fig 2.
Typical On-Resistance vs. Drain Current
Notes:
T
C
measured with thermocouple mounted to top (Drain) of part.
ꢀ
Repetitive rating;
pulse width limited by max. junction temperature.
Starting T
J
= 25°C, L = 0.33mH, R
G
= 25
Ω
, I
AS
= 40A.
Surface mounted on 1 in. square Cu board, steady state.
1
May 6, 2014
IRF7779L2PbF
Static @ T
J
= 25°C (unless otherwise specified)
Conditions
Parameter
Min. Typ. Max.
Units
V
GS
= 0V, I
D
= 250
μ
A
BV
DSS
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
150
–––
–––
3.0
–––
0.13
9.0
4.0
-15
–––
–––
–––
–––
–––
97
–––
–––
11
V
Reference to 25°C, I
D
= 2mA
V
GS
= 10V, I
D
= 40A
ΔΒ
V
DSS
/
Δ
T
J
R
DS(on)
V/°C
m
Ω
V
DS
= V
GS
, I
D
= 250
μ
A
V
GS(th)
5.0
V
V
/ T
Δ
GS(th)
Δ
Gate Threshold Voltage Coefficient
Drain-to-Source Leakage Current
–––
–––
–––
–––
–––
83
––– mV/°C
J
V
DS
= 150V, V
GS
= 0V
I
DSS
20
250
100
-100
–––
150
–––
–––
50
μ
A
nA
S
V
DS
= 120V, V
GS
= 0V, T
J
= 125°C
V
GS
= 20V
I
GSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Forward Transconductance
Total Gate Charge
V
GS
= -20V
V
DS
= 50V, I
D
= 40A
gfs
Q
g
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
V
DS
= 75V
Q
gs1
Pre-Vth Gate-to-Source Charge
Post-Vth Gate-to-Source Charge
Gate-to-Drain Charge
Gate Charge Overdrive
Switch Charge (Q
gs2
+ Q
gd
)
Output Charge
27
V
GS
= 10V
Q
gs2
Q
gd
6.9
33
nC
I
D
= 40A
Q
godr
30
–––
–––
–––
–––
–––
–––
–––
–––
See Fig. 9
Q
sw
40
V
DS
= 16V, V
GS
= 0V
Q
oss
R
G
39
nC
Gate Resistance
1.5
16
Ω
V
DD
= 75V, V
GS
= 10V
I
D
= 40A
t
d(on)
t
r
t
d(off)
t
f
Turn-On Delay Time
Rise Time
19
R
G
=1.8
Ω
Turn-Off Delay Time
36
ns
Fall Time
12
V
GS
= 0V
C
iss
C
oss
C
rss
C
oss
C
oss
Input Capacitance
––– 6660 –––
V
DS
= 25V
ƒ = 1.0MHz
Output Capacitance
–––
–––
840
180
–––
–––
pF
Reverse Transfer Capacitance
Output Capacitance
V
GS
= 0V, V
DS
= 1.0V, f=1.0MHz
––– 5620 –––
––– 400 –––
V
GS
= 0V, V
DS
= 120V, f=1.0MHz
Output Capacitance
Diode Characteristics
Conditions
MOSFET symbol
Parameter
Continuous Source Current
Min. Typ. Max.
Units
I
S
–––
–––
67
showing the
(Body Diode)
A
I
SM
integral reverse
Pulsed Source Current
(Body Diode)
–––
–––
270
p-n junction diode.
T
J
= 25°C, I
S
= 40A, V
GS
= 0V
T
J
= 25°C, I
F
= 40A, V
DD
= 75V
di/dt = 100A/
μ
s
V
SD
t
rr
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
–––
–––
–––
–––
110
510
1.3
170
770
V
ns
nC
Q
rr
Notes:
ꢀ
Repetitive rating;
pulse width limited by max. junction temperature.
Pulse width
≤
400
μ
s; duty cycle
≤
2%.
2
May 6, 2014
IRF7779L2PbF
Absolute Maximum Ratings
Max.
Parameter
Units
125
Power Dissipation
Power Dissipation
Power Dissipation
W
P
P
P
@T
C
= 25°C
@T
C
= 100°C
@T
A
= 25°C
D
D
D
P
J
63
3.3
270
Peak Soldering Temperature
Operating Junction and
°C
T
T
T
-55 to
+ 175
Storage Temperature Range
STG
Thermal Resistance
Parameter
Typ.
–––
12.5
20
Max.
45
Units
R
θ
JA
Junction-to-Ambient
R
θ
JA
Junction-to-Ambient
Junction-to-Ambient
Junction-to-Can
–––
–––
1.2
R
θ
JA
°C/W
R
θ
J-Can
R
θ
J-PCB
–––
–––
Junction-to-PCB Mounted
0.5
10
1
D = 0.50
0.20
0.10
0.05
0.1
R
1
R
1
R
2
R
2
R
3
R
3
R
4
Ri (°C/W)
τ
i (sec)
R
4
0.02
0.01
0.1080
0.6140
0.4520
1.47e-05
0.000171
0.053914
0.006099
0.036168
τ
τ
J
τ
J
τ
C
τ
0.01
0.001
0.0001
1
τ
1
Ci=
τ
i
/
Ri
τ
τ
τ
2
τ
2
3
τ
3
4
τ
4
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
t
, Rectangular Pulse Duration (sec)
1
Fig 3.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
Notes:
Mounted on minimum footprint full size board with metalized
back and with small clip heatsink.
Surface mounted on 1 in. square Cu board, steady state.
T
C
measured with thermocouple incontact with top (Drain) of part.
Used double sided cooling, mounting pad with large heatsink.
R
is measured at
T
J
of approximately 90°C.
θ
Surface mounted on 1 in. square Cu
board (still
air).
Mounted on minimum footprint full size board with metalized
back and with small clip heatsink. (still air)
3
May 6, 2014
IRF7779L2PbF
1000
100
10
1000
100
10
VGS
15V
10V
8.0V
7.5V
7.0V
6.5V
6.0V
5.5V
VGS
15V
10V
8.0V
7.5V
7.0V
6.5V
6.0V
5.5V
TOP
TOP
BOTTOM
BOTTOM
≤
60
μ
s PULSE WIDTH
5.5V
Tj = 25°C
5.5V
1
≤
60
μ
s PULSE WIDTH
Tj = 175°C
1
0.1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 4.
Typical Output Characteristics
Fig 5.
Typical Output Characteristics
1000
3.0
2.5
2.0
1.5
1.0
0.5
V
= 50V
I
= 40A
DS
60
μ
s PULSE WIDTH
D
≤
V
= 10V
GS
100
10
1
T
T
T
= 175°C
J
J
J
= 25°C
= -40°C
0.1
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
-60 -40 -20
0
20 40 60 80
100 120 140 160 180
V
, Gate-to-Source Voltage (V)
GS
T
, Junction Temperature (°C)
J
Fig 6.
Typical Transfer Characteristics
Fig 7.
Normalized On-Resistance vs. Temperature
100000
14
V
C
= 0V,
f = 1 MHZ
GS
I
= 40A
D
= C
+ C
, C
SHORTED
iss
gs
gd ds
V
V
V
= 120V
= 75V
= 30V
12
10
8
DS
DS
DS
C
= C
rss
gd
C
= C
+ C
ds
oss
gd
10000
1000
100
Ciss
6
Coss
4
2
Crss
10
0
0
20
40
60
80
100 120 140
1
100
1000
Q
Total Gate Charge (nC)
G
V
, Drain-to-Source Voltage (V)
DS
Fig 9.
Typical Total
Gate Charge vs
Fig 8.
Typical Capacitance vs.Drain-to-Source Voltage
Gate-to-Source Voltage
4
May 6, 2014
IRF7779L2PbF
1000
100
10
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
T
T
T
= 175°C
= 25°C
= -40°C
J
J
J
100
μ
sec
1msec
10msec
DC
1
1
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
GS
0.1
0.1
0
1
10
100
1000
0.2
0.4
0.6
0.8
1.0
V
, Drain-toSource Voltage (V)
V
, Source-to-Drain Voltage (V)
DS
SD
Fig 10.
Typical Source-Drain Diode Forward Voltage
Fig11.
Maximum Safe Operating Area
70
60
50
40
30
20
10
0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
I
I
I
= 1.0A
D
D
D
= 1.0mA
= 250
μ
A
25
50
75
100
125
150
175
-75 -50 -25
0
J
25 50 75
100 125 150 175
, Temperature ( °C )
T
, CaseTemperature (°C)
T
C
Fig 13.
Typical Threshold Voltage vs.
Fig 12.
Maximum Drain Current vs. Case Temperature
Junction Temperature
1200
I
D
TOP
7.8A
12A
40A
1000
800
600
400
200
0
BOTTOM
25
50
75
100
125
150
175
Starting T
, Junction Temperature (°C)
J
Fig 14.
Maximum Avalanche Energy Vs. Drain Current
5
May 6, 2014
IRF7779L2PbF
1000
100
10
Allowed avalanche Current vs avalanche
Duty Cycle = Single Pulse
pulsewidth, tav, assuming
Tj = 150°C and
Δ
Tstart =25°C (Single Pulse)
0.01
0.05
0.10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
ΔΤ
j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15.
Typical Avalanche Current Vs.Pulsewidth
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T
jmax
. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 19a, 19b.
280
240
200
160
120
80
TOP
BOTTOM 1%
Duty Cycle
= 40A
Single Pulse
I
D
4. P
D (ave)
= Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. I
av
= Allowable avalanche current.
7.
Δ
T
=
Allowable rise in junction temperature, not to exceed
T
jmax
(assumed as 25°C in Figure 15, 16).
t
av =
Average time in avalanche.
40
0
D = Duty cycle in avalanche =
t
av
·f
25
50
75
100
125
150
175
Z
thJC
(D, t
av
) = Transient thermal resistance, see figure 11)
Starting T
, Junction Temperature (°C)
J
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
D
T/ Z
thJC
Fig 16.
Maximum Avalanche Energy Vs. Temperature
I
av
= 2
D
T/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
a
Driver Gate Drive
P
.
W.
D.U.T
Period
D =
Period
P.W.
+
*
=10V
V
GS
Circuit Layout Considerations
•
Low Stray Inductance
•
Ground Plane
•
Low Leakage Inductance
Current Transformer
–
D.U.
T
. I
W
aveform
SD
+
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
–
+
–
D.U.
T
. V
W
aveform
DS
Diode Recovery
dv/dt
V
DD
V
DD
•
di/dt controlled by R
G
Re-Applied
Voltage
R
G
+
–
•
Driver same type as D.U.T.
Body Diode
Inductor Current
Forward Drop
•
I
SD
controlled by Duty Factor “D”
•
D.U.T. – Device Under Test
I
SD
Ripple
≤
5%
*
V
GS
= 5V for Logic Level Devices
Fig 17.
Diode Reverse Recovery Test Circuit
for N-Channel HEXFET
®
Power MOSFETs
6
IRF7779L2PbF
Id
Vds
Vgs
L
VCC
DUT
0
Vgs(th)
20K
Qgs1
Qgs2
Qgodr
Qgd
Fig 18a.
Gate Charge Test Circuit
Fig 18b.
Gate Charge Waveform
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
V
R
D.U.T
AS
GS
G
V
DD
–
I
A
20V
t
0.01
Ω
p
I
AS
Fig 19b.
Unclamped Inductive Waveforms
Fig 19a.
Unclamped Inductive Test Circuit
R
D
V
DS
V
DS
90%
V
GS
D.U.T.
R
G
+
V
DD
–
V
GS
10%
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
V
GS
t
t
r
t
t
f
d(on)
d(off)
Fig 20a.
Switching Time Test Circuit
Fig 20b.
Switching Time Waveforms
7
May 6, 2014
IRF7779L2PbF
DirectFET
Board Footprint, L8 (Large Size Can).
Please see AN-1035 for DirectFET assembly details and stencil and substrate design recommendations
G = GATE
D = DRAIN
S = SOURCE
D
D
D
D
D
D
S
S
S
S
S
S
S
S
G
8
May 6, 2014
IRF7779L2PbF
DirectFET
Outline Dimension, L8 Outline (LargeSize Can).
Please see AN-1035 for DirectFET assembly details and stencil and substrate design recommendations
DIMENSIONS
IMPERIAL
MIN
0.356
7.10 0.270
METRIC
MAX
9.15
CODE
MIN
9.05
6.85
5.90
0.55
0.58
1.18
0.98
0.73
0.38
1.34
2.52
0.59
0.03
0.09
MAX
0.360
0.280
0.236
0.026
0.024
0.048
0.017
0.030
0.017
0.058
0.106
0.028
0.003
0.007
A
B
C
D
E
F
6.00
0.65
0.62
0.232
0.022
0.023
1.22 0.046
1.02
0.77
0.42
1.47
2.69
0.70
0.08
0.18
0.015
0.029
0.015
0.053
0.099
0.023
0.001
0.003
G
H
J
K
L
M
N
P
DirectFET
Part Marking
GATE MARKING
LOGO
PART NUMBER
BATCH NUMBER
DATE CODE
Line above the last character of
the date code indicates “Lead-Free”
9
May 6, 2014
IRF7779L2PbF
DirectFET
T
a
pe & Reel Dimension (Showing component orientation).
NOTE: Controlling dimensions in mm Std reel
quantity is 4000 parts. (ordered as IRF7779L2PBF).
REEL DIMENSIONS
STANDARD OPTION
(QTY 4000)
METRIC
MAX
IMPERIAL
MIN
CODE
MAX
N.C
MIN
12.992
0.795
0.504
0.059
3.937
N.C
A
B
C
D
E
F
330.0
20.2
12.8
1.5
N.C
N.C
13.2
N.C
N.C
22.4
18.4
18.4
N.C
0.520
N.C
100.0
N.C
N.C
0.889
0.724
0.724
G
H
0.646
0.626
16.4
15.9
LOADED TAPE FEED DIRECTION
NOTE: CONTROLLING
DIMENSIONS IN MM
DIMENSIONS
METRIC
IMPERIAL
CODE
MIN
MIN
MAX
0.476
0.161
0.642
0.299
0.291
0.398
NC
MAX
12.10
4.10
16.30
7.60
7.40
10.10
NC
0.469
0.154
0.626
0.291
0.284
0.390
0.059
0.059
A
B
C
D
E
F
11.90
3.90
15.90
7.40
7.20
9.90
1.50
1.50
G
H
0.063
1.60
May 6, 2014
IRF7779L2PbF
Qualification Information
†
Industrial
††
Qualification level
(per JEDEC JESD47F
†††
guidelines)
Comments: This family of products has passed JEDEC’s Industrial
qualification. IR’s Consumer qualification level is granted by extension of the
higher Industrial level.
MSL1
Moisture Sensitivity Level
RoHS Compliant
DFET2
(per JEDEC J-STD-020D
†††
)
Yes
Qualification standards can be found at International Rectifier’s web site
Higher qualification ratings may be available should the user have such requirements.
Please contact your International Rectifier sales representative for further information:
Applicable version of JEDEC standard at the time of product release.
Revision History
Date
Comments
•
•
Updated ordering information to reflect the End-Of-life (EOL) of the mini-reel option
(EOL notice #264).
Updated data sheet based on corporate template.
5/6/2014
IR WORLD HEADQUARTERS:
101 N. Sepulveda Blvd., El Segundo, California 90245, USA
11
May 6, 2014
