Infineon-Technologies-IRF8010PBF
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PD – 95505
IRF8010PbF
SMPS MOSFET
l
High frequency DC-DC converters
l
UPS and Motor Control
l
Lead-Free
Applications
HEXFET
®
Power MOSFET
V
DSS
R
DS(on)
max
I
D
100V
15m
Ω
80A
Benefits
l
Low Gate-to-Drain Charge to Reduce
Switching Losses
l
Fully Characterized Capacitance Including
Effective C
OSS
to Simplify Design, (See
App. Note AN1001)
l
Fully Characterized Avalanche Voltage
and Current
l
Typical R
DS(on)
= 12m
Ω
TO-220AB
Absolute Maximum Ratings
Parameter
Max.
80
Units
A
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
I
I
I
@ T
= 25°C
C
D
D
@ T
= 100°C
C
57
320
260
DM
P
@T =
25°C
C
Power Dissipation
W
D
Linear Derating Factor
Gate-to-Source Voltage
1.8
W/°C
V
V
± 20
GS
dv/dt
T
J
Peak Diode Recovery dv/dt
Operating Junction and
16
V/ns
-55 to
+ 175
T
Storage Temperature Range
°C
STG
Soldering Temperature, for 10 seconds
Mounting torque, 6-32 or
M3 screw
300 (1.6mm from case )
1.1(10)
N•m (lbf•in)
Thermal Resistance
Parameter
Typ.
–––
Max.
0.57
–––
62
Units
R
θ
JC
R
θ
CS
R
θ
JA
Junction-to-Case
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient
0.50
–––
°C/W
Notes
through
are on
page 8
1
07/06/04
IRF8010PbF
Static @ T
J
= 25°C (unless otherwise specified)
Parameter
Min. Typ. Max.
Units
Conditions
V
(BR)DSS
Drain-to-Source Breakdown Voltage
100
–––
0.11
12
–––
V
V
GS
= 0V, I
D
= 250µA
∆
∆
V
(BR)DSS
/ T
J
Breakdown Voltage Temp. Coefficient
–––
––– V/°C
Reference to 25°C, I
D
= 1mA
m
Ω
R
DS(on)
V
GS(th)
I
DSS
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
–––
2.0
15
4.0
V
GS
= 10V, I
D
= 45A
V
DS
= V
GS
, I
D
= 250µA
µA V
DS
= 100V, V
GS
= 0V
–––
–––
–––
–––
–––
V
Drain-to-Source Leakage Current
–––
–––
–––
–––
20
250
200
-200
V
DS
= 100V, V
GS
= 0V, T
J
= 125°C
I
GSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
nA V
GS
= 20V
V
GS
= -20V
Dynamic @ T
J
= 25°C (unless otherwise specified)
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max.
Units
Conditions
gfs
82
–––
81
–––
120
–––
–––
–––
–––
–––
–––
V
V
DS
= 25V, I
D
= 45A
I
D
= 80A
Q
g
–––
–––
–––
–––
–––
–––
–––
Q
gs
Q
gd
t
d(on)
t
r
Gate-to-Source Charge
Gate-to-Drain (“Miller”) Charge
Turn-On Delay Time
Rise Time
22
nC
V
DS
= 80V
26
V
GS
= 10V
V
DD
= 50V
I
D
= 80A
15
130
61
t
d(off)
t
f
Ω
R
G
= 39
Turn-Off Delay Time
Fall Time
ns
120
V
GS
= 10V
V
GS
= 0V
V
DS
= 25V
C
iss
C
oss
C
rss
C
oss
C
oss
C
oss
eff.
Input Capacitance
––– 3830 –––
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
–––
–––
480
59
–––
–––
pF ƒ
= 1.0MHz
––– 3830 –––
V
GS
= 0V,
V
DS
= 1.0V,
ƒ = 1.0MHz
–––
–––
280
530
–––
–––
V
GS
= 0V,
V
DS
= 80V,
ƒ = 1.0MHz
V
GS
= 0V, V
DS
= 0V to 80V
Avalanche Characteristics
Parameter
Single Pulse Avalanche Energy
Typ.
–––
–––
–––
Max.
310
45
Units
mJ
A
E
AS
I
AR
Avalanche Current
Repetitive Avalanche Energy
E
AR
26
mJ
Diode Characteristics
Parameter
Min. Typ. Max.
Units
Conditions
D
I
I
Continuous Source Current
–––
–––
80
MOSFET symbol
S
(Body Diode)
Pulsed Source Current
A
showing the
integral reverse
G
–––
–––
320
SM
S
(Body Diode)
p-n junction diode.
V
t
Diode Forward Voltage
–––
–––
–––
–––
99
1.3
150
700
V
T =
25°C, I
= 80A, V
= 0V
J S GS
SD
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
ns T
= 150°C, I
= 80A, V
DD
= 50V
J F
rr
di/dt = 100A/µs
Q
t
460
nC
rr
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
on
2
IRF8010PbF
10000
1000
100
10
1000
100
10
VGS
15V
12V
VGS
15V
12V
TOP
TOP
10V
10V
6.0V
5.5V
5.0V
4.5V
4.0V
6.0V
5.5V
5.0V
4.5V
BOTTOM
BOTTOM 4.0V
4.0V
4.0V
1
20µs PULSE WIDTH
Tj = 175°C
20µs PULSE WIDTH
Tj = 25°C
1
0.1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
DS
V
, Drain-to-Source Voltage (V)
DS
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
3.5
1000
80A
=
I
D
T
= 175°C
3.0
2.5
2.0
1.5
1.0
0.5
0.0
J
100
10
1
T
= 25°C
J
V
= 50V
DS
20µs PULSE WIDTH
V
= 10V
GS
2.0
4.0
V
6.0
8.0
10.0
12.0
14.0
16.0
-60 -40 -20
0
20 40 60 80
100 120 140 160 180
°
T ,
Junction Temperature
( C)
, Gate-to-Source Voltage (V)
J
GS
Fig 3.
Typical Transfer Characteristics
Fig 4.
Normalized On-Resistance
Vs. Temperature
3
IRF8010PbF
100000
12
10
8
V
= 0V,
f = 1 MHZ
I =
80A
GS
D
C
= C
+ C
, C
SHORTED
iss
gs gd
ds
V
V
V
= 80V
= 50V
= 20V
DS
DS
DS
C
= C
gd
rss
C
= C
+ C
oss
ds gd
10000
1000
100
C
iss
6
C
oss
4
2
C
rss
0
10
0
20
40
60
80
100
1
10
100
Q
Total Gate Charge (nC)
G
V
, Drain-to-Source Voltage (V)
DS
Fig 6.
Typical Gate Charge Vs.
Fig 5.
Typical Capacitance Vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
1000
100
10
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
°
T =
175
J
C
100µsec
1msec
°
T =
25
J
C
1
1
Tc = 25°C
10msec
Tj = 175°C
Single Pulse
V
= 0 V
GS
0.1
0.1
0.0
0.5
1.0
1.5
2.0
1
10
100
1000
V
,Source-to-Drain Voltage (V)
SD
V
, Drain-to-Source Voltage (V)
DS
Fig 8.
Maximum Safe Operating Area
Fig 7.
Typical Source-Drain Diode
Forward Voltage
4
IRF8010PbF
R
D
80
60
40
20
0
V
DS
LIMITED BY PACKAGE
V
GS
10V
D.U.T.
R
G
+
V
DD
–
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
Fig 10a.
Switching Time Test Circuit
V
DS
90%
25
50
75
100
125
150
175
°
, Case Temperature
( C)
T
C
10%
V
GS
t
t
r
t
t
f
Fig 9.
Maximum Drain Current Vs.
d(on)
d(off)
Case Temperature
Fig 10b.
Switching Time Waveforms
10
1
D = 0.50
0.20
P
DM
0.1
t
1
0.10
0.05
t
2
SINGLE PULSE
0.02
Notes:
(THERMAL RESPONSE)
0.01
1. Duty factor D =
t
/ t
1
2
2. Peak T
= P
x
Z
+ T
J
DM
thJC
C
0.01
0.00001
0.0001
0.001
0.01
0.1
1
t ,
Rectangular Pulse Duration (sec)
1
Fig 11.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
5
IRF8010PbF
600
500
400
300
200
100
0
15V
I
D
TOP
18A
32A
45A
DRIVER
+
L
BOTTOM
V
DS
D.U.T
AS
R
G
V
DD
–
I
A
20V
0.01
Ω
t
p
Fig 12a.
Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
25
50
75
100
125
°
( C)
150
175
Starting Tj, Junction Temperature
Fig 12c.
Maximum Avalanche Energy
Vs. Drain Current
I
AS
Fig 12b.
Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.
T
.
Q
G
50K
Ω
.2
µ
F
12V
10 V
.3
µ
F
Q
Q
GD
GS
+
V
DS
D.U.
T
.
–
V
GS
V
G
3mA
I
I
D
G
Charge
Current Sampling Resistors
Fig 13a.
Basic Gate Charge Waveform
Fig 13b.
Gate Charge Test Circuit
6
IRF8010PbF
Peak Diode Recovery dv/dt Test Circuit
+
Circuit Layout Considerations
•
Low Stray Inductance
•
Ground Plane
•
Low Leakage Inductance
Current Transformer
D.U.T
–
+
–
–
+
R
G
•
dv/dt controlled by R
G
+
–
•
Driver same type as D.U.T.
•
I
SD
controlled by Duty Factor “D”
•
D.U.T. – Device Under Test
V
DD
Driver Gate Drive
P.W.
P
.
W.
Period
Period
D =
V
=10V
*
GS
D.U.
T
. I
W
aveform
SD
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.
T
. V
W
aveform
DS
Diode Recovery
dv/dt
V
DD
Re-Applied
Voltage
Body Diode
Forward Drop
Inductor Curent
I
SD
Ripple
≤
5%
*
V
GS
= 5V for Logic Level Devices
Fig 14.
For N-Channel HEXFET
®
Power MOSFETs
7
IRF8010PbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
10.54 (.415)
3.78 (.149)
– B –
10.29 (.405)
2.87 (.113)
2.62 (.103)
4.69 (.185)
4.20 (.165)
3.54 (.139)
1.32 (.052)
1.22 (.048)
– A –
6.47 (.255)
6.10 (.240)
4
15.
2
4 (.600)
14.
8
4 (.584)
LEAD ASSIGNMENTS
1.15 (.045)
MIN
HEXFET
IGBTs, CoPACK
1
2
3
1- GATE
1- GATE
2- DRAIN
2- COLLECTOR
3- EMITTER
4- COLLECTOR
3- SOURCE
4- DRAIN
14.09 (.555)
13.47 (.530)
4.06 (.160)
3.55 (.140)
0.93 (.037)
0.69 (.027)
0.55 (.022)
0.46 (.018)
3X
3X
1.40 (.055)
3X
1.15 (.045)
0.36 (.014)
M
B A M
2.92 (.115)
2.64 (.104)
2.54 (.100)
2X
NOTES:
1
2
D
I
MENS
I
O
NING & TOLERANCING PER ANSI Y14.5M, 1982.
CONTROLLING DIMENSION : INCH
3
4
OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.
HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
TO-220AB Part Marking Information
E
X
AM
P
L
E
: THIS
IS AN IRF
1
010
L
O
T CODE 1789
P
A
RT NUMBER
A
S
SEMBLED ON
W
W
1
9, 1997
IN T
H
E
A
S
SE
M
BLY
LINE “
C
”
I
N
TERNATIONAL
RECT
I
F
I
ER
L
O
GO
Note:
“P” in assembly line
position indicates “Lead-Free”
DAT E
C
ODE
Y
E
A
R 7 =
1
997
WEE K 19
A
S
SE
M
BLY
L
O
T CODE
LINE C
Notes:
Repetitive rating;
pulse width limited by
max. junction temperature.
Starting T
J
= 25°C, L = 0.31mH, R
G
= 25
Ω
,
I
AS
= 45A.
Pulse width
≤
300µs; duty cycle
≤
2%.
ꢀ
C
oss
eff. is a fixed capacitance that gives the same charging time
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 75A.
I
SD
≤
45A, di/dt
≤
110A/µs, V
DD
≤
V
(BR)DSS
,
T
J
≤
175°C.
TO-220 package is not recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
8
Note: For
the most current drawings please refer to the IR website at:
