Infineon-Technologies-IRF8327STRPBF
| Part # | Infineon-Technologies-IRF8327STRPBF |
| Download | Infineon-Technologies-IRF8327STRPBF |
IRF8327SPbF
l
Low Profile (<0.7 mm)
Typical values (unless otherwise specified)
V
DSS
V
GS
R
DS(on)
R
DS(on)
l
Ultra Low Package Inductance
30V max
±20V max
5.1m
Ω
@ 10V
8.5m
Ω
@ 4.5V
l
Ideal for CPU Core DC-DC Converters
l
Low Conduction and Switching Losses
Q
g tot
Q
gd
Q
gs2
Q
rr
Q
oss
V
gs(th)
9.2nC 3.0nC 1.2nC
19nC
7.9nC
1.9V
DirectFET
®
ISOMETRIC
SQ
SX
ST
MQ
MX
MT
MP
SQ
Description
The IRF8327SPbF combines the latest HEXFET
®
Power MOSFET Silicon technology with the advanced DirectFET
®
packaging to achieve the
lowest on-state resistance in a package that has the footprint of a MICRO-8 and only 0.7 mm profile.
The DirectFET
®
package is compatible
with existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infra-red or convection soldering
techniques, when application note AN-1035 is followed regarding the manufacturing methods and processes. The DirectFET
®
package allows
dual sided cooling to maximize thermal transfer in power systems, improving previous best thermal resistance by 80%.
The IRF8327SPbF balances both low resistance and low charge along with ultra low package inductance to reduce both conduction and
switching losses. The reduced total losses make this product ideal for high efficiency DC-DC converters that power the latest generation of
processors operating at higher frequencies.
The IRF8327SPbF has been optimized for parameters that are critical in synchronous buck
operating from 12 volt bus converters including Rds(on) and gate charge
to minimize losses
.
Standard Pack
Form
Tape and Reel
Tape and Reel
Orderable part number
Package Type
Note
Quantity
4800
1000
IRF8327STRPbF
IRF8327STR1PbF
DirectFET SQ
DirectFET SQ
“TR” suffix
“
T
R1″ suffix EOL notice # 264
Absolute Maximum Ratings
Max.
Parameter
Units
Drain-to-Source Voltage
Gate-to-Source Voltage
30
±20
14
11
60
110
62
11
V
V
DS
V
GS
I
D
@ T
A
= 25°C
I
D
@ T
A
= 70°C
I
D
@ T
C
= 25°C
I
DM
E
AS
I
AR
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
Single Pulse Avalanche Energy
Avalanche Current
A
mJ
A
25
20
15
10
5
14.0
I =
11A
I
= 14A
D
D
12.0
10.0
8.0
V
V
V
= 24V
= 15V
= 6.0V
DS
DS
DS
6.0
T
= 125°C
J
4.0
2.0
T
= 25°C
5
J
0
0.0
0
10
15
20
0
5
10
15
20
25
Q
Total Gate Charge (nC)
G
V
Gate -to -Source Voltage
(V)
GS,
Fig 1.
Typical On-Resistance vs. Gate Voltage
Notes:
Fig 2.
Typical Total
Gate Charge vs. Gate-to-Source Voltage
T
C
measured with thermocouple mounted to top (Drain) of part.
ꢀ
Repetitive rating;
pulse width limited by max. junction temperature.
Starting T
J
= 25°C, L = 1.1mH, R
G
= 25
Ω
, I
AS
= 11A.
Surface mounted on 1 in. square Cu board, steady state.
1
May 6, 2014
IRF8327SPbF
Static @ T
J
= 25°C (unless otherwise specified)
Conditions
Parameter
Min. Typ. Max.
Units
V
GS
= 0V, I
D
= 250
μ
A
BV
DSS
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
30
–––
–––
V
Reference to 25°C, I
= 1mA
ΔΒ
V
DSS
/
Δ
T
J
R
DS(on)
–––
–––
–––
1.4
22
––– mV/°C
D
V
GS
= 10V, I
D
= 14A
5.1
8.5
1.9
-6.3
–––
–––
–––
–––
–––
9.2
2.7
1.2
3.0
2.3
4.2
7.9
2.1
7.8
8.9
9.3
5.3
7.3
10.9
2.4
m
Ω
V
GS
= 4.5V, I
D
= 11A
V
DS
= V
GS
, I
D
= 25
μ
A
V
GS(th)
Gate Threshold Voltage
V
Δ
V
GS(th)
/
Δ
T
J
I
DSS
Gate Threshold Voltage Coefficient
Drain-to-Source Leakage Current
–––
–––
–––
–––
–––
25
––– mV/°C
V
DS
= 24V, V
GS
= 0V
V
DS
= 24V, V
GS
= 0V, T
J
= 125°C
V
GS
= 20V
1.0
150
100
-100
–––
14
μ
A
nA
S
I
GSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Forward Transconductance
Total Gate Charge
V
GS
= -20V
V
DS
= 15V, I
D
= 11A
gfs
Q
g
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
V
DS
= 15V
Q
gs1
Q
gs2
Q
gd
Q
godr
Q
sw
Q
oss
R
G
Pre-Vth Gate-to-Source Charge
Post-Vth Gate-to-Source Charge
Gate-to-Drain Charge
Gate Charge Overdrive
Switch Charge (Q
gs2
+ Q
gd
)
Output Charge
–––
–––
–––
–––
–––
–––
3.7
V
GS
= 4.5V
I
D
= 11A
nC
See Fig. 15
V
DS
= 16V, V
GS
= 0V
nC
Gate Resistance
Ω
V
DD
= 15V, V
GS
= 4.5V
I
D
= 11A
t
d(on)
t
r
t
d(off)
t
f
Turn-On Delay Time
–––
–––
–––
–––
Rise Time
ns
R =
1.8
Ω
Turn-Off Delay Time
G
See Fig. 17
V
GS
= 0V
Fall Time
C
iss
C
oss
C
rss
Input Capacitance
––– 1430 –––
V
DS
= 15V
Output Capacitance
–––
–––
370
140
–––
–––
pF
ƒ = 1.0MHz
Reverse Transfer Capacitance
Diode Characteristics
Conditions
Parameter
Min. Typ. Max.
Units
I
S
MOSFET symbol
Continuous Source Current
–––
–––
52
showing the
(Body Diode)
A
I
SM
integral reverse
Pulsed Source Current
(Body Diode)
–––
–––
110
p-n junction diode.
T
J
= 25°C, I
S
= 11A, V
GS
= 0V
T
J
= 25°C, I
F
= 11A
di/dt = 230A/
μ
s
V
SD
t
rr
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
–––
–––
–––
0.80
17
1.0
26
29
V
ns
nC
Q
rr
19
Notes:
Pulse width
≤
400
μ
s; duty cycle
≤
2%.
2
May 6, 2014
IRF8327SPbF
Absolute Maximum Ratings
Max.
Parameter
Units
2.2
Power Dissipation
Power Dissipation
Power Dissipation
W
P
P
P
@T
A
= 25°C
@T
A
= 70°C
@T
C
= 25°C
D
D
D
P
J
1.4
42
270
T
T
T
Peak Soldering Temperature
Operating Junction and
°C
-40 to
+ 150
Storage Temperature Range
STG
Thermal Resistance
Parameter
Typ.
–––
12.5
20
Max.
58
Units
°C/W
W/°C
R
θ
JA
Junction-to-Ambient
Junction-to-Ambient
Junction-to-Ambient
Junction-to-Case
R
θ
JA
–––
–––
3.0
R
θ
JA
R
θ
JC
–––
1.0
R
θ
J-PCB
Junction-to-PCB Mounted
Linear Derating Factor
–––
0.017
100
10
D = 0.50
0.20
0.10
0.05
0.02
0.01
1
R
1
R
1
R
2
R
2
R
3
R
3
Ri (°C/W)
τ
i (sec)
5.276 0.00315
τ
τ
J
τ
J
τ
A
τ
A
τ
1
τ
1
τ
0.1
2
τ
2
3
τ
3
30.637 0.75858
22.090 36.9
Ci=
τ
i
/
Ri
Ci=
τ
i
/
Ri
0.01
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthja + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
10
100
1000
t
, Rectangular Pulse Duration (sec)
1
Fig 3.
Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
Notes:
R
is measured at
T
J
of approximately 90°C.
Used double sided cooling , mounting pad with large heatsink.
Mounted on minimum footprint full size board with metalized
back and with small clip heatsink.
θ
Mounted on minimum
footprint full size board with
metalized back and with small
clip heatsink (still air)
Mounted to a PCB
with
small clip heatsink (still air)
Surface mounted on 1 in. square Cu
(still air).
3
May 6, 2014
IRF8327SPbF
1000
100
10
1000
100
10
VGS
10V
VGS
10V
TOP
TOP
5.0V
4.5V
4.0V
3.5V
3.0V
2.8V
2.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.8V
2.5V
BOTTOM
BOTTOM
1
2.5V
1
0.1
0.01
2.5V
60
μ
s PULSE WIDTH
Tj = 150°C
≤
60
μ
s PULSE WIDTH
Tj = 25°C
≤
0.1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
DS
V
, Drain-to-Source Voltage (V)
Fig 4.
Ty
D
p
S
ical Output Characteristics
Fig 5.
Typical Output Characteristics
1000
100
10
2.0
1.5
1.0
0.5
V
= 15V
I
= 14A
DS
D
≤
60
μ
s PULSE WIDTH
V
V
= 10V
GS
GS
= 4.5V
T =
150°C
J
T =
25°C
J
T =
-40°C
J
1
0.1
1.5
2.0
2.5
3.0
3.5
4.0
4.5
-60 -40 -20
0
20 40 60 80
100 12
0
1
40 160
T
J
, Junction Temperature (°C)
V
, Gate-to-Source Voltage (V)
GS
Fig 7.
Normalized On-Resistance vs. Temperature
Fig 6.
Typical Transfer Characteristics
10000
1000
100
40
V
= 0V,
= C
f = 1 MHZ
GS
T
= 25°C
J
C
C
C
+ C
, C
SHORTED
ds
iss
gs
gd
35
30
25
20
15
10
5
= C
rss
oss
gd
= C
+ C
Vgs = 3.5V
Vgs = 4.0V
Vgs = 4.5V
Vgs = 5.0V
Vgs = 8.0V
Vgs = 10V
ds
gd
C
iss
C
oss
C
rss
0
1
10
100
0
20
40
60
80
100
120
V
, Drain-to-Source Voltage (V)
DS
I
, Drain Current (A)
D
Fig 9.
Typical On-Resistance vs.
Drain Current and Gate Voltage
Fig 8.
Typical Capacitance vs.Drain-to-Source Voltage
4
May 6, 2014
IRF8327SPbF
1000
100
10
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
T
T
T
= 150°C
= 25°C
= -40°C
100
μ
sec
J
J
J
1msec
10msec
1
DC
1
T
= 25°C
0.1
0.01
A
T =
150°C
J
V
= 0V
Single Pulse
GS
0
0.01 0.10
1.00
10.00
100.00
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
, Source-to-Drain Voltage (V)
V
, Drain-to-Source Voltage (V)
V
DS
SD
Fig 10.
Typical Source-Drain Diode Forward Voltage
Fig11.
Maximum Safe Operating
Area
3.0
2.5
2.0
1.5
1.0
60
50
40
30
20
10
0
I
I
I
I
I
I
= 25
μ
A
D
D
D
D
D
D
= 100
μ
A
= 150
μ
A
= 250
μ
A
= 1.0mA
= 1.0A
-75 -50 -25
0
25 50 75
100 125 150
25
50
T
75
100
125
150
T
, Temperature ( °C )
J
, Case Temperature (°C)
C
Fig 13.
Typical Threshold Voltage vs. Junction
Fig 12.
Maximum Drain Current vs. Case Temperature
Temperature
250
I
D
TOP
0.82A
1.0A
200
150
100
50
BOTTOM 11A
0
25
50
75
100
125
150
Starting T
, Junction Temperature (°C)
J
Fig 14.
Maximum Avalanche Energy vs. Drain Current
5
May 6, 2014
IRF8327SPbF
Id
Vds
Vgs
L
VCC
DUT
0
Vgs(th)
20K
Qgs1
Qgs2
Qgodr
Qgd
Fig 15a.
Gate Charge Test Circuit
Fig 15b.
Gate Charge Waveform
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
V
R
D.U.T
AS
GS
G
V
DD
–
I
A
20V
t
0.01
Ω
p
I
AS
Fig 16b.
Unclamped Inductive Waveforms
Fig 16a.
Unclamped Inductive Test Circuit
V
R
D
DS
V
DS
90%
V
GS
D.U.T.
R
G
+
V
DD
–
10%
V
GS
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
V
GS
t
t
r
t
t
f
d(on)
d(off)
Fig 17a.
Switching Time Test Circuit
Fig 17b.
Switching Time Waveforms
6
IRF8327SPbF
Driver Gate Drive
P.W.
P
.
W.
D =
D.U.T
Period
Period
+
V
***
=10V
GS
Circuit Layout Considerations
•
Low Stray Inductance
•
Ground Plane
•
Low Leakage Inductance
Current Transformer
–
D.U.
T
. I
W
aveform
SD
+
–
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
–
+
D.U.
T
. V
W
aveform
DS
Diode Recovery
dv/dt
V
DD
*
V
DD
**
Re-Applied
Voltage
•
dv/dt controlled by R
G
R
G
+
–
Body Diode
Forward Drop
•
Driver same type as D.U.T.
•
I
SD
controlled by Duty Factor “D”
•
D.U.T. – Device Under Test
Inductor Curent
I
SD
Ripple
≤
5%
*
Use P-Channel Driver for P-Channel Measurements
**
Reverse Polarity for P-Channel
***
V
GS
= 5V for Logic Level Devices
Fig 18.
Diode Reverse Recovery Test Circuit
for HEXFET
®
Power MOSFETs
DirectFET
®
Board Footprint, SQ Outline
(Small Size Can, Q-Designation).
Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET.
This includes all recommendations for stencil and
substrate designs.
G = GATE
D = DRAIN
S = SOURCE
D
D
D
D
G
S
7
May 6, 2014
IRF8327SPbF
DirectFET
®
Outline Dimension, SQ Outline
(Small Size Can, Q-Designation).
Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET. This includes
all recommendations for stencil and
substrate designs.
DIMENSIONS
METRIC
IMPERIAL
CODE MIN
MAX
MIN
MAX
0.191
0.156
0.112
0.018
0.020
0.032
0.036
0.032
N/A
A
B
C
D
E
F
4.75
3.70
2.75
0.35
0.48
0.78
0.88
0.78
N/A
4.85
3.95
2.85
0.45
0.52
0.82
0.92
0.82
N/A
0.187
0.146
0.108
0.014
0.019
0.031
0.035
0.031
N/A
G
H
J
0.93
2.00
0.59
0.08
0.97
2.10
0.70
0.17
0.037
0.079
0.023
0.003
0.038
0.083
0.028
0.007
K
L
M
P
R
0.020 0.080 0.0008 0.0031
Dimensions are shown in
millimeters (inches)
DirectFET
®
Part Marking
GATE MARKING
LOGO
PART NUMBER
BATCH NUMBER
DATE CODE
Line above the last character of
the date code indicates “Lead-Free”
8
May 6, 2014
IRF8327SPbF
DirectFET
®
T
a
pe & Reel Dimension (Showing component orientation).
F
D
G
H
NOTE: Controlling dimensions in mm Std reel
quantity is 4800 parts. (ordered as IRF8327SPBF).
REEL DIMENSIONS
STANDARD OPTION
(QTY 4800)
IMPERIAL
METRIC
MAX
MIN
CODE
MAX
N.C
MIN
A
B
C
D
E
F
12.992
0.795
0.504
0.059
3.937
N.C
330.0
20.2
12.8
1.5
N.C
N.C
13.2
N.C
N.C
18.4
14.4
15.4
N.C
0.520
N.C
100.0
N.C
N.C
0.724
0.567
0.606
G
H
0.488
0.469
12.4
11.9
LOADED TAPE FEED DIRECTION
B
A
H
E
G
DIMENSIONS
METRIC
MIN
IMPERIAL
NOTE: CONTROLLING
DIMENSIONS IN MM
CODE
MIN
MAX
8.10
4.10
12.30
5.55
4.20
5.20
N.C
MAX
0.319
0.161
0.484
0.219
0.165
0.205
N.C
A
B
C
D
E
F
0.311
0.154
0.469
0.215
0.158
0.197
0.059
0.059
7.90
3.90
11.90
5.45
4.00
5.00
1.50
1.50
G
H
0.063
1.60
9
May 6, 2014
IRF8327SPbF
Qualification Information
†
Consumer
††
Qualification level
(per JEDEC JESD47F
†††
guidelines)
Comments: This family of products has passed JEDEC’s Industrial
qualification. IR’s Consumer qualification level is granted by extension of
the higher Industrial level.
MSL
1
(per JEDEC J-STD-020D
†††
Moisture Sensitivity Level
RoHS Compliant
DFET
)
Yes
Qualification standards can be found at International Rectifier’s web site
Higher qualification ratings may be available should the user have such requirements.
Please contact your International Rectifier sales representative for further information:
Applicable version of JEDEC standard at the time of product release.
Revision History
Date
Comments
•
•
Updated ordering information to reflect the End-Of-life (EOL) of the mini-reel option
(EOL notice #264).
Updated data sheet based on corporate template.
5/6/2014
IR WORLD HEADQUARTERS:
101 N. Sepulveda Blvd., El Segundo, California 90245, USA
10
May 6, 2014
