Infineon-Technologies-IRF8910TRPBF
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IRF8910PbF-1
HEXFET
®
Power MOSFET
V
DS
20
V
1
2
8
S1
G1
D1
R
DS(on) max
(@V
GS
= 10V)
R
DS(on) max
(@V
GS
= 4.5V)
Q
g (typical)
I
D
7
13.4
D1
m
Ω
3
4
6
S2
D2
18.3
7.4
10
5
G2
D2
nC
A
SO-8
Top View
(@T
A
= 25°C)
Features
Industry-standard pinout SO-8 Package
Benefits
Multi-Vendor Compatibility
⇒
Compatible with Existing Surface Mount Techniques
RoHS Compliant, Halogen-Free
MSL1, Industrial qualification
Easier Manufacturing
Environmentally Friendlier
Increased Reliability
Standard Pack
Form
Base Part
Number
Package Type
Orderable Part Number
Quantity
Tube/Bulk
Tape and Reel
95
4000
IRF8910PbF-1
IRF8910TRPbF-1
IRF8910PbF-1
SO-8
Absolute Maximum Ratings
Parameter
Max.
Units
V
DS
Drain-to-Source Voltage
20
± 20
10
V
V
Gate-to-Source Voltage
GS
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
I
I
I
@ T
A
= 25°C
D
D
@ T
A
= 70°C
8.3
82
A
DM
P
P
@T
A
= 25°C
@T
A
= 70°C
Power Dissipation
Power Dissipation
2.0
1.3
W
D
D
Linear Derating Factor
Operating Junction and
0.016
-55 to
+ 150
W/°C
°C
T
J
T
Storage Temperature Range
STG
Thermal Resistance
Parameter
Junction-to-Drain Lead
Junction-to-Ambient
Typ.
–––
Max.
42
Units
°C/W
R
θ
JL
R
θ
JA
–––
62.5
Notes
through
ꢀ
are on page 10
1
IRF8910PbF-1
Static @ T
J
= 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
20 –––
–––
Conditions
V
GS
= 0V, I
D
= 250
μ
A
BV
DSS
ΔΒ
R
DS(on)
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
V
Δ
V
DSS
/ T
J
––– 0.015 –––
––– 10.7 13.4
––– 14.6 18.3
1.65 ––– 2.55
V/°C Reference
to 25°C, I
D
= 1mA
V
GS
= 10V, I
D
= 10A
GS
= 4.5V, I
D
= 8.0A
m
Ω
V
V
GS(th)
Gate Threshold Voltage
V
V
DS
= V
GS
, I
D
= 250
μ
A
Δ
I
DSS
Δ
V
GS(th)
/ T
J
Gate Threshold Voltage Coefficient
Drain-to-Source Leakage Current
–––
–––
–––
–––
–––
24
-4.8
–––
–––
–––
––– mV/°C
1.0
150
100
μ
A V
DS
= 16V, V
GS
= 0V
V
DS
= 16V, V
GS
= 0V, T
J
= 125°C
GS
= 20V
I
GSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Forward Transconductance
Total Gate Charge
nA
S
V
––– -100
V
GS
= -20V
gfs
Q
g
–––
7.4
2.4
–––
11
V
DS
= 10V, I
D
= 8.2A
–––
–––
Q
gs1
Pre-Vth Gate-to-Source Charge
Post-Vth Gate-to-Source Charge
Gate-to-Drain Charge
–––
V
DS
= 10V
Q
gs2
Q
gd
––– 0.80 –––
nC V
GS
= 4.5V
I
D
= 8.2A
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
2.5
1.7
3.3
4.4
6.2
10
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Q
godr
Gate Charge Overdrive
Switch Charge (Q
gs2
+ Q
gd
)
See Fig. 6
Q
sw
Q
oss
t
d(on)
t
r
Output Charge
nC
V
DS
= 10V, V
GS
= 0V
Turn-On Delay Time
Rise Time
V
DD
= 10V, V
GS
= 4.5V
ns I
D
= 8.2A
Clamped Inductive Load
t
d(off)
t
f
Turn-Off Delay Time
Fall Time
9.7
4.1
960
300
160
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
V
GS
= 0V
pF V
DS
= 10V
ƒ = 1.0MHz
Avalanche Characteristics
Parameter
Typ.
–––
–––
Max.
Units
mJ
Single Pulse Avalanche Energy
E
AS
I
AR
19
Avalanche Current
8.2
A
Diode Characteristics
Parameter
Min. Typ. Max. Units
Conditions
I
S
Continuous Source Current
–––
–––
2.5
MOSFET symbol
D
(Body Diode)
Pulsed Source Current
A
showing the
integral reverse
G
I
SM
–––
–––
82
S
(Body Diode)
p-n junction diode.
V
SD
t
rr
Diode Forward Voltage
–––
–––
–––
–––
17
1.0
26
V
T =
25°C, I
= 8.2A, V
= 0V
J S
GS
Reverse Recovery Time
Reverse Recovery Charge
ns T
= 25°C, I
= 8.2A, V
DD
= 10V
J F
Q
rr
di/dt = 100A/
μ
s
6.5
9.7
nC
2
June 30, 2014
IRF8910PbF-1
100
10
1
100
10
VGS
10V
VGS
10V
TOP
TOP
8.0V
5.5V
4.5V
3.5V
3.0V
2.8V
2.5V
8.0V
5.5V
4.5V
3.5V
3.0V
2.8V
2.5V
BOTTOM
BOTTOM
1
2.5V
0.1
0.01
2.5V
1
60
μ
s PULSE WIDTH
≤
60
μ
s PULSE WIDTH
≤
Tj = 25°C
Tj = 150°C
0.1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
DS
V
, Drain-to-Source Voltage (V)
DS
Fig 2.
Typical Output Characteristics
Fig 1.
Typical Output Characteristics
100
1.5
1.0
0.5
I
= 10A
D
V
= 10V
GS
10
1
T
= 150°C
J
T
3
= 25°C
J
V
= 10V
DS
≤
60
μ
s PULSE WIDTH
0.1
1
2
4
5
6
-60 -40 -20
0
20 40 60 80
100 120 140 160
T
J
, Junction Temperature (°C)
V
, Gate-to-Source Voltage (V)
GS
Fig 4.
Normalized On-Resistance
Fig 3.
Typical Transfer Characteristics
vs
.
T
emperature
3
June 30, 2014
IRF8910PbF-1
10000
1000
100
6.0
5.0
4.0
3.0
2.0
1.0
0.0
V
= 0V,
= C
f = 1 MHZ
GS
I =
8.2A
D
C
C
C
+ C
, C
SHORTED
iss
gs
gd
ds
= C
V
V
= 16V
= 10V
rss
oss
gd
= C
+ C
DS
DS
ds
gd
C
iss
C
oss
C
rss
1
10
100
0
1
2
3
4
5
6
7
8
9
10
V
, Drain-to-Source Voltage (V)
Q
Total Gate Charge (nC)
DS
G
Fig 6.
Typical Gate Charge Vs.
Fig 5.
Typical Capacitance vs.
Gate-to-Source Voltage
Drain-to-Sourc
e
V
oltage
100.00
10.00
1.00
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
T
= 150°C
J
100
μ
sec
1msec
T
= 25°C
J
0.10
10msec
1
T
= 25°C
A
Tj = 150°C
Single Pulse
V
= 0V
1.4
GS
0.01
0.1
0.2
0.4
V
0.6
0.8
1.0
1.2
1.6
0
1
10
100
, Source-to-Drain Voltage (V)
V
, Drain-to-Source Voltage (V)
SD
DS
Fig 8.
Maximum Safe Operating Area
Fig 7.
Typical Source-Drain Diode
Forward Voltage
4
IRF8910PbF-1
2.5
2.0
1.5
1.0
10
9
8
7
6
5
4
3
2
1
0
I
= 250
μ
A
D
-75 -50 -25
0
25
50
75 100
125 150
25
50
75
100
125
150
T ,
Temperature ( °C )
J
T
, Ambient Temperature (°C)
A
Fig 9.
Maximum Drain Current vs.
Fig 10.
Threshold Voltage vs. Temperature
Ambien
t
T
emperature
100
10
D = 0.50
0.20
0.10
0.05
Ri (°C/W)
τ
i (sec)
R
1
R
1
R
2
R
2
R
3
R
3
R
4
R
4
R
5
R
5
0.02
0.01
1.2647
2.0415
18.970
23.415
16.803
0.000091
0.000776
0.188739
0.757700
25.10000
1
τ
τ
J
τ
J
τ
C
τ
τ
1
τ
1
τ
τ
τ
2
τ
2
3
τ
3
4
τ
4
5
τ
5
Ci=
τ
i
/
Ri
Ci=
τ
i
/
Ri
0.1
0.01
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthja + Tc
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
10
100
t
, Rectangular Pulse Duration (sec)
1
Fig 11.
Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
5
June 30, 2014
IRF8910PbF-1
40.00
30.00
20.00
10.00
0.00
80
70
60
50
40
30
20
10
0
I
I
= 10A
D
D
TOP
3.4A
4.9A
BOTTOM 8.2A
T
= 125°C
J
T
= 25°C
J
3
4
5
6
7
8
9
10
25
50
75
100
125
150
Starting T
, Junction Temperature (°C)
J
V
Gate -to -Source Voltage
(V)
GS,
Fig 13.
Maximum Avalanche Energy
Fig 12.
On-Resistance vs. Gate Voltage
vs. Drain Current
Current Regulator
Same Type as D.U.
T
.
V
(BR)DSS
t
15V
p
50K
Ω
.2
μ
F
12V
.3
μ
F
DRIVER
+
L
V
DS
+
V
DS
D.U.
T
.
–
D.U.T
AS
R
G
V
DD
–
I
A
V
GS
2
V
G
S
Ω
0.01
t
p
I
AS
3mA
I
I
D
G
Fig 14.
Unclamped Inductive Test Circuit
Current Sampling Resistors
an
d
W
aveform
Fig 15.
Gate Charge Test Circuit
L
D
V
DS
V
DS
90%
+
–
V
DD
D.U.T
10%
V
GS
V
GS
Pulse Width < 1
μ
s
Duty Factor < 0.1%
t
d(on)
t
d(off)
t
r
t
f
Fig 17.
Switching Time Waveforms
Fig 16.
Switching Time Test Circuit
6
June 30, 2014
IRF8910PbF-1
Driver Gate Drive
P.W.
P
.
W.
D =
D.U.T
Period
Period
+
–
*
=10V
V
GS
Circuit Layout Considerations
•
Low Stray Inductance
•
Ground Plane
•
Low Leakage Inductance
Current Transformer
D.U.
T
. I
W
aveform
SD
+
–
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
–
+
D.U.
T
. V
W
aveform
DS
Diode Recovery
dv/dt
V
DD
V
DD
Re-Applied
Voltage
•
dv/dt controlled by R
G
R
G
+
–
Body Diode
Forward Drop
•
Driver same type as D.U.T.
•
I
SD
controlled by Duty Factor “D”
•
D.U.T. – Device Under Test
Inductor Curent
I
SD
Ripple
≤
5%
*
V
GS
= 5V for Logic Level Devices
Fig 15.
Peak Diode Recovery dv/dt Test Circuit
for N-Channel
HEXFET
®
Power MOSFETs
Id
Vds
Vgs
Vgs(th)
Qgs1
Qgs2
Qgd
Qgodr
Fig 16.
Gate Charge Waveform
7
June 30, 2014
IRF8910PbF-1
Power MOSFET Selection for Non-Isolated DC/DC Converters
Synchronous FET
Control FET
The power loss equation for Q2 is approximated
by;
Special attention has been given to the power losses
in the switching elements of the circuit – Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FE
T
,
a
re impacted by the R
ds(on)
of the
MOSFE
T
,
b
ut these conduction losses are only about
one half of the total losses.
P
=
P
+
P
+
P
*
loss
conduction
drive
output
P
=
I
rms
2
×
R
ds(on)
loss
( )
Power losses in the control switch Q1 are given
by;
+
Q
×
V
×
f
(
)
g
g
⎛
⎜
Q
oss
⎞
⎠
P
loss
= P
conduction
+ P
switching
+ P
drive
+ P
output
+
×
V
×
f
+
Q
×
V
×
f
(
)
in
rr
in
⎝
2
This can be expanded and approximated by;
*dissipated primarily in Q1.
P
=
I
2
×
R
ds
(
on )
(
)
loss
rms
For the synchronous MOSFET Q2, R
ds(on)
is an im-
portant characteristic; however, once again the im-
portance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con-
trol IC so the gate drive losses become much more
significant. Secondl
y
,
t
he output charge Q
oss
and re-
verse recovery charge Q
rr
both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFE
T
s
’ susceptibility to Cdv/dt turn on.
⎛
⎛
Q
gd
i
g
⎞
Q
g
s
2
i
g
⎞
⎟
⎜
⎟
⎜
+
I
×
×
V
×
f
+
I
×
×
V
×
f
in
in
⎝
⎠
⎝
⎠
+
Q
×
V
×
f
(
)
g
g
⎛
Q
oss
⎞
⎠
+
×
V
×
f
in
⎝
2
This simplified loss equation includes the terms Q
gs2
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be-
tween ground and V
in
. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is ca-
pacitively coupled to the gate of
Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Q
gd
/Q
gs1
must be minimized to reduce the
potential for Cdv/dt turn on.
and Q
oss
which are new to Power MOSFET data sheets.
Q
gs2
is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Q
gs1
and Q
gs2
, can be seen from
Fig 16.
Q
gs2
indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached
and the time the drain cur-
rent rises to I
dmax
at which time the drain voltage be-
gins to change. Minimizing Q
gs2
is a critical factor in
reducing switching losses in Q1.
Q
oss
is the charge that must be supplied to the out-
put capacitance of the MOSFET during every switch-
ing cycle. Figure A shows how Q
oss
is formed by the
parallel combination of the voltage dependant (non-
linear) capacitances C
ds
and C
dg
when multiplied by
the power supply input buss voltage.
Figure A:
Q
oss
Characteristic
8
IRF8910PbF-1
SO-8 Package Outline
(Mosfet & Fetky)
Dimensions are shown in milimeters (inches)
IN
C
H
ES
M
I
LLI
M
E
TERS
DIM
D
B
M
I
N
.0532
A1
.
0040
MAX
.0688
.0098
.020
M
I
N
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
5
A
A
E
b
c
D
E
.013
8
1
7
2
6
3
5
.0075
.189
.0098
.1968
.1574
6
H
0.25 [.010]
A
.1497
4
e
.050 B
A
S
I
C
1.27
B
A
S
IC
e1
.
025
B
A
S
I
C
0.635
B
A
S
I
C
H
K
L
.2284
.0099
.016
0°
.2440
.0196
.050
8°
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
e
6X
y
e1
A
K x 45°
A
C
y
0.10 [.004]
8X c
A1
B
8X L
8X b
0.25 [.010]
7
C
F
O
O
T
P
RINT
NO
T
ES:
1. DIMEN
S
I
ONING
&
T
O
L
ER
A
NCING P
E
R
A
S
M
E Y14.5
M
–
1994.
2.
C
ON
T
R
O
L
LIN
G
D
IMENSI
O
N:
MI
L
LI
M
E
TER
8X 0.72 [.028]
3. DIMEN
S
I
ONS
A
R
E SH
O
WN
I
N MI
L
LI
M
E
TERS
[
IN
C
H
ES
]
.
4.
O
U
T L
I
NE
CONF OR MS
T O J
E
DE C
O
U T L
I
NE
MS -012
A
A.
5
6
7
DIMEN
S
I
ON DO
E
S
N
OT INC
L
U
D
E MO
L
D PR
O
T
R
USI
O
N
S
.
MO
L
D PR
O
T
RUSI
O
NS NOT
T
O
EX
C
E
ED
0
.15 [.006].
DIMEN
S
I
ON DO
E
S
N
OT INC
L
U
D
E MO
L
D PR
O
T
R
USI
O
N
S
.
MO
L
D PR
O
T
RUSI
O
NS NOT
T
O
EX
C
E
ED
0
.25 [.010].
6.46 [.255]
DIMEN
S
I
ON IS
T
HE LE
N
GT
H OF
L
E
A
D
F
O
R
S
O
L
D
E
RING TO
AS
U
BSTR
A
T
E.
3X 1.27 [.050]
8X 1.78 [.070]
SO-8 Part Marking Information
E
X
A
M
P
LE: THIS IS
A
N
I
RF
7
101 (MO
S
FET)
DAT E
CODE (YWW)
P =
DI
S
G
N
A
T
ES LE
A
D
–
F
REE
PR
O
D
U
C
T (O
P
T
I
O
N
A
L
)
Y =
L
A
S
T
D
I
G
I
T
O
F
T
HE YE
A
R
WW =
W
E
E K
A=
A
S
SE
M
B
LY
SITE
C
O
D
E
XXXX
F
7
101
IN
T
ER
N
A
T
I
O
N
A
L
RE
C
T
IFIER
L
O
GO
L
O
T CODE
P
A
R
T NU
M
B
ER
9
IRF8910PbF-1
SO-8 Tape and Reel
(Dimensions are shown in milimeters (inches))
TERMINAL NUMBER 1
12.3 ( .484 )
11.7 ( .461 )
8.1 ( .318 )
7.9 ( .312 )
F
E
ED DIRECTION
NOTES:
1. CONTROLLING
DIMENSION : MILLIMETER.
2. ALL
DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES).
3. OUTLINE
CONFORMS TO EIA-481 & EIA-541.
330.00
(12.992)
MAX.
14.40 ( .566 )
12.40 ( .488 )
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
Notes:
Repetitive rating;
pulse width limited by max. junction temperature.
Starting T
J
= 25°C, L = 0.57mH, R
G
= 25
Ω
, I
AS
= 8.2A.
Pulse width
≤
400
μ
s; duty cycle
≤
2%.
When mounted on 1 inch square
copper board.
ꢀ
R
is measured at
T
J
of approximately 90°C.
θ
Qualification information
†
I
n
du
s
t
r
i
a
l
(
p
er
J
E
D
E
C JES
D
47
F
††
g
u
i
d
e
l
in
e
s
)
Qualification level
MS L 1
Moisture Sensitivity Level
RoHS
c
o
m
pliant
SO-8
(
p
er
J
E
D
E
C J-S T
D
-020D
††
Yes
)
Qualification standards can be found at International Rectifier’s web site:
http://www.irf.com/product-info/reliability
††
Applicable version of JEDEC standard at the time of product release
IR WORLD HEADQUARTERS:
101 N. Sepulveda Blvd., El Segundo, California 90245, USA
10
June 30, 2014
